mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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final version?
This commit is contained in:
Zane Kaminski
parent
aa30aa8a55
commit
8631b52104
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|
||||
(property "LCSC Part" "C23182" (at 146.05 121.92 0)
|
||||
(property "LCSC Part" "C23182" (at 146.05 119.38 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid cd9bf5a8-7226-4f49-a738-e9b34ab17a2e))
|
||||
|
||||
@ -182,30 +182,23 @@ The Ready signals are always high during ROM access so all ROM accesses complete
|
||||
|
||||
<h3 id="t5">5. Back-to-Back RAM Access</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x..2............x..2............x......', phase: 0.00, period: 0.5, data:['000000-3FFFFF','000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x....2..........x....2..........x......', phase: 0.00, period: 0.5, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........x1....x0........x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '2.0.x.1...........0.x.1...........0.x.2', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '201..01..0', phase: 0.00, period: 2.0},
|
||||
{name: 'DS (RD)', wave: '1...x0........x1....x0........x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1.0.1.0.1.', phase:-0.10, period: 2.0},
|
||||
{name: 'DS (WR)', wave: '1.......x0....x1........x0....x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0...x.1.......x.0...x.1......', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady',wave: '1.........', phase: 0.00, period: 2},
|
||||
{name: 'DTACK', wave: '210..10..1', phase:-0.10, period: 2},
|
||||
{name: 'DTACKr', wave: '2.10..10..', phase: 0.00, period: 2},
|
||||
{name: 'D (FPMR)',wave: 'z.........x.2.xz..........x.2.xz.......', phase: 0.05, period: 0.5},
|
||||
{name: 'D (EDOR)',wave: 'z.........x.2...xz........x.2...xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'D (WR)', wave: 'z.....x.2.......xz....x.2.......xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'RS', wave: '2222222222', phase: 0.00, period: 2, data:[0,0,1,2,3,0,1,2,3,0]},
|
||||
{name: 'RASEN', wave: '1..0.1.0.1', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.01..01..', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1..01..01.', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '1...x.0.......x1....x.0.......x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.1.0.', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2..x2..x.', phase: 0.25, period: 2, data:['000000-3FFFFF','000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x..1....x..1....x...', phase: 0.25, period: 1, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........x1....x0........x1....x2.', phase:-0.25, period: 0.5},
|
||||
{name: 'DS (RD)', wave: '1...x0........x1....x0........x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1.......x0....x1........x0....x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0...x.1.......x.0...x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'Ready', wave: 'x10.x10.x.', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: '1.0..10..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z....x2.z....x2.z...', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z......x.2......z......x.2......z......', phase:-0.30, period:0.5},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,5,6,7,0]},
|
||||
{name: 'RAS', wave: '1...x.0.......x.1...x.0.......x.1......', phase:-0.35, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......x....2..x2......x......', phase:-0.20, period:0.5, data:['row','col','row','col']},
|
||||
{name: 'CAS', wave: '1..01..01.', phase: 0.90, period: 2},
|
||||
]}</script><p>
|
||||
{name: 'CAS', wave: '1..0.1.0.1', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram introduces the DRAM access timing.
|
||||
</p><p>
|
||||
At 25 MHz for a 4-clock read cycle, there are only 2.5 clock cycles (100 ns) between
|
||||
@ -221,149 +214,112 @@ which outputs row addresses to the DRAM array when RASEL is low and column addre
|
||||
The /CAS signal is a function of RASEL. RASEL changes after FCLK rises. If RASEL is high at the next falling edge, /CAS is asserted.
|
||||
Otherwise if RASEL is low, /CAS is deasserted at the next falling edge.
|
||||
</p><p>
|
||||
"RS" is the RAM state. The RS state changes after the rising edge of the clock
|
||||
and can take on values 0-7. <br/>
|
||||
In RS0, the RAM is considered to be idle. <br/>
|
||||
At the rising edge of the clock in RS0 a RAM cycle begins if, if /AS is asserted,
|
||||
a RAM address is present, and a RAM cycle has not already occurred for this /AS cycle. <br/>
|
||||
In this case, we know that /RAS has been active for at least 10 nanoseconds, so RASEL is brogught high. <br/>
|
||||
This switches the RA bus from row to column addresses and RS0 transitions to RS5. <br/>
|
||||
At the falling edge in the middle of RS5, /CAS is brought low. RS5 always transitions to RS6. <br/>
|
||||
At the end of RS6, RASEL is brought low again, switching the RA multiplexers back to row addresses
|
||||
in preparation for the next DRAM access cycle. RS6 always transitions to RS7. <br/>
|
||||
RS7 is the state in which a RAM access or refresh is concluded. At the falling edge in the middle of RS7, /CAS is brought high. <br/>
|
||||
RS7 transitions to RS2 if a refresh request is pending, otherwise RS7 transitions to RS0. <br/>
|
||||
The states RS1 and RS2-RS4 will be discussed in association with the subsequent refresh cycle diagrams. <br/>
|
||||
The RS and RAMCS signals are used to generate the Ready0 ready signal input to the FSB.
|
||||
Ready0 is high if and only if RS==0 and RAMCS is active.<br/>
|
||||
</p><p>
|
||||
Also notice how, during write cycles,
|
||||
it is undefined whether the cycle is conducted as an "early write" or an "OE-controlled write" cycle. <br/>
|
||||
/OE is held high at all times during write cycles,
|
||||
but /LWE and /UWE are asynchronous functions of MC68k's /LDS and /UDS signals. <br/>
|
||||
It is undefined during a write cycle whether /LWE and /UWE will go low before or after /CAS falls. <br/>
|
||||
Since /OE is held high during write cycles, the order of the /WE signals and /CAS is of no consequence.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t6">6. Long-running RAM Access</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: 'x..2............................x......', phase: 0.00, period: 0.5, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x....2..........................x......', phase: 0.00, period: 0.5, data:['read or write']},
|
||||
{name: 'AS', wave: '1...x0........................x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '2.0.x.1...........................0.x.2', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '201......0', phase: 0.00, period: 2.0},
|
||||
{name: 'DS (RD)', wave: '1...x0........................x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1.0.....1.', phase:-0.10, period: 2.0},
|
||||
{name: 'DS (WR)', wave: '1.......x0....................x1....x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......x.0.....x1.....................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady',wave: '1.........', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '21....0..1', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '2.1....0..', phase: 0.00, period: 2.0},
|
||||
{name: 'D (RD)', wave: 'z.........x.2...................xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'D (WR)', wave: 'z.....x.2.......................xz.....', phase: 0.05, period: 0.5},
|
||||
{name: 'RS', wave: '2222222222', phase: 0.00, period: 2.0, data:[0,0,1,2,2,2,2,2,3,0]},
|
||||
{name: 'RASEN', wave: '1..0.....1', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.01......', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1..01.....', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '1...x.0.......x1....................x2.', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.....', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: 'x...2...x2......x2..............x......', phase: 0.00, period: 0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1..0....1.', phase: 0.90, period: 2.0},
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2......x.', phase: 0.25, period: 2, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x..1............x...', phase: 0.25, period: 1, data:['read or write','read or write']},
|
||||
{name: 'AS', wave: '1...x0........................x1.......', phase:-0.25, period: 0.5},
|
||||
{name: 'Ready', wave: '0....1....', phase:-0.20, period: 2},
|
||||
{name: 'DTACK', wave: '1.....0..1', phase:-0.20, period: 2},
|
||||
{name: 'D (RD)', wave: 'z....x2..z..........', phase:-0.30},
|
||||
{name: 'D (WR)', wave: 'z..x2...........z...', phase: 0.00},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,0,5,6,7,0,0,0,0,0]},
|
||||
{name: 'RAS', wave: '1...x.0.......................x.1......', phase:-0.25, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.1.0.....', phase:-0.20, period: 2},
|
||||
{name: 'RA', wave: 'x...x2..x2......2...............x........', phase:-0.20, period:0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1..0.1....', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram shows the timing for a long-running RAM access, in which the RAM read or write completes sooner than MC68k removes /AS.
|
||||
This diagram shows the timing for a long-running RAM access,
|
||||
in which the RAM read or write completes sooner than MC68k removes /AS. <br/>
|
||||
</p><p>
|
||||
There are cases in which a DRAM access completes in time for termination of a 4-clock bus cycle,
|
||||
but the bus cycle is lengthened because not all of the Ready signals to the FSB controller have gone high. <br/>
|
||||
If RS0 is returned to after a DRAM access but /AS remains asserted,
|
||||
then the DRAM must not enter RS5-7 and thus not initiate any additional /CAS cycles. <br/>
|
||||
Notice how /CAS goes high in the middle of RS7 but /RAS stays low until the end of the /AS cycle.
|
||||
Using EDO DRAM allows the data bus output to be maintained while /RAS is low. <br/>
|
||||
However, if FPM DRAM is used or if a refresh cycle occurs before /AS rises,
|
||||
then maintenance of read data on the data bus falls to the bus capacitance and the bus hold resistors. <br/>
|
||||
Therefore it is best not to prolong DRAM read cycles, even when using EDO DRAM, so that there is no possibility of
|
||||
an intervening DRAM refresh cycle causing the data outputs to tristate. <br/>
|
||||
Fortunately, although DRAM write cycles shadowed to main sound and video memory need to be extended
|
||||
when the posted write FIFO is full, there is no need to extend DRAM read cycles. <br/>
|
||||
Therefore we do not attempt to extend the /CAS pulse to fix this problem until /AS rises since the /CAS pulse
|
||||
could be interrupted by a refresh cycle anyway. <br/>
|
||||
To fix this problem, we could extend the /CAS pulse until /AS is high and have the
|
||||
DRAM controller conform to the DRAM "hidden refresh" protocol but it is not necessary.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t7">7. Refresh During Idle</h3><script type="WaveDrom">{signal: [
|
||||
{name: 'MCLK', wave: 'p.......', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: 'x...............................', phase: 0.00, period: 0.5, data:['000000-3FFFFF']},
|
||||
{name: 'RW', wave: 'x...............................', phase: 0.00, period: 0.5, data:['read or write']},
|
||||
{name: 'AS', wave: '1...............................', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '1...............................', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '1.......', phase: 0.00, period: 2.0},
|
||||
{name: 'DS', wave: '1...............................', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1.......', phase:-0.10, period: 2.0},
|
||||
{name: 'WE (WR)', wave: '1...............................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady', wave: '1.......', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '1.......', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '1.......', phase: 0.00, period: 2.0},
|
||||
{name: 'RS', wave: '22222222', phase: 0.00, period: 2.0, data:[0,0,4,5,6,7,0,0]},
|
||||
{name: 'RASEN', wave: '1.0...1.', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.0.1...', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1.......', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '1.......x0......x1..............', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '0.......', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: 'x...............................', phase: 0.00, period: 0.5, data:['row','col','row']},
|
||||
{name: 'CAS', wave: '1.0.1...', phase: 0.90, period: 2.0},
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '1............', phase:-0.75},
|
||||
{name: 'RS', wave: '2222222', phase:-0.2, period: 2, data:[0,0,2,3,4,7,0,0,0]},
|
||||
{name: 'RefReq', wave: '01..0..', phase:-0.2, period: 2},
|
||||
{name: 'RASEN', wave: '1.0...1', phase:-0.2, period: 2},
|
||||
{name: 'RRAS', wave: '1.....0...1...', phase:-0.20},
|
||||
{name: 'RAS', wave: '1.....0...1...', phase:-0.40},
|
||||
{name: 'CAS', wave: '1..0.1.', phase: 0.80, period: 2},
|
||||
]}</script><br/><p>
|
||||
This diagram shows the timing of a refresh occurring after the bus and DRAM are and have been idle for at least one clock cycle.
|
||||
</p>
|
||||
</p><p>
|
||||
RAM states RS2, RS3, RS4, and RS7 are used for refresh. <br/>
|
||||
RS2-RS4 implement the main refresh behavior. <br/>
|
||||
When a refresh request is pending at the rising edge ending RS0 or RS7 while /RAS is inactive,
|
||||
RASEN is brought low and RS2 is entered. <br/>
|
||||
With RASEN low, /AS activity does not cause a /RAS pulse and the DRAM controller uses the registered /RRAS signal
|
||||
to initiate refresh cycles. <br/>
|
||||
At the falling edge in the middle of RS2, /CAS is activated. Then at the rising edge concluding RS2, /RAS is activated
|
||||
and RS2 transitions to RS3. <br/>
|
||||
In RS3, /RAS and /CAS remain active, and RS3 transitions to RS4.
|
||||
RS3 and RS4 serve to implement the requisite /RAS pulse width for a refresh. <br/>
|
||||
At the falling edge in the middle of RS4, /CAS is deactivated. Then at the rising edge concluding RS4, /RAS is deactivated
|
||||
and RS4 transitions to RS7. <br/>
|
||||
RREQ is cleared after the first rising edge on which RefRAS is active.<br/>
|
||||
In RS7, /RAS and /CAS remain inactive. RS7 serves to implement the requisite RAS precharge time between DRAM cycles.<br/>
|
||||
RASEN is brought high again after the rising edge concluding RS7 and RS7 transitions to RS0 and the DRAM is considered idle again.<br/>
|
||||
</p><p>
|
||||
Also notice how a RASEN can only be disabled if /RAS is high or if a DRAM cycle is complete, otherwise
|
||||
there may be a tRAS timing violation. This constrains the timing of a refresh.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t8">8A. Refresh Immediately Following DRAM Access - Idle afterwards</h3>
|
||||
<h3 id="t8">8. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p............', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'RW', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'AS', wave: '0.x1................................................', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '1.....0.............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '1.0..........', phase: 0.00, period: 2.0},
|
||||
{name: 'DS', wave: '0.x1................................................', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '01...........', phase:-0.10, period: 2.0},
|
||||
{name: 'WE (WR)', wave: '2.x.1...............................................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady', wave: '1............', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '0.1..........', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '0..1.........', phase: 0.00, period: 2.0},
|
||||
{name: 'RS', wave: '2222222222222', phase: 0.00, period: 2.0, data:[2,3,4,5,6,7,0,0,0,0,0,0,0]},
|
||||
{name: 'RASEN', wave: '0.....1......', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.0.1........', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1............', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '2.x1....x0......x1..................................', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '20...........', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'CAS', wave: '010.1........', phase: 0.90, period: 2.0},
|
||||
]}
|
||||
</script><br/>
|
||||
|
||||
|
||||
<h3 id="t8">8B. Refresh Immediately Following DRAM Access - RAM access immediately afterwards</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p............', phase: 0.00, period: 2.0},
|
||||
{name: 'A', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'RW', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'AS', wave: '0.x1....x0..........................................', phase:-0.10, period: 0.5},
|
||||
{name: 'BACT', wave: '1.....0.x.1.........................................', phase: 0.00, period: 0.5},
|
||||
{name: 'BACTr', wave: '1.01.........', phase: 0.00, period: 2.0},
|
||||
{name: 'DS (RD)', wave: '0.x1....x0..........................................', phase:-0.10, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '0.x1........x0......................................', phase:-0.10, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '010..........', phase:-0.10, period: 2.0},
|
||||
{name: 'WE (WR)', wave: '2.x..1......................x0......................', phase:-0.10, period: 0.5},
|
||||
{name: 'RAMReady', wave: '1............', phase: 0.00, period: 2.0},
|
||||
{name: 'DTACK', wave: '0.1..........', phase:-0.10, period: 2.0},
|
||||
{name: 'DTACKr', wave: '0..1.........', phase: 0.00, period: 2.0},
|
||||
{name: 'RS', wave: '2222222222222', phase: 0.00, period: 2.0, data:[2,3,4,5,6,7,0,1,2,3,0,0,0]},
|
||||
{name: 'RASEN', wave: '0.....1......', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrr', wave: '1.0.1..01....', phase: 0.00, period: 2.0},
|
||||
{name: 'RASrf', wave: '1.......01...', phase: 1.00, period: 2.0},
|
||||
{name: 'RAS', wave: '2.x1....x0......x1......x0........x1................', phase:-0.10, period: 0.5},
|
||||
{name: 'RASEL', wave: '20.....1.0...', phase: 0.00, period: 2.0},
|
||||
{name: 'RA', wave: '2...x...............................................', phase: 0.00, period: 0.5},
|
||||
{name: 'CAS', wave: '010.1...01...', phase: 0.90, period: 2.0},
|
||||
]}
|
||||
</script><br/>
|
||||
|
||||
|
||||
<h3 id="t8">9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....................x0..', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[2,3,4,5,6,7,0]},
|
||||
{name: 'RASEN', wave: '0.....1', phase: 0.00, period: 2},
|
||||
{name: 'RASrr', wave: '1.0.1..', phase: 0.00, period: 2},
|
||||
{name: 'RASrf', wave: '01.....', phase: 1.00, period: 2},
|
||||
{name: 'RAS', wave: '0x1....x0......x1.......x0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0....1.', phase: 0.80, period: 2},
|
||||
{name: 'RASEL', wave: '0...1..', phase: 0.00, period: 2},
|
||||
]}
|
||||
</script><br/>
|
||||
|
||||
|
||||
<h3 id="t8">10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....x0..................', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[2,3,4,5,6,7,0]},
|
||||
{name: 'RASEN', wave: '0.....1', phase: 0.00, period: 2},
|
||||
{name: 'RASrr', wave: '1.0.1..', phase: 0.00, period: 2},
|
||||
{name: 'RASrf', wave: '01.....', phase: 1.00, period: 2},
|
||||
{name: 'RAS', wave: '0x1....x0......x1......x.0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0....1.', phase: 0.80, period: 2},
|
||||
{name: 'RASEL', wave: '0...1..', phase: 0.00, period: 2},
|
||||
{name: 'MCLK', wave: 'p...', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.x1....x.......', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222', phase:-0.20, period: 2, data:[6,7,2,3,4]},
|
||||
{name: 'RefReq', wave: '21..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0.', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.x.1.......0..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of a refresh occurring immediately after a RAM access cycle.
|
||||
@ -379,6 +335,113 @@ The purpose of this diagram is mainly to demonstrate that adequate /RAS and /CAS
|
||||
after the previous DRAM access is terminated before /RAS is pulsed for refresh.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t9">9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated While Refresh In-Progress</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.............x1....x......', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[6,7,2,3,4,7,0,0,0,0]},
|
||||
{name: 'RefReq', wave: '21..0..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0...1', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0.1.', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.......1...0.......1...x..', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10.1.', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs during a long-running DRAM access
|
||||
and the /AS cycle terminates before the refresh ends.
|
||||
</p><p>
|
||||
It is possible for a DRAM access cycle to be extended for a long time, during which the DRAM may be deprived of refresh. <br/>
|
||||
Therefore we must provide for the case where a DRAM access completes and a refresh begins but before /AS ever goes high. <br/>
|
||||
In this case, the rising edge of RASEN causes /RAS to go inactive, as opposed to the rising edge of /AS. <br/>
|
||||
Therefore, the /RAS precharge pulse width in this case is much shorter than
|
||||
a refresh occurring during idle or immediately following a DRAM access. <br/>
|
||||
At 25 MHz, the /RAS precharge width is only 40ns. This is the minimum tRP for 60ns DRAM and is the tightest timing parameter in the Warp-SE. <br/>
|
||||
We could purpose RS1 to add additional precharge time if necessary.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t10">10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated After Refresh Completes</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p........', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0.........................x1....x...', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '222222222', phase:-0.20, period: 2, data:[6,7,2,3,4,7,0,0,0]},
|
||||
{name: 'RefReq', wave: '21..0....', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1.0.....1', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1..0.1...', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0.......1...0.......1...........x...', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.10.1...', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs during a long-running DRAM access
|
||||
and the /AS cycle does not terminate before the refresh ends.
|
||||
</p><p>
|
||||
This case is similar to the previous but there is a key difference.
|
||||
/AS does not rise until after the refresh cycle completes. <br/>
|
||||
Therefore if RASEN were brought high upon exit from RS7 into RS0, there may be an improperly-short /RAS pulse
|
||||
terminated by the rising edge of the /AS. <br/>
|
||||
Consequently RASEN enablement is held off the first rising edge during which BACT is low.
|
||||
</p>
|
||||
|
||||
<h3 id="t11">11. Refresh in the "Middle" of DRAM Access</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p......', phase: 0.00, period: 2},
|
||||
{name: 'AS', wave: '0...........................', phase:-0.25, period:0.5},
|
||||
{name: 'RS', wave: '2222222', phase:-0.20, period: 2, data:[6,7,0,0,0,2,3]},
|
||||
{name: 'RefReq', wave: '0...1..', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '1....0.', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1.....0', phase:-0.20, period:2},
|
||||
{name: 'RAS', wave: '0...................1...0...', phase:-0.40, period:0.5},
|
||||
{name: 'CAS', wave: '0.1...0', phase: 0.80, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the case where a refresh request occurs in the "middle" of a long-running DRAM access. <br/>
|
||||
The remainder of the timing is given by diagrams 9 or 10.
|
||||
</p>
|
||||
|
||||
<h3 id="t12">12. Concurrent DRAM Access and Refresh Requests</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'MCLK', wave: 'p.........', phase: 0.00, period: 2},
|
||||
{name: 'A', wave: 'x2......x.', phase: 0.25, period: 2, data:['000000-4FFFFF']},
|
||||
{name: '/AS', wave: '1..x0........................x1........', phase:-0.75, period: 0.5},
|
||||
{name: 'DTACK', wave: '1.....0..1', phase:-0.30, period: 2},
|
||||
{name: 'DS (RD)', wave: '1..x0........................x1.......', phase:-0.75, period: 0.5},
|
||||
{name: 'OE (RD)', wave: '1...x.0......................x.1.....', phase:-0.75, period: 0.5},
|
||||
{name: 'DS (WR)', wave: '1......x0....................x1.......', phase:-0.75, period: 0.5},
|
||||
{name: 'WE (WR)', wave: '1.......................0....x.1......', phase:-0.75, period: 0.5},
|
||||
{name: 'RS', wave: '2222222222', phase:-0.20, period: 2, data:[0,2,3,4,7,0,5,6,7,0]},
|
||||
{name: 'Ready0', wave: 'x0...10.x.', phase:-0.20, period: 2},
|
||||
{name: 'RefReq', wave: '1..0......', phase:-0.20, period: 2},
|
||||
{name: 'RASEN', wave: '10...1....', phase:-0.20, period: 2},
|
||||
{name: 'RRAS', wave: '1...0...1...........', phase:-0.20},
|
||||
{name: '/RAS', wave: '1.......0.......1...0.........x.1......', phase:-0.45, period: 0.5},
|
||||
{name: '/CAS', wave: '1.0.1..0.1', phase: 0.70, period: 2},
|
||||
]}
|
||||
</script><br/><p>
|
||||
This diagram shows the timing of a refresh starting concurrently with the beginning of a RAM access cycle.
|
||||
</p><p>
|
||||
Here we see the timing of refresh being entered concurrently with the start of a RAM access.
|
||||
In this case, there is a little bit of a race condition. <br/>
|
||||
RASEN and /AS both fall following the rising edge of FCLK. /AS causes /RAS activation asynchronously,
|
||||
but RASEN gates this from occurring. <br/>
|
||||
Therefore the internal RASEN feedback in the CPLD must occur sooner than /AS transitions,
|
||||
otherwise an erroneous /RAS pulse will be generated. <br/>
|
||||
Fortunately the CPLDs intended to be used (ispMACH4000, XC9500XL) are some 10 years newer than MC68HC000,
|
||||
so their speed advantage mitigates the problem. <br/>
|
||||
The negation of Ready0 causes /DTACK generation and termination of the bus cycle
|
||||
to be delayed until completion of the refresh. <br/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Before showing the timing for the I/O bus slave port on the FSB,
|
||||
it's instructive to understand the timing of the I/O bus master controller.
|
||||
</p>
|
||||
|
||||
|
||||
<h3 id="t13">13. I/O Bus E State, VMA, "ETACK"</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
@ -420,7 +483,7 @@ terminate the /AS cycle in synchronization with the E clock going low.
|
||||
<h3 id="t14">14. I/O Bus Access (Even Phase)</h3>
|
||||
<script type="WaveDrom">
|
||||
{signal: [
|
||||
{name: 'IOS', wave:'22222222222222222222|222222', period: 1,data:[0,0,0,0,0,0,0,2,3,4,5,6,7,0,1,2,3,4,5,5,5,6,7,0,0,0,0]},
|
||||
{name: 'IOS', wave:'22222222222222222222|222222', period: 1,data:[0,0,0,0,0,0,1,2,3,4,5,6,7,0,1,2,3,4,5,5,5,6,7,0,0,0,0]},
|
||||
{name: 'C16M', wave:'p...................|......', period: 1},
|
||||
{name: 'C8M', wave:'10101010101010101010|101010', phase:-0.25, period: 1},
|
||||
{name: 'C8Mr', wave:'01010101010101010101|010101', phase:-0.10, period: 1},
|
||||
|
||||
432
Power.kicad_sch
432
Power.kicad_sch
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(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid c6d248c1-3a60-47cd-ba0f-1abdfcd1cfdb))
|
||||
(pin "2" (uuid a155eac0-c833-4bed-b97d-1f5e65d354bc))
|
||||
(pin "1" (uuid 07344bba-5ce6-4a5d-8286-68fcbc8a47cd))
|
||||
(pin "2" (uuid bd9f67ae-1e2c-49d6-abcf-99e80b4104ae))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "C9") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "power:+3V3") (at 173.99 53.34 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 5c6352b1-8792-4bf7-b620-189e229be5d1)
|
||||
(property "Reference" "#PWR025" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Value" "+3V3" (at 173.99 49.53 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (at 173.99 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (at 173.99 53.34 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid 470aada9-829c-480d-9232-756b34522830))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "#PWR025") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 107.95 57.15 0) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 9774af56-8e6c-43f2-b1a4-812a34de1810)
|
||||
(property "Reference" "C4" (at 105.41 55.88 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 105.41 58.42 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 107.95 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid af556cd9-cdfa-4414-b548-84662ff8466a))
|
||||
(pin "2" (uuid 542182e8-a04e-4d15-bf62-22259bef9898))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
(reference "C4") (unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
(symbol (lib_id "Device:C_Small") (at 173.99 57.15 0) (mirror y) (unit 1)
|
||||
(in_bom yes) (on_board yes) (dnp no)
|
||||
(uuid 9d3d51a8-d1d0-4ba6-9980-26c7d1d1c409)
|
||||
(property "Reference" "C10" (at 176.53 55.88 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Value" "10u" (at 176.53 58.42 0)
|
||||
(effects (font (size 1.27 1.27)) (justify right))
|
||||
)
|
||||
(property "Footprint" "stdpads:C_0805" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "~" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "LCSC Part" "C15850" (at 173.99 57.15 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(pin "1" (uuid dfcfb5ab-1d5f-432b-b554-6209ece946c2))
|
||||
(pin "2" (uuid 136d4e5d-dbec-47fa-a193-e06c732d1a8b))
|
||||
(instances
|
||||
(project "WarpSE"
|
||||
(path "/a5be2cb8-c68d-4180-8412-69a6b4c5b1d4/00000000-0000-0000-0000-000061b3a5f1"
|
||||
|
||||
965
Prog.kicad_sch
965
Prog.kicad_sch
File diff suppressed because it is too large
Load Diff
138131
WarpSE.kicad_pcb
138131
WarpSE.kicad_pcb
File diff suppressed because it is too large
Load Diff
@ -3,8 +3,8 @@
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"board_outline_line_width": 0.15,
|
||||
"copper_line_width": 0.15239999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
@ -38,7 +38,7 @@
|
||||
"height": 0.4,
|
||||
"width": 0.4
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_line_width": 0.15,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
@ -66,13 +66,13 @@
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"copper_sliver": "error",
|
||||
"courtyards_overlap": "warning",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"duplicate_footprints": "error",
|
||||
"extra_footprint": "error",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
@ -82,13 +82,13 @@
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_issues": "ignore",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"missing_footprint": "error",
|
||||
"net_conflict": "error",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
@ -97,7 +97,7 @@
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"solder_mask_bridge": "warning",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
@ -117,20 +117,20 @@
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.508,
|
||||
"min_clearance": 0.15,
|
||||
"min_connection": 0.12,
|
||||
"min_copper_edge_clearance": 0.4064,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_hole_to_hole": 0.254,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.19999999999999998,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.15,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
@ -186,11 +186,8 @@
|
||||
0.45,
|
||||
0.5,
|
||||
0.6,
|
||||
0.7,
|
||||
0.8,
|
||||
1.0,
|
||||
1.2,
|
||||
1.2,
|
||||
1.27,
|
||||
1.524
|
||||
],
|
||||
@ -201,7 +198,7 @@
|
||||
},
|
||||
{
|
||||
"diameter": 0.5,
|
||||
"drill": 0.2
|
||||
"drill": 0.3
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
@ -215,18 +212,6 @@
|
||||
"diameter": 1.0,
|
||||
"drill": 0.5
|
||||
},
|
||||
{
|
||||
"diameter": 1.2,
|
||||
"drill": 0.6
|
||||
},
|
||||
{
|
||||
"diameter": 1.27,
|
||||
"drill": 0.635
|
||||
},
|
||||
{
|
||||
"diameter": 1.5,
|
||||
"drill": 0.75
|
||||
},
|
||||
{
|
||||
"diameter": 1.524,
|
||||
"drill": 0.762
|
||||
@ -477,7 +462,7 @@
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.15,
|
||||
"via_diameter": 0.5,
|
||||
"via_drill": 0.2,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
(fp_lib_table
|
||||
(lib (name stdpads)(type KiCad)(uri ${KIPRJMOD}/../stdpads.pretty)(options "")(descr ""))
|
||||
(version 7)
|
||||
(lib (name "stdpads")(type "KiCad")(uri "$(KIPRJMOD)/../stdpads.pretty")(options "")(descr ""))
|
||||
)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user