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https://github.com/garrettsworkshop/Warp-SE.git
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Add back settings
This commit is contained in:
Zane Kaminski
parent
29b1436bad
commit
8b54476fc8
56
cpld/CNT.v
56
cpld/CNT.v
@ -22,14 +22,13 @@ module CNT(
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input SCSICS,
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input SndCSWR,
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/* QoS settings inputs */
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/*input SlowIACK,
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input SlowVIA,
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input SlowIWM,
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input SlowSCC,
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input SlowSCSI,
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input SlowSnd,
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input SlowClockGate,
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input [3:0] SlowInterval, */
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input SetSCCFast,
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input SetVIASlow,
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input SetIWMSlow,
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input SetSndSlow,
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input SetClockGate,
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input SetSndClockGate,
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input SetSlow,
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/* QoS outputs */
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output reg QoSEN,
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output reg MCKE);
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@ -75,47 +74,50 @@ module CNT(
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/* QoS select latch */
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reg SndCSWRr; always @(posedge CLK) SndCSWRr <= BACT && SndCSWR;
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/* QoS state */
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reg [3:0] QS;
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always @(posedge CLK) begin
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if (!nRESin) QS <= 3;
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else if (BACT && IACK0CS) QS <= 15;
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else if (BACT && VIACS) QS[1] <= 1;
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else if (BACT && IWMCS) QS[1] <= 1;
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else if (SndCSWRr) QS <= 15;
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else if (BACT && IACK0CS && SetSndSlow) QS <= 15;
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else if (BACT && VIACS && SetVIASlow) QS[1] <= 1;
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else if (BACT && IWMCS && SetIWMSlow) QS[1] <= 1;
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else if (SndCSWRr && SetSndSlow) QS <= 15;
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else if (QS!=0 && TimerTick) QS <= QS-1;
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end
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/* QoS-fast state */
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reg [1:0] QFS;
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always @(posedge CLK) begin
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if (!nRESin) QFS <= 0;
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else if (BACT && IACK1CS) QFS <= 2;
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else if (BACT && IACK0CS) QFS <= 0;
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else if (BACT && VIACS) QFS <= 0;
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else if (BACT && IWMCS) QFS <= 0;
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else if (BACT && SCCCS) QFS <= 2;
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else if (SndCSWRr) QFS <= 0;
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else if (BACT && IACK1CS && SetSCCFast) QFS <= 2;
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else if (BACT && IACK0CS) QFS <= 0;
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else if (BACT && VIACS) QFS <= 0;
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else if (BACT && IWMCS) QFS <= 0;
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else if (BACT && SCCCS && SetSCCFast) QFS <= 2;
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else if (SndCSWRr) QFS <= 0;
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else if (QFS!=0 && TimerTick) QFS <= QFS-1;
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end
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/* Clock gating enable control */
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reg ClockGateEN;
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always @(posedge CLK) begin
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if (!nRESin) ClockGateEN <= 0;
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else if (SndCSWRr) ClockGateEN <= 1;
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else if (BACT && IACK1CS) ClockGateEN <= 0;
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else if (BACT && IACK0CS) ClockGateEN <= 0;
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else if (BACT && VIACS) ClockGateEN <= 0;
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else if (BACT && IWMCS) ClockGateEN <= 0;
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else if (BACT && SCCCS) ClockGateEN <= 0;
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else if (BACT && SCSICS) ClockGateEN <= 0;
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else if (SndCSWRr && SetSndClockGate) ClockGateEN <= 1;
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else if (BACT && IACK1CS) ClockGateEN <= 0;
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else if (BACT && IACK0CS) ClockGateEN <= 0;
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else if (BACT && VIACS) ClockGateEN <= 0;
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else if (BACT && IWMCS) ClockGateEN <= 0;
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else if (BACT && SCCCS) ClockGateEN <= 0;
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else if (BACT && SCSICS) ClockGateEN <= 0;
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end
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/* QoS enable control */
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always @(posedge CLK) if (!BACT) QoSEN <= QS!=0 && QFS==0;
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always @(posedge CLK) if (!BACT) QoSEN <= (QS!=0 && QFS==0) || SetSlow;
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/* MC68k clock gating during QoS */
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always @(negedge CLK, negedge nAS) begin
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if (!nAS) MCKE <= 1;
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else MCKE <= !(QoSEN && !ASrf && !C8MFall && ClockGateEN);
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else MCKE <= !(QoSEN && !ASrf && !C8MFall && (ClockGateEN || SetClockGate));
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end
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/* Long timer counts from 0 to 4095.
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@ -55,7 +55,7 @@ module CS(
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((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign SetCSWR = A[23:20]==4'hF && !A[19] && !nWE;
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assign SetCSWR = A[23:20]==4'hF && A[19:16]==4'h0 && !nWE;
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/* Select signals - IOB domain */
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assign IACS = A[23:20]==4'hF; // IACK
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63
cpld/SET.v
63
cpld/SET.v
@ -2,49 +2,36 @@ module SET(
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input CLK,
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input nPOR,
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input BACT,
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input [11:1] A,
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input [7:1] A,
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input SetCSWR,
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output SlowIACK,
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output SlowVIA,
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output SlowIWM,
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output SlowSCC,
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output SlowSCSI,
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output SlowSnd,
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output SlowClockGate,
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output [3:0] SlowInterval);
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output reg SetSCCFast,
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output reg SetVIASlow,
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output reg SetIWMSlow,
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output reg SetSndSlow,
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output reg SetClockGate,
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output reg SetSndClockGate,
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output reg SetSlow);
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//reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
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assign SlowInterval[3:0] = 4'hF;
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assign SlowIACK = 1;
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assign SlowVIA = 1;
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assign SlowIWM = 1;
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assign SlowSCC = 1;
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assign SlowSCSI = 1;
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assign SlowSnd = 1;
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assign SlowClockGate = 0;
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reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
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/*always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (!nPOR) begin
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SlowInterval[3:0] <= 4'hF;
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SlowIACK <= 1;
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SlowVIA <= 1;
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SlowIWM <= 1;
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SlowSCC <= 1;
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SlowSCSI <= 1;
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SlowSnd <= 1;
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SlowClockGate <= 0;
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SetSCCFast <= 1;
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SetVIASlow <= 1;
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SetIWMSlow <= 1;
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SetSndSlow <= 1;
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SetSndClockGate <= 1;
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SetClockGate <= 0;
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SetSlow <= 0;
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end else if (SetWRr) begin
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SlowInterval[3:0] <= A[11:8];
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SlowIACK <= A[7];
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SlowVIA <= A[6];
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SlowIWM <= A[5];
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SlowSCC <= A[4];
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SlowSCSI <= A[3];
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SlowSnd <= A[2];
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SlowClockGate <= A[1];
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SetSCCFast <= A[7];
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SetVIASlow <= A[6];
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SetIWMSlow <= A[5];
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SetSndSlow <= A[4];
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SetSndClockGate <= A[3];
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SetClockGate <= A[2];
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SetSlow <= A[1];
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end
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end*/
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end
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endmodule
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@ -210,22 +210,26 @@ module WarpSE(
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.IOACT(IOACT),
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.IODONE(IODONE));
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//wire SlowIACK, SlowVIA, SlowIWM, SlowSCC, SlowSCSI, SlowSnd, SlowClockGate;
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//wire [3:0] SlowInterval;
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/*SET set(
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wire SetSCCFast;
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wire SetVIASlow;
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wire SetIWMSlow;
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wire SetSndSlow;
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wire SetClockGate;
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wire SetSndClockGate;
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wire SetSlow;
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SET set(
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.CLK(FCLK),
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.nPOR(nPOR),
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.BACT(BACT),
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.A(A_FSB[11:1]),
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.A(A_FSB[7:1]),
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.SetCSWR(SetCSWR),
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.SlowIACK(SlowIACK),
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.SlowVIA(SlowVIA),
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.SlowIWM(SlowIWM),
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.SlowSCC(SlowSCC),
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.SlowSCSI(SlowSCSI),
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.SlowSnd(SlowSnd),
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.SlowClockGate(SlowClockGate),
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.SlowInterval(SlowInterval));*/
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.SetSCCFast(SetSCCFast),
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.SetVIASlow(SetVIASlow),
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.SetIWMSlow(SetIWMSlow),
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.SetSndSlow(SetSndSlow),
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.SetClockGate(SetClockGate),
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.SetSndClockGate(SetSndClockGate),
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.SetSlow(SetSlow));
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wire nBR_IOBout;
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assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
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@ -259,14 +263,13 @@ module WarpSE(
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.SCSICS(SCSICS),
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.SndCSWR(SndCSWR),
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/* QoS settings inputs */
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/*.SlowIACK(SlowIACK),
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.SlowVIA(SlowVIA),
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.SlowIWM(SlowIWM),
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.SlowSCC(SlowSCC),
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.SlowSCSI(SlowSCSI),
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.SlowSnd(SlowSnd),
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.SlowClockGate(SlowClockGate),
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.SlowInterval(SlowInterval),*/
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.SetSCCFast(SetSCCFast),
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.SetVIASlow(SetVIASlow),
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.SetIWMSlow(SetIWMSlow),
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.SetSndSlow(SetSndSlow),
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.SetClockGate(SetClockGate),
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.SetSndClockGate(SetSndClockGate),
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.SetSlow(SetSlow),
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/* QoS outputs */
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.QoSEN(QoSEN),
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.MCKE(MCKE));
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