mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-22 08:32:09 +00:00
300 lines
6.2 KiB
Verilog
300 lines
6.2 KiB
Verilog
module WarpSE(
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input [23:1] A_FSB,
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output [23:22] GA,
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input nAS_FSB,
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input nLDS_FSB,
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input nUDS_FSB,
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input nWE_FSB,
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output nDTACK_FSB,
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output nVPA_FSB,
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output nBERR_FSB,
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input FCLK,
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input C16M,
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input C8M,
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input E,
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input nDTACK_IOB,
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input nVPA_IOB,
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output nVMA_IOB,
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output nAS_IOB,
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output RnW_IOB,
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output nUDS_IOB,
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output nLDS_IOB,
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output nBR_IOB,
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input nBG_IOB,
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input nBERR_IOB,
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inout nRES,
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input nIPL2,
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output nROMOE,
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output nRAMLWE,
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output nRAMUWE,
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output nROMWE,
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output nRAS,
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output nCAS,
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output [11:0] RA,
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output nOE,
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output nADoutLE0,
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output nADoutLE1,
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output nAoutOE,
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output nDoutOE,
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output nDinOE,
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output nDinLE,
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output MCKE,
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input [5:0] DBG);
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/* GA gated (translated) address output */
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assign GA[23:22] = A_FSB[23:22];
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/*assign GA[23:22] = (
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// $800000-$8FFFFF to $000000-$0FFFFF (1 MB)
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(A_FSB[23:20]==4'h8) ||
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// $700000-$7EFFFF to $300000-$3EFFFF (960 kB)
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(A_FSB[23:20]==4'h7 && A_FSB[19:16]!=4'hF) ||
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// $600000-$6FFFFF to $200000-$2FFFFF (1 MB)
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(A_FSB[23:20]==4'h6)) ? 2'b00 : A_FSB[23:22];*/
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/* Reset input and open-drain output */
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wire nRESin = nRES;
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wire nRESout;
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assign nRES = !nRESout ? 1'b0 : 1'bZ;
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/* Power-on reset */
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wire nPOR;
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/* AS cycle detection */
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wire ASrf, BACT, BACTr;
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/* Refresh request/ack signals */
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wire RefReq, RefUrg;
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/* FSB chip select signals */
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wire IOCS, IORealCS, IOPWCS;
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wire ROMCS, ROMCS4X;
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wire RAMCS, RAMCS0X;
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wire QoSEN;
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wire IACKCS, IACK0CS, IACK1CS;
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wire VIACS, IWMCS, SCCCS, SCSICS, SndCSWR;
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//wire SetCSWR;
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CS cs(
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/* MC68HC000 interface */
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.A(A_FSB[23:1]),
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.CLK(FCLK),
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.nRES(nRESin),
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.nWE(nWE_FSB),
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/* /AS cycle detection */
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.BACT(BACT),
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/* QoS enable input */
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.QoSEN(QoSEN),
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/* Device select outputs */
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.IOCS(IOCS),
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.IORealCS(IORealCS),
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.IOPWCS(IOPWCS),
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.ROMCS(ROMCS),
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.ROMCS4X(ROMCS4X),
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.RAMCS(RAMCS),
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.RAMCS0X(RAMCS0X),
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/* Motherboard I/O device select outputs */
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.IACKCS(IACKCS),
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.IACK0CS(IACK0CS),
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.IACK1CS(IACK1CS),
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.VIACS(VIACS),
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.IWMCS(IWMCS),
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.SCCCS(SCCCS),
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.SCSICS(SCSICS),
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.SndCSWR(SndCSWR)/*,*/
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/* Settings register select output */
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/*.SetCSWR(SetCSWR)*/);
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wire RAMReady;
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RAM ram(
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/* MC68HC000 interface */
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.CLK(FCLK),
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.A(A_FSB[21:1]),
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.nWE(nWE_FSB),
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.nAS(nAS_FSB),
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.nLDS(nLDS_FSB),
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.nUDS(nUDS_FSB),
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.nDTACK(nDTACK_FSB),
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/* AS cycle detection inputs */
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.BACT(BACT),
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.BACTr(BACTr),
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/* RAM and ROM select inputs */
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.RAMCS(RAMCS),
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.RAMCS0X(RAMCS0X),
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.ROMCS(ROMCS),
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.ROMCS4X(ROMCS4X),
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/* RAM ready output */
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.RAMReady(RAMReady),
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/* Refresh Counter Interface */
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.RefReqIn(RefReq),
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.RefUrgIn(RefUrg),
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/* DRAM and NOR flash interface */
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.RA(RA[11:0]),
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.nRAS(nRAS),
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.nCAS(nCAS),
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.nLWE(nRAMLWE),
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.nUWE(nRAMUWE),
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.nOE(nOE),
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.nROMOE(nROMOE),
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.nROMWE(nROMWE));
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wire IONPReady, IOPWReady;
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wire IOREQ, IORW;
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wire IOL0, IOU0;
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wire ALE0S, ALE0M, ALE1;
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assign nADoutLE0 = ~(ALE0S || ALE0M);
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assign nADoutLE1 = ~ALE1;
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wire IOACT, IODONE;
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IOBS iobs(
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/* MC68HC000 interface */
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.CLK(FCLK),
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.nWE(nWE_FSB),
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.nAS(nAS_FSB),
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.nLDS(nLDS_FSB),
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.nUDS(nUDS_FSB),
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/* AS cycle detection */
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.BACT(BACT), .BACTr(BACTr),
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/* Select signals */
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.IOCS(IOCS),
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.IORealCS(IORealCS),
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.IOPWCS(IOPWCS),
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/* FSB cycle termination outputs */
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.IONPReady(IONPReady),
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.IOPWReady(IOPWReady),
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.nBERR_FSB(nBERR_FSB),
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/* Read data OE control */
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.nDinOE(nDinOE),
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/* IOB Master Controller Interface */
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.IOREQ(IOREQ),
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.IORW(IORW),
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.IOACT(IOACT),
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.IODONEin(IODONE),
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.nBERR_IOB(!nBERR_IOB),
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/* FIFO primary level control */
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.ALE0(ALE0S),
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.IOL0(IOL0),
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.IOU0(IOU0),
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/* FIFO secondary level control */
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.ALE1(ALE1));
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wire AoutOE;
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assign nAoutOE = !AoutOE;
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wire nAS_IOBout, RnW_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
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assign RnW_IOB = AoutOE ? RnW_IOBout : 1'bZ;
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assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
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assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
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assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
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IOBM iobm(
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/* PDS interface */
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.C16M(C16M),
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.C8M(C8M),
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.E(E),
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.nAS(nAS_IOBout),
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.RnW(RnW_IOBout),
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.nLDS(nLDS_IOBout),
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.nUDS(nUDS_IOBout),
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.nVMA(nVMA_IOBout),
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.nDTACK(nDTACK_IOB),
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.nVPA(nVPA_IOB),
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.nBERR(nBERR_IOB),
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.nRES(nRESin),
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/* PDS address and data latch control */
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.AoutOE(AoutOE),
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.nDoutOE(nDoutOE),
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.ALE0(ALE0M),
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.nDinLE(nDinLE),
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/* IO bus slave port interface */
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.IOREQ(IOREQ),
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.IORW(IORW),
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.IOLDS(IOL0),
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.IOUDS(IOU0),
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.IOACT(IOACT),
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.IODONE(IODONE));
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wire SetSCCFast;
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wire SetVIASlow;
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wire SetIWMSlow;
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wire SetSndSlow;
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wire SetClockGate;
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wire SetSndClockGate;
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wire SetSlow;
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SET set(
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.CLK(FCLK),
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.nPOR(nPOR),
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.BACT(BACT),
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.A(A_FSB[7:1]),
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.SetCSWR(SetCSWR),
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.SetSCCFast(SetSCCFast),
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.SetVIASlow(SetVIASlow),
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.SetIWMSlow(SetIWMSlow),
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.SetSndSlow(SetSndSlow),
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.SetClockGate(SetClockGate),
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.SetSndClockGate(SetSndClockGate),
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.SetSlow(SetSlow));
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wire nBR_IOBout;
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assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
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CNT cnt(
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/* FSB clock, 7.8336 MHz clock, and E clock inputs */
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.CLK(FCLK),
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.C8M(C8M),
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.E(E),
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/* Power-on reset */
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.nPOR(nPOR),
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/* Refresh request */
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.RefReq(RefReq),
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.RefUrg(RefUrg),
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/* Reset, button */
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.nRESout(nRESout),
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.nRESin(nRESin),
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.nIPL2(nIPL2),
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/* Mac PDS bus master control outputs */
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.AoutOE(AoutOE),
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.nBR_IOB(nBR_IOBout),
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/* QoS select inputs */
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.nAS(nAS_FSB),
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.ASrf(ASrf),
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.BACT(BACT),
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.BACTr(BACTr),
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.IACK0CS(IACK0CS),
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.IACK1CS(IACK1CS),
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.VIACS(VIACS),
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.IWMCS(IWMCS),
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.SCCCS(SCCCS),
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.SCSICS(SCSICS),
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.SndCSWR(SndCSWR),
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/* QoS settings inputs */
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.SetSCCFast(SetSCCFast),
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.SetVIASlow(SetVIASlow),
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.SetIWMSlow(SetIWMSlow),
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.SetSndSlow(SetSndSlow),
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.SetClockGate(SetClockGate),
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.SetSndClockGate(SetSndClockGate),
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.SetSlow(SetSlow),
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/* QoS outputs */
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.QoSEN(QoSEN),
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.MCKE(MCKE));
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FSB fsb(
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/* MC68HC000 interface */
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.FCLK(FCLK),
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.nAS(nAS_FSB),
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.nDTACK(nDTACK_FSB),
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.nVPA(nVPA_FSB),
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/* FSB cycle detection */
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.ASrf(ASrf),
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.BACT(BACT),
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.BACTr(BACTr),
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/* Ready inputs */
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.ROMCS(ROMCS4X),
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.RAMCS(RAMCS0X),
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.RAMReady(RAMReady),
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.IOPWCS(IOPWCS),
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.IOPWReady(IOPWReady),
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.IONPReady(IONPReady),
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.QoSEN(QoSEN),
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/* Interrupt acknowledge select */
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.IACKCS(IACKCS));
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endmodule
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