Macintosh-HW/Warp-SE
1
0
Fork 0
mirror of https://github.com/garrettsworkshop/Warp-SE.git synced 2024-11-21 17:31:47 +00:00
Code Issues Projects Releases Wiki Activity

Add back settings

Browse Source
This commit is contained in:
Zane Kaminski 2024-10-16 23:33:00 -04:00
parent 29b1436bad
commit 8b54476fc8
4 changed files with 78 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
cpld/CNT.v
View File

@ -22,14 +22,13 @@ module CNT(
input SCSICS, input SCSICS,
input SndCSWR, input SndCSWR,
/* QoS settings inputs */ /* QoS settings inputs */
/*input SlowIACK, input SetSCCFast,
input SlowVIA, input SetVIASlow,
input SlowIWM, input SetIWMSlow,
input SlowSCC, input SetSndSlow,
input SlowSCSI, input SetClockGate,
input SlowSnd, input SetSndClockGate,
input SlowClockGate, input SetSlow,
input [3:0] SlowInterval, */
/* QoS outputs */ /* QoS outputs */
output reg QoSEN, output reg QoSEN,
output reg MCKE); output reg MCKE);
@ -75,47 +74,50 @@ module CNT(
/* QoS select latch */ /* QoS select latch */
reg SndCSWRr; always @(posedge CLK) SndCSWRr <= BACT && SndCSWR; reg SndCSWRr; always @(posedge CLK) SndCSWRr <= BACT && SndCSWR;
/* QoS state */
reg [3:0] QS; reg [3:0] QS;
always @(posedge CLK) begin always @(posedge CLK) begin
if (!nRESin) QS <= 3; if (!nRESin) QS <= 3;
else if (BACT && IACK0CS) QS <= 15; else if (BACT && IACK0CS && SetSndSlow) QS <= 15;
else if (BACT && VIACS) QS[1] <= 1; else if (BACT && VIACS && SetVIASlow) QS[1] <= 1;
else if (BACT && IWMCS) QS[1] <= 1; else if (BACT && IWMCS && SetIWMSlow) QS[1] <= 1;
else if (SndCSWRr) QS <= 15; else if (SndCSWRr && SetSndSlow) QS <= 15;
else if (QS!=0 && TimerTick) QS <= QS-1; else if (QS!=0 && TimerTick) QS <= QS-1;
end end
/* QoS-fast state */
reg [1:0] QFS; reg [1:0] QFS;
always @(posedge CLK) begin always @(posedge CLK) begin
if (!nRESin) QFS <= 0; if (!nRESin) QFS <= 0;
else if (BACT && IACK1CS) QFS <= 2; else if (BACT && IACK1CS && SetSCCFast) QFS <= 2;
else if (BACT && IACK0CS) QFS <= 0; else if (BACT && IACK0CS) QFS <= 0;
else if (BACT && VIACS) QFS <= 0; else if (BACT && VIACS) QFS <= 0;
else if (BACT && IWMCS) QFS <= 0; else if (BACT && IWMCS) QFS <= 0;
else if (BACT && SCCCS) QFS <= 2; else if (BACT && SCCCS && SetSCCFast) QFS <= 2;
else if (SndCSWRr) QFS <= 0; else if (SndCSWRr) QFS <= 0;
else if (QFS!=0 && TimerTick) QFS <= QFS-1; else if (QFS!=0 && TimerTick) QFS <= QFS-1;
end end
/* Clock gating enable control */
reg ClockGateEN; reg ClockGateEN;
always @(posedge CLK) begin always @(posedge CLK) begin
if (!nRESin) ClockGateEN <= 0; if (!nRESin) ClockGateEN <= 0;
else if (SndCSWRr) ClockGateEN <= 1; else if (SndCSWRr && SetSndClockGate) ClockGateEN <= 1;
else if (BACT && IACK1CS) ClockGateEN <= 0; else if (BACT && IACK1CS) ClockGateEN <= 0;
else if (BACT && IACK0CS) ClockGateEN <= 0; else if (BACT && IACK0CS) ClockGateEN <= 0;
else if (BACT && VIACS) ClockGateEN <= 0; else if (BACT && VIACS) ClockGateEN <= 0;
else if (BACT && IWMCS) ClockGateEN <= 0; else if (BACT && IWMCS) ClockGateEN <= 0;
else if (BACT && SCCCS) ClockGateEN <= 0; else if (BACT && SCCCS) ClockGateEN <= 0;
else if (BACT && SCSICS) ClockGateEN <= 0; else if (BACT && SCSICS) ClockGateEN <= 0;
end end
/* QoS enable control */ /* QoS enable control */
always @(posedge CLK) if (!BACT) QoSEN <= QS!=0 && QFS==0; always @(posedge CLK) if (!BACT) QoSEN <= (QS!=0 && QFS==0) || SetSlow;
/* MC68k clock gating during QoS */ /* MC68k clock gating during QoS */
always @(negedge CLK, negedge nAS) begin always @(negedge CLK, negedge nAS) begin
if (!nAS) MCKE <= 1; if (!nAS) MCKE <= 1;
else MCKE <= !(QoSEN && !ASrf && !C8MFall && ClockGateEN); else MCKE <= !(QoSEN && !ASrf && !C8MFall && (ClockGateEN || SetClockGate));
end end
/* Long timer counts from 0 to 4095. /* Long timer counts from 0 to 4095.

2
cpld/CS.v
View File

@ -55,7 +55,7 @@ module CS(
((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) || ((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3))); ((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
assign SetCSWR = A[23:20]==4'hF && !A[19] && !nWE; assign SetCSWR = A[23:20]==4'hF && A[19:16]==4'h0 && !nWE;
/* Select signals - IOB domain */ /* Select signals - IOB domain */
assign IACS = A[23:20]==4'hF; // IACK assign IACS = A[23:20]==4'hF; // IACK

63
cpld/SET.v
View File

@ -2,49 +2,36 @@ module SET(
input CLK, input CLK,
input nPOR, input nPOR,
input BACT, input BACT,
input [11:1] A, input [7:1] A,
input SetCSWR, input SetCSWR,
output SlowIACK, output reg SetSCCFast,
output SlowVIA, output reg SetVIASlow,
output SlowIWM, output reg SetIWMSlow,
output SlowSCC, output reg SetSndSlow,
output SlowSCSI, output reg SetClockGate,
output SlowSnd, output reg SetSndClockGate,
output SlowClockGate, output reg SetSlow);
output [3:0] SlowInterval);
//reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR; reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
assign SlowInterval[3:0] = 4'hF;
assign SlowIACK = 1;
assign SlowVIA = 1;
assign SlowIWM = 1;
assign SlowSCC = 1;
assign SlowSCSI = 1;
assign SlowSnd = 1;
assign SlowClockGate = 0;
/*always @(posedge CLK) begin always @(posedge CLK) begin
if (!nPOR) begin if (!nPOR) begin
SlowInterval[3:0] <= 4'hF; SetSCCFast <= 1;
SlowIACK <= 1; SetVIASlow <= 1;
SlowVIA <= 1; SetIWMSlow <= 1;
SlowIWM <= 1; SetSndSlow <= 1;
SlowSCC <= 1; SetSndClockGate <= 1;
SlowSCSI <= 1; SetClockGate <= 0;
SlowSnd <= 1; SetSlow <= 0;
SlowClockGate <= 0;
end else if (SetWRr) begin end else if (SetWRr) begin
SlowInterval[3:0] <= A[11:8]; SetSCCFast <= A[7];
SlowIACK <= A[7]; SetVIASlow <= A[6];
SlowVIA <= A[6]; SetIWMSlow <= A[5];
SlowIWM <= A[5]; SetSndSlow <= A[4];
SlowSCC <= A[4]; SetSndClockGate <= A[3];
SlowSCSI <= A[3]; SetClockGate <= A[2];
SlowSnd <= A[2]; SetSlow <= A[1];
SlowClockGate <= A[1];
end end
end*/ end
endmodule endmodule

43
cpld/WarpSE.v
View File

@ -210,22 +210,26 @@ module WarpSE(
.IOACT(IOACT), .IOACT(IOACT),
.IODONE(IODONE)); .IODONE(IODONE));
//wire SlowIACK, SlowVIA, SlowIWM, SlowSCC, SlowSCSI, SlowSnd, SlowClockGate; wire SetSCCFast;
//wire [3:0] SlowInterval; wire SetVIASlow;
/*SET set( wire SetIWMSlow;
wire SetSndSlow;
wire SetClockGate;
wire SetSndClockGate;
wire SetSlow;
SET set(
.CLK(FCLK), .CLK(FCLK),
.nPOR(nPOR), .nPOR(nPOR),
.BACT(BACT), .BACT(BACT),
.A(A_FSB[11:1]), .A(A_FSB[7:1]),
.SetCSWR(SetCSWR), .SetCSWR(SetCSWR),
.SlowIACK(SlowIACK), .SetSCCFast(SetSCCFast),
.SlowVIA(SlowVIA), .SetVIASlow(SetVIASlow),
.SlowIWM(SlowIWM), .SetIWMSlow(SetIWMSlow),
.SlowSCC(SlowSCC), .SetSndSlow(SetSndSlow),
.SlowSCSI(SlowSCSI), .SetClockGate(SetClockGate),
.SlowSnd(SlowSnd), .SetSndClockGate(SetSndClockGate),
.SlowClockGate(SlowClockGate), .SetSlow(SetSlow));
.SlowInterval(SlowInterval));*/
wire nBR_IOBout; wire nBR_IOBout;
assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0; assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
@ -259,14 +263,13 @@ module WarpSE(
.SCSICS(SCSICS), .SCSICS(SCSICS),
.SndCSWR(SndCSWR), .SndCSWR(SndCSWR),
/* QoS settings inputs */ /* QoS settings inputs */
/*.SlowIACK(SlowIACK), .SetSCCFast(SetSCCFast),
.SlowVIA(SlowVIA), .SetVIASlow(SetVIASlow),
.SlowIWM(SlowIWM), .SetIWMSlow(SetIWMSlow),
.SlowSCC(SlowSCC), .SetSndSlow(SetSndSlow),
.SlowSCSI(SlowSCSI), .SetClockGate(SetClockGate),
.SlowSnd(SlowSnd), .SetSndClockGate(SetSndClockGate),
.SlowClockGate(SlowClockGate), .SetSlow(SetSlow),
.SlowInterval(SlowInterval),*/
/* QoS outputs */ /* QoS outputs */
.QoSEN(QoSEN), .QoSEN(QoSEN),
.MCKE(MCKE)); .MCKE(MCKE));