mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-21 17:31:47 +00:00
Add back settings
This commit is contained in:
Zane Kaminski
parent
29b1436bad
commit
8b54476fc8
56
cpld/CNT.v
56
cpld/CNT.v
@ -22,14 +22,13 @@ module CNT(
|
||||
input SCSICS,
|
||||
input SndCSWR,
|
||||
/* QoS settings inputs */
|
||||
/*input SlowIACK,
|
||||
input SlowVIA,
|
||||
input SlowIWM,
|
||||
input SlowSCC,
|
||||
input SlowSCSI,
|
||||
input SlowSnd,
|
||||
input SlowClockGate,
|
||||
input [3:0] SlowInterval, */
|
||||
input SetSCCFast,
|
||||
input SetVIASlow,
|
||||
input SetIWMSlow,
|
||||
input SetSndSlow,
|
||||
input SetClockGate,
|
||||
input SetSndClockGate,
|
||||
input SetSlow,
|
||||
/* QoS outputs */
|
||||
output reg QoSEN,
|
||||
output reg MCKE);
|
||||
@ -75,47 +74,50 @@ module CNT(
|
||||
/* QoS select latch */
|
||||
reg SndCSWRr; always @(posedge CLK) SndCSWRr <= BACT && SndCSWR;
|
||||
|
||||
/* QoS state */
|
||||
reg [3:0] QS;
|
||||
always @(posedge CLK) begin
|
||||
if (!nRESin) QS <= 3;
|
||||
else if (BACT && IACK0CS) QS <= 15;
|
||||
else if (BACT && VIACS) QS[1] <= 1;
|
||||
else if (BACT && IWMCS) QS[1] <= 1;
|
||||
else if (SndCSWRr) QS <= 15;
|
||||
else if (BACT && IACK0CS && SetSndSlow) QS <= 15;
|
||||
else if (BACT && VIACS && SetVIASlow) QS[1] <= 1;
|
||||
else if (BACT && IWMCS && SetIWMSlow) QS[1] <= 1;
|
||||
else if (SndCSWRr && SetSndSlow) QS <= 15;
|
||||
else if (QS!=0 && TimerTick) QS <= QS-1;
|
||||
end
|
||||
|
||||
/* QoS-fast state */
|
||||
reg [1:0] QFS;
|
||||
always @(posedge CLK) begin
|
||||
if (!nRESin) QFS <= 0;
|
||||
else if (BACT && IACK1CS) QFS <= 2;
|
||||
else if (BACT && IACK0CS) QFS <= 0;
|
||||
else if (BACT && VIACS) QFS <= 0;
|
||||
else if (BACT && IWMCS) QFS <= 0;
|
||||
else if (BACT && SCCCS) QFS <= 2;
|
||||
else if (SndCSWRr) QFS <= 0;
|
||||
else if (BACT && IACK1CS && SetSCCFast) QFS <= 2;
|
||||
else if (BACT && IACK0CS) QFS <= 0;
|
||||
else if (BACT && VIACS) QFS <= 0;
|
||||
else if (BACT && IWMCS) QFS <= 0;
|
||||
else if (BACT && SCCCS && SetSCCFast) QFS <= 2;
|
||||
else if (SndCSWRr) QFS <= 0;
|
||||
else if (QFS!=0 && TimerTick) QFS <= QFS-1;
|
||||
end
|
||||
|
||||
/* Clock gating enable control */
|
||||
reg ClockGateEN;
|
||||
always @(posedge CLK) begin
|
||||
if (!nRESin) ClockGateEN <= 0;
|
||||
else if (SndCSWRr) ClockGateEN <= 1;
|
||||
else if (BACT && IACK1CS) ClockGateEN <= 0;
|
||||
else if (BACT && IACK0CS) ClockGateEN <= 0;
|
||||
else if (BACT && VIACS) ClockGateEN <= 0;
|
||||
else if (BACT && IWMCS) ClockGateEN <= 0;
|
||||
else if (BACT && SCCCS) ClockGateEN <= 0;
|
||||
else if (BACT && SCSICS) ClockGateEN <= 0;
|
||||
else if (SndCSWRr && SetSndClockGate) ClockGateEN <= 1;
|
||||
else if (BACT && IACK1CS) ClockGateEN <= 0;
|
||||
else if (BACT && IACK0CS) ClockGateEN <= 0;
|
||||
else if (BACT && VIACS) ClockGateEN <= 0;
|
||||
else if (BACT && IWMCS) ClockGateEN <= 0;
|
||||
else if (BACT && SCCCS) ClockGateEN <= 0;
|
||||
else if (BACT && SCSICS) ClockGateEN <= 0;
|
||||
end
|
||||
|
||||
/* QoS enable control */
|
||||
always @(posedge CLK) if (!BACT) QoSEN <= QS!=0 && QFS==0;
|
||||
always @(posedge CLK) if (!BACT) QoSEN <= (QS!=0 && QFS==0) || SetSlow;
|
||||
|
||||
/* MC68k clock gating during QoS */
|
||||
always @(negedge CLK, negedge nAS) begin
|
||||
if (!nAS) MCKE <= 1;
|
||||
else MCKE <= !(QoSEN && !ASrf && !C8MFall && ClockGateEN);
|
||||
else MCKE <= !(QoSEN && !ASrf && !C8MFall && (ClockGateEN || SetClockGate));
|
||||
end
|
||||
|
||||
/* Long timer counts from 0 to 4095.
|
||||
|
||||
@ -55,7 +55,7 @@ module CS(
|
||||
((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
|
||||
((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
|
||||
|
||||
assign SetCSWR = A[23:20]==4'hF && !A[19] && !nWE;
|
||||
assign SetCSWR = A[23:20]==4'hF && A[19:16]==4'h0 && !nWE;
|
||||
|
||||
/* Select signals - IOB domain */
|
||||
assign IACS = A[23:20]==4'hF; // IACK
|
||||
|
||||
63
cpld/SET.v
63
cpld/SET.v
@ -2,49 +2,36 @@ module SET(
|
||||
input CLK,
|
||||
input nPOR,
|
||||
input BACT,
|
||||
input [11:1] A,
|
||||
input [7:1] A,
|
||||
input SetCSWR,
|
||||
output SlowIACK,
|
||||
output SlowVIA,
|
||||
output SlowIWM,
|
||||
output SlowSCC,
|
||||
output SlowSCSI,
|
||||
output SlowSnd,
|
||||
output SlowClockGate,
|
||||
output [3:0] SlowInterval);
|
||||
output reg SetSCCFast,
|
||||
output reg SetVIASlow,
|
||||
output reg SetIWMSlow,
|
||||
output reg SetSndSlow,
|
||||
output reg SetClockGate,
|
||||
output reg SetSndClockGate,
|
||||
output reg SetSlow);
|
||||
|
||||
//reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
|
||||
reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
|
||||
|
||||
|
||||
assign SlowInterval[3:0] = 4'hF;
|
||||
assign SlowIACK = 1;
|
||||
assign SlowVIA = 1;
|
||||
assign SlowIWM = 1;
|
||||
assign SlowSCC = 1;
|
||||
assign SlowSCSI = 1;
|
||||
assign SlowSnd = 1;
|
||||
assign SlowClockGate = 0;
|
||||
|
||||
/*always @(posedge CLK) begin
|
||||
always @(posedge CLK) begin
|
||||
if (!nPOR) begin
|
||||
SlowInterval[3:0] <= 4'hF;
|
||||
SlowIACK <= 1;
|
||||
SlowVIA <= 1;
|
||||
SlowIWM <= 1;
|
||||
SlowSCC <= 1;
|
||||
SlowSCSI <= 1;
|
||||
SlowSnd <= 1;
|
||||
SlowClockGate <= 0;
|
||||
SetSCCFast <= 1;
|
||||
SetVIASlow <= 1;
|
||||
SetIWMSlow <= 1;
|
||||
SetSndSlow <= 1;
|
||||
SetSndClockGate <= 1;
|
||||
SetClockGate <= 0;
|
||||
SetSlow <= 0;
|
||||
end else if (SetWRr) begin
|
||||
SlowInterval[3:0] <= A[11:8];
|
||||
SlowIACK <= A[7];
|
||||
SlowVIA <= A[6];
|
||||
SlowIWM <= A[5];
|
||||
SlowSCC <= A[4];
|
||||
SlowSCSI <= A[3];
|
||||
SlowSnd <= A[2];
|
||||
SlowClockGate <= A[1];
|
||||
SetSCCFast <= A[7];
|
||||
SetVIASlow <= A[6];
|
||||
SetIWMSlow <= A[5];
|
||||
SetSndSlow <= A[4];
|
||||
SetSndClockGate <= A[3];
|
||||
SetClockGate <= A[2];
|
||||
SetSlow <= A[1];
|
||||
end
|
||||
end*/
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -210,22 +210,26 @@ module WarpSE(
|
||||
.IOACT(IOACT),
|
||||
.IODONE(IODONE));
|
||||
|
||||
//wire SlowIACK, SlowVIA, SlowIWM, SlowSCC, SlowSCSI, SlowSnd, SlowClockGate;
|
||||
//wire [3:0] SlowInterval;
|
||||
/*SET set(
|
||||
wire SetSCCFast;
|
||||
wire SetVIASlow;
|
||||
wire SetIWMSlow;
|
||||
wire SetSndSlow;
|
||||
wire SetClockGate;
|
||||
wire SetSndClockGate;
|
||||
wire SetSlow;
|
||||
SET set(
|
||||
.CLK(FCLK),
|
||||
.nPOR(nPOR),
|
||||
.BACT(BACT),
|
||||
.A(A_FSB[11:1]),
|
||||
.A(A_FSB[7:1]),
|
||||
.SetCSWR(SetCSWR),
|
||||
.SlowIACK(SlowIACK),
|
||||
.SlowVIA(SlowVIA),
|
||||
.SlowIWM(SlowIWM),
|
||||
.SlowSCC(SlowSCC),
|
||||
.SlowSCSI(SlowSCSI),
|
||||
.SlowSnd(SlowSnd),
|
||||
.SlowClockGate(SlowClockGate),
|
||||
.SlowInterval(SlowInterval));*/
|
||||
.SetSCCFast(SetSCCFast),
|
||||
.SetVIASlow(SetVIASlow),
|
||||
.SetIWMSlow(SetIWMSlow),
|
||||
.SetSndSlow(SetSndSlow),
|
||||
.SetClockGate(SetClockGate),
|
||||
.SetSndClockGate(SetSndClockGate),
|
||||
.SetSlow(SetSlow));
|
||||
|
||||
wire nBR_IOBout;
|
||||
assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
|
||||
@ -259,14 +263,13 @@ module WarpSE(
|
||||
.SCSICS(SCSICS),
|
||||
.SndCSWR(SndCSWR),
|
||||
/* QoS settings inputs */
|
||||
/*.SlowIACK(SlowIACK),
|
||||
.SlowVIA(SlowVIA),
|
||||
.SlowIWM(SlowIWM),
|
||||
.SlowSCC(SlowSCC),
|
||||
.SlowSCSI(SlowSCSI),
|
||||
.SlowSnd(SlowSnd),
|
||||
.SlowClockGate(SlowClockGate),
|
||||
.SlowInterval(SlowInterval),*/
|
||||
.SetSCCFast(SetSCCFast),
|
||||
.SetVIASlow(SetVIASlow),
|
||||
.SetIWMSlow(SetIWMSlow),
|
||||
.SetSndSlow(SetSndSlow),
|
||||
.SetClockGate(SetClockGate),
|
||||
.SetSndClockGate(SetSndClockGate),
|
||||
.SetSlow(SetSlow),
|
||||
/* QoS outputs */
|
||||
.QoSEN(QoSEN),
|
||||
.MCKE(MCKE));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user