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https://github.com/garrettsworkshop/Warp-SE.git
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Revert "Put back full RAM refresh conditions"
This reverts commit adb2578821
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parent
cf1b0ec03b
commit
8e273169a0
10
cpld/RAM.v
10
cpld/RAM.v
@ -4,7 +4,7 @@ module RAM(
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/* AS cycle detection */
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/* AS cycle detection */
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input BACT,
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input BACT,
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/* Select and ready signals */
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/* Select and ready signals */
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input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady,
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input RAMCS, input ROMCS, output reg RAMReady,
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/* Refresh Counter Interface */
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/* Refresh Counter Interface */
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input RefReqIn, input RefUrgIn,
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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@ -16,8 +16,8 @@ module RAM(
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/* RAM control state */
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/* RAM control state */
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reg [2:0] RS = 0;
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reg [2:0] RS = 0;
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reg Once = 0;
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reg RAMEN = 0;
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reg RAMEN = 0;
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reg Once = 0;
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reg RASEL = 0;
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reg RASEL = 0;
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reg CAS = 0;
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reg CAS = 0;
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reg RASrr = 0;
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reg RASrr = 0;
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@ -59,10 +59,8 @@ module RAM(
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[00] = !RASEL ? A[09] : A[01];
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assign RA[00] = !RASEL ? A[09] : A[01];
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wire RefFromRS0 = ((RefReq && BACT && !BACTr && !RAMCS0X) ||
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wire RefFromRS0 = ((RefReq && !BACT) ||
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(RefUrg && !BACT) ||
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(RefUrg && !BACT));
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && BACT && !RAMEN && !nWE));
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wire RefFromRS2 = RefUrg;
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wire RefFromRS2 = RefUrg;
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wire RAMStart = BACT && RAMCS && RAMEN;
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wire RAMStart = BACT && RAMCS && RAMEN;
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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@ -75,7 +75,7 @@ module WarpSE(
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/* AS cycle detection */
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/* AS cycle detection */
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BACT,
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BACT,
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/* Select and ready signals */
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/* Select and ready signals */
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RAMCS, RAMCS0X, ROMCS, RAMReady,
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RAMCS, ROMCS, RAMReady,
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/* Refresh Counter Interface */
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/* Refresh Counter Interface */
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RefReq, RefUrg,
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RefReq, RefUrg,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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