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Fix typos in recent commits

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This commit is contained in:
Zane Kaminski 2023-04-08 05:49:29 -04:00
parent a8e6aa015e
commit a85da985ed
3 changed files with 13 additions and 11 deletions
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20
cpld/CNT.v
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@ -8,7 +8,7 @@ module CNT(
/* Mac PDS bus master control outputs */ /* Mac PDS bus master control outputs */
output reg AoutOE, output reg nBR_IOB, output reg AoutOE, output reg nBR_IOB,
/* Sound QoS */ /* Sound QoS */
input BACT, input SndRAMCSWR, output QoSReady); input BACT, input SndRAMCSWR, output reg QoSReady);
/* E clock synchronization */ /* E clock synchronization */
reg [1:0] Er; reg [1:0] Er;
@ -18,6 +18,9 @@ module CNT(
/* NMI button synchronization */ /* NMI button synchronization */
reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2; reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
/* Startup sequence state */
reg [1:0] IS = 0;
/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us /* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
* Refresh timer sequence * Refresh timer sequence
* | Timer | RefReq | RefUrg | * | Timer | RefReq | RefUrg |
@ -57,7 +60,7 @@ module CNT(
if (EFall && TimerTC) begin if (EFall && TimerTC) begin
if (IS==3) begin if (IS==3) begin
LTimer[12:10] <= 3'b000; LTimer[12:10] <= 3'b000;
if (LTimer==0 && BACT && VidRAMCSWR) LTimer <= 1; if (LTimer==0 && BACT && SndRAMCSWR) LTimer <= 1;
else if (LTimer==0) LTimer <= 0; else if (LTimer==0) LTimer <= 0;
else LTimer[9:0] <= LTimer+1; else LTimer[9:0] <= LTimer+1;
end else LTimer <= LTimer+1; end else LTimer <= LTimer+1;
@ -68,19 +71,18 @@ module CNT(
/* Sound QoS */ /* Sound QoS */
reg [3:0] WS = 0; reg [3:0] WS = 0;
always @(posedge CLK) begin always @(posedge CLK) begin
if (BACT) begin if (!BACT) begin
if (QoSReady) QoSReady <= 1;
else if (WS==12) QoSReady <= 1;
WS <= WS+1;
end else begin
if (LTimer!=0) QoSReady <= 0; if (LTimer!=0) QoSReady <= 0;
else QoSReady <= 1; else QoSReady <= 1;
WS <= 0; WS <= 0;
end else begin
if (QoSReady) QoSReady <= 1;
else if (WS==12) QoSReady <= 1;
WS <= WS+1;
end end
end end
/* Startup sequence control */ /* Startup sequence state control */
reg [1:0] IS = 0;
wire ISTC = EFall && TimerTC && LTimerTC; wire ISTC = EFall && TimerTC && LTimerTC;
always @(posedge CLK) begin always @(posedge CLK) begin
case (IS[1:0]) case (IS[1:0])

2
cpld/CS.v
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@ -95,7 +95,7 @@ module CS(
((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3)))); ((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
/* Select signals - IOB domain */ /* Select signals - IOB domain */
assign IACS = A[23:16]==4'hFF; // IACK assign IACS = A[23:16]==8'hFF; // IACK
assign IOCS = A[23:20]==4'hF || // IACK assign IOCS = A[23:20]==4'hF || // IACK
A[23:20]==4'hE || // VIA A[23:20]==4'hE || // VIA
A[23:20]==4'hD || // IWM A[23:20]==4'hD || // IWM

2
cpld/FSB.v
View File

@ -8,7 +8,7 @@ module FSB(
input RAMCS, input RAMReady, input RAMCS, input RAMReady,
input IOPWCS, input IOPWReady, input IONPReady, input IOPWCS, input IOPWReady, input IONPReady,
input QoSReady, input QoSReady,
/* Interrupt acknowledge select */z /* Interrupt acknowledge select */
input IACS); input IACS);
/* AS cycle detection */ /* AS cycle detection */