Merge branch 'dev' of https://github.com/garrettsworkshop/Warp-SE into dev
This commit is contained in:
commit
a8e6aa015e
54
cpld/CNT.v
54
cpld/CNT.v
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@ -6,12 +6,17 @@ module CNT(
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/* Reset, button */
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/* Reset, button */
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output reg nRESout, input nIPL2,
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output reg nRESout, input nIPL2,
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/* Mac PDS bus master control outputs */
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output reg nBR_IOB);
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output reg AoutOE, output reg nBR_IOB,
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/* Sound QoS */
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input BACT, input SndRAMCSWR, output QoSReady);
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/* E clock synchronization */
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/* E clock synchronization */
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reg [1:0] Er;
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reg [1:0] Er;
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wire EFall = Er[1] && !Er[0];
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wire EFall = Er[1] && !Er[0];
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always @(posedge CLK) Er[1:0] <= { Er[0], E };
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always @(posedge CLK) Er[1:0] <= { Er[0], E };
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/* NMI button synchronization */
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reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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* Refresh timer sequence
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* Refresh timer sequence
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@ -41,40 +46,61 @@ module CNT(
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end
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end
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end
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end
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/* Long timer counts from 0 to 8191 -- 8192 states == 115.033 ms */
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/* During init (IS!=3) long timer counts from 0 to 8191.
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* 8192 states == 115.033 ms
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* During operation (IS==3) long timer counts from 0 to 1023
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* starting at first sound RAM access.
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* 8192 states == 14.379 ms */
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reg [12:0] LTimer;
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reg [12:0] LTimer;
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reg LTimerTC;
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reg LTimerTC;
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (EFall && TimerTC) begin
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if (EFall && TimerTC) begin
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LTimer <= LTimer+1;
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if (IS==3) begin
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LTimer[12:10] <= 3'b000;
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if (LTimer==0 && BACT && VidRAMCSWR) LTimer <= 1;
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else if (LTimer==0) LTimer <= 0;
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else LTimer[9:0] <= LTimer+1;
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end else LTimer <= LTimer+1;
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LTimerTC <= LTimer[12:0]==13'h1FFE;
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LTimerTC <= LTimer[12:0]==13'h1FFE;
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end
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end
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end
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end
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reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
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/* Sound QoS */
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reg [3:0] WS = 0;
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/* Startup sequence control */
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reg [1:0] INITS = 0;
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wire INITSTC = EFall && TimerTC && LTimerTC;
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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case (INITS[1:0])
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if (BACT) begin
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if (QoSReady) QoSReady <= 1;
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else if (WS==12) QoSReady <= 1;
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WS <= WS+1;
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end else begin
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if (LTimer!=0) QoSReady <= 0;
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else QoSReady <= 1;
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WS <= 0;
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end
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end
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/* Startup sequence control */
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reg [1:0] IS = 0;
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wire ISTC = EFall && TimerTC && LTimerTC;
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always @(posedge CLK) begin
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case (IS[1:0])
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2'h0: begin
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2'h0: begin
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AoutOE <= 0; // Tristate PDS address and control
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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nBR_IOB <= 0; // Default to request bus
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if (INITSTC) INITS <= 1;
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if (ISTC) IS <= 1;
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end 2'h1: begin
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end 2'h1: begin
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AoutOE <= 0;
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AoutOE <= 0;
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nRESout <= 0;
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nRESout <= 0;
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nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
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nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
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if (INITSTC && nIPL2r) INITS <= 2;
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if (ISTC && nIPL2r) IS <= 2;
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end 2'h2: begin
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end 2'h2: begin
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AoutOE <= !nBR_IOB;
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AoutOE <= !nBR_IOB;
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nRESout <= 0;
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nRESout <= 0;
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if (INITSTC) INITS <= 3;
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if (ISTC) IS <= 3;
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end 2'h3: begin
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end 2'h3: begin
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nRESout <= 1; // Release reset
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nRESout <= 1; // Release reset
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INITS <= 3;
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IS <= 3;
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end
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end
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endcase
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endcase
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end
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end
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26
cpld/CS.v
26
cpld/CS.v
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@ -95,19 +95,19 @@ module CS(
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((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
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((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
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/* Select signals - IOB domain */
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/* Select signals - IOB domain */
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assign IACS = (A[23:20]==4'hF) && (A[19:18]==2'b11); // IACK
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assign IACS = A[23:16]==4'hFF; // IACK
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assign IOCS = (A[23:20]==4'hF) || // IACK
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assign IOCS = A[23:20]==4'hF || // IACK
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(A[23:20]==4'hE) || // VIA
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A[23:20]==4'hE || // VIA
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(A[23:20]==4'hD) || // IWM
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A[23:20]==4'hD || // IWM
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(A[23:20]==4'hC) || // empty / fast ROM
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A[23:20]==4'hC || // empty / fast ROM
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(A[23:20]==4'hB) || // SCC write
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A[23:20]==4'hB || // SCC write
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(A[23:20]==4'hA) || // empty
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A[23:20]==4'hA || // empty
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(A[23:20]==4'h9) || // SCC read/reset
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A[23:20]==4'h9 || // SCC read/reset
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(A[23:20]==4'h8) || // empty
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A[23:20]==4'h8 || // empty
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(A[23:20]==4'h7) || // empty
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A[23:20]==4'h7 || // empty
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(A[23:20]==4'h6) || // empty
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A[23:20]==4'h6 || // empty
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(A[23:20]==4'h5) || // SCSI
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A[23:20]==4'h5 || // SCSI
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((A[23:20]==4'h4) && Overlay) || // ROM once
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(A[23:20]==4'h4 && Overlay) || // ROM once
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VidRAMCSWR; // Write to video RAM
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VidRAMCSWR; // Write to video RAM
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assign IOPWCS = VidRAMCSWR;
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assign IOPWCS = VidRAMCSWR;
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endmodule
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endmodule
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@ -7,7 +7,8 @@ module FSB(
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input ROMCS,
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input ROMCS,
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input RAMCS, input RAMReady,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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/* Interrupt acknowledge select */
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input QoSReady,
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/* Interrupt acknowledge select */z
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input IACS);
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input IACS);
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/* AS cycle detection */
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/* AS cycle detection */
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@ -17,9 +18,10 @@ module FSB(
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/* DTACK/VPA control */
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/* DTACK/VPA control */
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wire Ready = (RAMCS && RAMReady && !IOPWCS) ||
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wire Ready = QoSReady &&
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((RAMCS && RAMReady && !IOPWCS) ||
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(RAMCS && RAMReady && IOPWCS && IOPWReady) ||
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(RAMCS && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS) || (IONPReady);
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(ROMCS) || (IONPReady));
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
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always @(posedge FCLK, posedge nAS) begin
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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if (nAS) nVPA <= 1;
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@ -57,7 +57,7 @@ module WarpSE(
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/* FSB chip select signals */
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/* FSB chip select signals */
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wire IOCS, IOPWCS, IACS;
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wire IOCS, IOPWCS, IACS;
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wire ROMCS, ROMCS4X;
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wire ROMCS, ROMCS4X;
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wire RAMCS, RAMCS0X;
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wire RAMCS, RAMCS0X, SndRAMCSWR;
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CS cs(
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CS cs(
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/* MC68HC000 interface */
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/* MC68HC000 interface */
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A_FSB[23:08], FCLK, nRESin, nWE_FSB,
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A_FSB[23:08], FCLK, nRESin, nWE_FSB,
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@ -66,7 +66,7 @@ module WarpSE(
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/* Device select outputs */
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/* Device select outputs */
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IOCS, IOPWCS, IACS,
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IOCS, IOPWCS, IACS,
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ROMCS, ROMCS4X,
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ROMCS, ROMCS4X,
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RAMCS, RAMCS0X);
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RAMCS, RAMCS0X, SndRAMCSWR);
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wire RAMReady;
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wire RAMReady;
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RAM ram(
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RAM ram(
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@ -126,6 +126,7 @@ module WarpSE(
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IORDREQ, IOWRREQ, IOL0, IOU0,
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IORDREQ, IOWRREQ, IOL0, IOU0,
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IOACT, IODONE, IOBERR);
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IOACT, IODONE, IOBERR);
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wire QoSReady;
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CNT cnt(
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CNT cnt(
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/* FSB clock and E clock inputs */
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/* FSB clock and E clock inputs */
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FCLK, E,
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FCLK, E,
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@ -134,7 +135,9 @@ module WarpSE(
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/* Reset, button */
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/* Reset, button */
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nRESout, nIPL2,
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nRESout, nIPL2,
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/* Mac PDS bus master control outputs */
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/* Mac PDS bus master control outputs */
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AoutOE, nBR_IOB);
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AoutOE, nBR_IOB,
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/* Sound QoS */
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BACT, SndRAMCSWR, QoSReady);
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FSB fsb(
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FSB fsb(
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/* MC68HC000 interface */
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/* MC68HC000 interface */
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@ -146,6 +149,8 @@ module WarpSE(
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RAMCS0X, RAMReady,
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RAMCS0X, RAMReady,
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IOPWCS, IOPWReady, IONPReady,
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IOPWCS, IOPWReady, IONPReady,
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/* Interrupt acknowledge select */
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/* Interrupt acknowledge select */
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IACS);
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IACS,
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/* Sound QoS */
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QoSReady);
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endmodule
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endmodule
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