New stuff
This commit is contained in:
Zane Kaminski
parent
ee3a28dd04
commit
a91c6c4ffb
118
cpld/CNT.v
118
cpld/CNT.v
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@ -1,34 +1,104 @@
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module CNT(
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/* FSB clock and AS detection */
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input FCLK, input CACT,
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/* C16M clock */
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input C16M,
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/* FSB clock and bus active signal */
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input FCLK, input BACT,
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/* Refresh request */
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output RefReq, output RefUrgent, input RefAck,
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/* Timeout signals */
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output reg TimeoutA, output reg TimeoutB);
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/* Refresh counter */
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reg [7:0] RefCnt = 0;
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reg RefDone = 0;
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assign RefReq = ~RefDone;
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assign RefUrgent = RefCnt[7] && RefCnt[6] && RefCnt[5] && ~RefDone;
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always @(posedge FCLK) begin
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RefCnt <= RefCnt+1;
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if (RefCnt==0) RefDone <= 0;
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else if (RefAck) RefDone <= 1;
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output reg RefReq, output RefUrgent,
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/* BERR and QoS speed limit output */
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output reg BERRTimeout, output reg QoSReady,
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/* Reset, switch, button */
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input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
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/* Configuration outputs */
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output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN);
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/* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */
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reg [7:0] Timer = 0;
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wire TimerTC = Timer[7:5]==3'b111;
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always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1;
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/* Refresh timer outputs
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* ___ _______________________________________
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* RefReq |___________| |_________
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* ___^ Timer==0 ^ Timer==17 _____________^ Timer==0
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* RefUrg |_____________________________________| |_________
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* ^ Timer==0 ^ Timer==128 ^ Timer==0
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*/
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assign RefUrgent = Timer[7];
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always @(posedge C16M) begin
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if (Timer[4]) RefREQ <= 1;
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else if (TimerTC) RefREQ <= 0;
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end
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/* Timeout signals */
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reg TimeoutBPre;
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/* NBACT - "Narrow BACT" in FCLK clock domain */
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reg [1:0] BACTCnt = 0;
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reg NBACT;
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always @(posedge FCLK) begin
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if (~CACT) begin
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TimeoutA <= 0;
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TimeoutBPre <= 0;
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TimeoutB <= 0;
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if (!BACT) begin
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BACTCnt <= 0;
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NBACT <= 0;
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end else begin
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if (RefCnt[6:0]==0) TimeoutA <= 1;
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if (RefCnt==0) TimeoutBPre <= 1;
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if (RefCnt==0 && TimeoutBPre) TimeoutB <= 1;
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BACTCnt <= BACTCnt+1;
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if (BACTCnt==2'b11 && BACT) NBACT <= 1;
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end
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end
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/* NBACTr - NBACT synchronized to C16M clock domain */
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reg NBACTr;
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always @(posedge C16M) NBACTr <= NBACT;
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/* BERR generation in C16M clock domain */
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reg BERRArm = 0;
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reg BERRTimeout = 0;
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always @(posedge C16M) begin
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if (NBACTr && TimerTC) begin
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if (BERRArm) BERRTimeout <= 1;
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end else if (!NBACTr) begin
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BERRArm <= 0;
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BERRTimeout <= 0;
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end
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end
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/* Sound QoS */
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reg [3:0] SC; // Sound counter
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always @(posedge C16M) begin
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if (PORDone && TimerTC) SC <= SC+1; // SC increment
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if SC[]
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end
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/* IPL2 and /RESET registration */
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reg nIPL2r, nRESr;
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always @(posedge C16M) begin
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nIPL2r <= nIPL2;
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nRESr <= nRES;
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end
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/* Startup sequence control */
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reg PORDone = 0;
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always @(posedge C16M) begin
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if (!PORDone) begin
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if (!nRESr) nRESout <= 1;
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else begin
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nRESout <= 0; // Re-enable reset
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PORDone <= 1; // Mark POR done
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// Decode buttons
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if (nRESr) begin // Reset not pressed: enable WarpSE
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nBR_IOB <= 0; // Request Mac bus
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FastROMEN <= 1; // Fast ROM enabled
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end else if (!nRES && nIPL2r) begin // Reset only: disable card
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nBR_IOB <= 1; // Don't request Mac bus
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FastROMEN <= 0; // Fast ROM enable is don't care
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end else if (!nRES && !nIPL2r) begin // Reset+IPL2: MB ROM
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nBR_IOB <= 0; // Request Mac bus
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FastROMEN <= 1; // Fast ROM disabled so as to use motherboard ROM
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end
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end
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end else if (SC[4]) nRESout <= 1; // Release reset to run
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1; // SW[0];
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assign C25MEN = 1; //!SW[0];
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endmodule
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@ -1,6 +1,6 @@
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module CS(
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/* Setting input */
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input MotherboardROMEN,
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input FastROMEN,
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/* MC68HC000 interface */
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input [23:08] A, input CLK, input nRES, input nWE,
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/* AS cycle detection */
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@ -44,13 +44,13 @@ module CS(
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(A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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(A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign ROMCS = (A[23:20]==4'h4 && !MotherboardROMEN) ||
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(A[23:20]==4'h8 && MotherboardROMEN) ||
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assign ROMCS = (A[23:20]==4'h4 && FastROMEN) ||
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(A[23:20]==4'h8 && !FastROMEN) ||
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(A[23:20]==4'h0 && Overlay);
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/* Select signals - IOB domain */
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assign IACS = A[23:08]==16'hFFFF; // IACK
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assign IOCS = (A[23:20]==4'h4 && MotherboardROMEN) || // Motherboard ROM
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assign IOCS = (A[23:20]==4'h4 && !FastROMEN) || // Motherboard ROM
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A[23:20]==4'h5 || // SCSI
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A[23:20]==4'h8 || // empty
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A[23:20]==4'h9 || // SCC read/reset
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34
cpld/FSB.v
34
cpld/FSB.v
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@ -4,7 +4,7 @@ module FSB(
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/* AS cycle detection */
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output BACT,
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/* Ready inputs */
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input Ready0, input Ready1, input Ready2, input Disable,
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input Ready0, input Ready1, input Ready2,
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/* BERR inputs */
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input BERR0, input BERR1,
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/* Interrupt acknowledge select */
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@ -15,29 +15,39 @@ module FSB(
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always @(negedge FCLK) begin ASrf <= ~nAS; end
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assign BACT = ~nAS || ASrf;
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/* Ready and BERR bypass */
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/* Ready generation and bypass */
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reg Ready0r, Ready1r, Ready2r;
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reg BERR0r, BERR1r;
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wire Ready = ~Disable && (Ready0 || Ready0r) &&
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(Ready1 || Ready1r) &&
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(Ready2 || Ready2r);
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wire BERR = (BERR0 || BERR0r || BERR1 || BERR1r);
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assign nBERR = ~(~nAS && BERR);
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wire Ready = (Ready0 || Ready0r) &&
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(Ready1 || Ready1r) &&
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(Ready2 || Ready2r);
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always @(posedge FCLK) begin
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if (~BACT) begin
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Ready0r <= 0;
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Ready1r <= 0;
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Ready2r <= 0;
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BERR0r <= 0;
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BERR1r <= 0;
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end else begin
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if (Ready0) Ready0r <= 1;
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if (Ready1) Ready1r <= 1;
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if (Ready2) Ready2r <= 1;
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if (BERR0) BERR0r <= 1;
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if (BERR1) BERR1r <= 1;
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end
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end
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/* BERR generation */
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reg BERR0r, BERR1r;
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always @(posedge FCLK) BERR0r <= BERR0;
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always @(posedge FCLK) BERR1r <= BERR1;
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reg BERREN = 0;
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reg BERRCNT = 0;
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always @(posedge FCLK) begin
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if (~BACT) begin
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BERREN <= 0;
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BERRCNT <= 0;
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end else begin
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BERRCNT <= BERRCNT+1;
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BERREN <= BERRCNT==3'b111;
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end
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end
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assign nBERR = ~(~nAS && BERREN && (BERR0r || BERR1r));
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/* DTACK/VPA control */
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reg VPA;
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39
cpld/IOBM.v
39
cpld/IOBM.v
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@ -1,7 +1,7 @@
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module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output nBR, output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
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output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
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input nASin, input nBG, input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE,
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@ -9,6 +9,14 @@ module IOBM(
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output reg IOACT, output reg IOBERR,
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input Park, input IOREQ, input IOLDS, input IOUDS, input IOWE);
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/* Bus grant recognition */
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reg nASr;
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reg BG = 0;
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always @(posedge C16M) begin
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nASr <= nASin;
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if (nASr) BG <= nBG;
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end
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/* I/O bus slave port input synchronization */
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reg IOREQr = 0;
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always @(negedge C16M) begin IOREQr <= IOREQ; end
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@ -52,35 +60,14 @@ module IOBM(
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else if (ES==0) nVMA <= 1;
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end
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/* Bus Request/Grant control */
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assign nBR = Park;
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reg BGr0 = 0;
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reg BGr1 = 0;
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reg BG = 0;
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always @(posedge C16M) begin
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BGr0 <= ~nBG;
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BGr1 <= BGr0;
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if (BGr1 && nASin) BG <= 1;
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else if (~BGr0) BG <= 0;
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end
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/* I/O bus state */
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reg [2:0] IOS = 0;
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always @(posedge C16M) begin
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if (IOS==0) begin
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if (IOREQr && BG) begin
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if (~C8M) begin
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IOS <= 1;
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end else begin
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IOS <= 0;
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end
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IOACT <= 1;
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ALE0 <= 1;
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end else begin
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IOS <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end
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if (~C8M && IOREQr && BG) IOS <= 1;
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else IOS <= 0;
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IOACT <= IOREQr;
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ALE0 <= IOREQr;
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end else if (IOS==1) begin
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IOS <= 2;
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IOACT <= 1;
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101
cpld/RAM.v
101
cpld/RAM.v
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@ -6,31 +6,74 @@ module RAM(
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/* Select and ready signals */
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input RAMCS, input ROMCS, output Ready,
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/* Refresh Counter Interface */
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input RefReq, input RefUrgent, output RefAck,
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input RefReqIn, input RefUrgentIn,
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
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/* RAM control state */
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reg [2:0] RS = 0;
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reg Once = 0;
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reg RAMEN = 0;
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reg RAMReady = 0;
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reg RASEL = 0; // RASEL controls /CAS signal
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/* Refresh request synchronization */
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reg RefReqR; // Refresh synchronization
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always @(posedge CLK) RefReqR <= RefReqIn;
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reg RefReq, RefUrgent; // Refresh commands
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reg RefDone; // Refresh done "remember"
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always @(posedge CLK) begin
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RefReq <= RefReqR && !RefDone;
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RefUrgent <= RefReqR && RefUrgentIn && !RefDone;
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if (!RefReqR) RefDone <= 0;
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else if (RS==2 || RS==3) RefDone <= 1; // RS2 || RS3 to save 1 input
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end
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/* RAM enable
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*/
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/* Refresh init conditions */
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wire RAMRefFromRS0Next = RS==0 && (
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// Non-urgent refresh can start during first clock of non-RAM cycle
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( BACT && ~BACTr && ~RAMCS && RefReq) ||
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// Urgent refresh can start during bus idle
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(~BACT && RefUrgent) ||
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// Urgent refresh can start during non-ram cycle
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( BACT && ~RAMCS && RefUrgent));
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wire RAMRefFromRS0Pre = RS==0 &&
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// Urgent refresh can start during long RAM cycle after RAM access done.
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BACT && RAMCS && !RAMEN && RefUrgent;
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wire RAMRefFromRS0 = RAMRefFromRS0Next || RAMRefFromRS0Pre;
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// Urgent refresh cannot start when BACT and RAMCS and RAMEN,
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// since /RAS has already been asserted. For this we wait for RS7.
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wire RAMRefFromRS7 = RS==7 && RefUrgent;
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/* RAM access start condition */
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wire RAMStart = RS==0 && BACT && RAMCS && RAMEN;
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/* RAM enable (/AS -> /RAS) */
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always @(posedge CLK) begin
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if (RS==0) begin
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if (RAMRefFromRS0) RAMEN <= 0;
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else if (!BACT) RAMEN <= 1;
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end else if (RS==7) begin
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if (RAMRefFromRS7) RAMEN <= 0;
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else if (BACT) RAMEN <= 0;
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else if (!BACT) RAMEN <= 1;
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end
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end
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/* Refresh state */
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reg RAMDIS1 = 0;
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reg RAMDIS2 = 0;
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wire RAMDIS = RAMDIS1 || RAMDIS2;
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wire RAMEN = ~RAMDIS;
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reg RefRAS = 0;
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assign nROMCS = ~ROMCS;
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assign nRAS = ~((~nAS && RAMCS && RAMEN && ~RefRAS /* does this add loading to these P-terms? */) || RefRAS);
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assign nRAS = ~((~nAS && RAMCS && RAMEN) || RefRAS);
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assign nOE = ~(~nAS && nWE);
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assign nLWE = ~(~nAS && ~nWE && ~nLDS && RAMEN);
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assign nUWE = ~(~nAS && ~nWE && ~nUDS && RAMEN);
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assign nROMWE = ~(~nAS && ~nWE);
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/* RAM address mux (and ROM address on RA8) */
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assign RA[11] = A[19];
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assign RA[10] = A[21];
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assign RA[09] = RASEL ? A[20] : A[19];
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@ -44,35 +87,31 @@ module RAM(
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assign RA[01] = RASEL ? A[02] : A[11];
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assign RA[00] = RASEL ? A[01] : A[10];
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always @(posedge CLK) begin
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if (~BACT) Once <= 0;
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else if (RS==0 && BACT && RAMCS) Once <= 1;
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end
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always @(posedge CLK) begin
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if (~BACT) RAMDIS2 <= 0;
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else if ((RS==0 && BACT && RefUrgent && Once && RAMCS) ||
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(RS==7 && BACT && RefUrgent && Once)) RAMDIS2 <= 1;
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end
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// Save BACT from last clock
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reg BACTr;
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always @(posedge CLK) begin BACTr <= BACT; end
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always @(posedge CLK) BACTr <= BACT;
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always @(posedge CLK) begin
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if (RS==0) begin
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if (( BACT && RefReq && ~RAMCS && ~BACTr) || // Non-urgent refresh can start during first clock of non-RAM cycle
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(~BACT && RefUrgent) || // Urgent refresh can start during bus idle
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( BACT && RefUrgent && ~RAMCS)) begin // Urgent refresh can start during non-ram cycle
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// In RS0, RAM is idle and ready for new command.
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if (RefFromRS0Next) begin
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RS <= 2;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 1;
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end else if (BACT && RAMCS && ~Once) begin
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end else if (RefFromRS0Pre) begin
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// Urgent ref can start during long RAM cycle after access.
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// Must insert one extra precharge state first by going to RS1.
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RS <= 1;
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RAMReady <= 0;
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RASEL <= 0;
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RAMDIS1 <= 1;
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end else if (BACT && RAMCS && RAMEN) begin
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// RAM access cycle has priority over urgent refresh if RAM access already begun
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RS <= 5;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 0;
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end else if (BACT && RAMCS && RefUrgent) begin
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// Urgent refresh can start during prolonged RAM access cycle
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// But we must insert one extra precharge state first.
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end else if (RAMRefFromRS0Pre) begin
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RS <= 1;
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RAMReady <= 0;
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RASEL <= 0;
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@ -86,53 +125,65 @@ module RAM(
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end
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RefRAS <= 0;
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end else if (RS==1) begin
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// RS1 implements extra precharge time before refresh.
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RS <= 2;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 1;
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RefRAS <= 0;
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end else if (RS==2) begin
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// Refresh RAS pulse asserted ater RS2.
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RS <= 3;
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RAMReady <= 0;
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RASEL <= 1;
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RAMDIS1 <= 1;
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RefRAS <= 1;
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end else if (RS==3) begin
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// RS3 implements requisite RAS pulse width.
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RS <= 4;
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RAMReady <= 0;
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RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
RefRAS <= 1;
|
||||
end else if (RS==4) begin
|
||||
// RS4 implements precharge after RAM refresh.
|
||||
RS <= 7;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==5) begin
|
||||
// RS5 is first state of R/W operation
|
||||
RS <= 6;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 1;
|
||||
RAMDIS1 <= 0;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==6) begin
|
||||
// RS6 is second state of R/W operation
|
||||
RS <= 7;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 0;
|
||||
RefRAS <= 0;
|
||||
end else if (RS==7) begin
|
||||
// RS7 is final state of R/W or refresh operation.
|
||||
if (~BACT && RefUrgent) begin
|
||||
// If /AS cycle terminated and urgent refresh request,
|
||||
// we know /RAS has been in precharge so we can go to RS2.
|
||||
RS <= 2;
|
||||
RAMReady <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
RASEL <= 1;
|
||||
end else if (BACT && RefUrgent) begin
|
||||
// But if /AS cycle hasn't terminated and we need to refresh,
|
||||
// we need to go to RS1 to add additional precharge time.
|
||||
RS <= 1;
|
||||
RAMReady <= 0;
|
||||
RASEL <= 0;
|
||||
RAMDIS1 <= 1;
|
||||
end else begin
|
||||
// Otherwise if no urgent refresh request, go to RS0.
|
||||
RS <= 0;
|
||||
RAMReady <= 1;
|
||||
RASEL <= 0;
|
||||
|
|
@ -143,8 +194,6 @@ module RAM(
|
|||
end
|
||||
always @(negedge CLK) begin nCAS <= ~RASEL; end
|
||||
|
||||
assign RefAck = RefRAS;
|
||||
|
||||
assign Ready = ~RAMCS || RAMReady;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ module WarpSE(
|
|||
output nBR_IOB,
|
||||
input nBG_IOB,
|
||||
input nBERR_IOB,
|
||||
input nRES,
|
||||
inout nRES,
|
||||
input nIPL2,
|
||||
output nROMCS,
|
||||
output nRAMLWE,
|
||||
|
|
@ -36,27 +36,30 @@ module WarpSE(
|
|||
output nDoutOE,
|
||||
output nDinOE,
|
||||
output nDinLE,
|
||||
input [2:0] SW,
|
||||
output CLK20EN,
|
||||
output CLK25EN);
|
||||
input [3:1] SW,
|
||||
output C20MEN,
|
||||
output C25MEN);
|
||||
|
||||
/* DIP switches */
|
||||
assign CLK20EN = SW[0];
|
||||
assign CLK25EN = !SW[0];
|
||||
wire MotherboardROMEN = !SW[1];
|
||||
/* Reset input and open-drain output */
|
||||
wire nRESin = nRES;
|
||||
wire nRESout;
|
||||
assign nRES = !nRESout ? 1'b0 : 1'bZ;
|
||||
|
||||
/* AS cycle detection */
|
||||
wire BACT;
|
||||
|
||||
/* Refresh request/ack signals */
|
||||
wire RefReq, RefUrgent, RefAck;
|
||||
wire RefReq, RefUrgent;
|
||||
|
||||
/* Fast ROM enable setting */
|
||||
wire FastROMEN;
|
||||
|
||||
wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR;
|
||||
CS cs(
|
||||
/* Setting input */
|
||||
MotherboardROMEN,
|
||||
FastROMEN,
|
||||
/* MC68HC000 interface */
|
||||
A_FSB[23:08], CLK_FSB, nRES, nWE_FSB,
|
||||
A_FSB[23:08], CLK_FSB, nRESin, nWE_FSB,
|
||||
/* AS cycle detection */
|
||||
BACT,
|
||||
/* Device select outputs */
|
||||
|
|
@ -71,13 +74,13 @@ module WarpSE(
|
|||
/* Select and ready signals */
|
||||
RAMCS, ROMCS, Ready_RAM,
|
||||
/* Refresh Counter Interface */
|
||||
RefReq, RefUrgent, RefAck,
|
||||
RefReq, RefUrgent,
|
||||
/* DRAM and NOR flash interface */
|
||||
RA[11:0], nRAS, nCAS,
|
||||
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
|
||||
|
||||
wire Ready_IOBS, BERR_IOBS;
|
||||
wire Park, IOREQ, IOACT, IOBERR;
|
||||
wire IOREQ, IOACT, IOBERR;
|
||||
wire ALE0S, ALE0M, ALE1;
|
||||
assign nADoutLE0 = ~(ALE0S || ALE0M);
|
||||
assign nADoutLE1 = ~ALE1;
|
||||
|
|
@ -106,38 +109,28 @@ module WarpSE(
|
|||
IOBM iobm(
|
||||
/* PDS interface */
|
||||
CLK2X_IOB, CLK_IOB, E_IOB,
|
||||
nBR_IOB, nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
|
||||
nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRES,
|
||||
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
|
||||
nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
|
||||
/* PDS address and data latch control */
|
||||
nAoutOE, nDoutOE, ALE0M, nDinLE,
|
||||
/* IO bus slave port interface */
|
||||
IOACT, IOBERR,
|
||||
Park, IOREQ, IOL0, IOU0, IORW0);
|
||||
IOREQ, IOL0, IOU0, IORW0);
|
||||
|
||||
wire TimeoutA, TimeoutB;
|
||||
wire BERRTimeout, QoSReady;
|
||||
CNT cnt(
|
||||
/* FSB clock and AS detection */
|
||||
CLK_FSB, BACT,
|
||||
/* C16M clock */
|
||||
C16M,
|
||||
/* FSB clock and bus active signal */
|
||||
FCLK, BACT,
|
||||
/* Refresh request */
|
||||
RefReq, RefUrgent, RefAck,
|
||||
/* Timeout signals */
|
||||
TimeoutA, TimeoutB);
|
||||
|
||||
/* Accelerator Disable Control */
|
||||
reg RESr0 = 0;
|
||||
reg RESr1 = 0;
|
||||
reg RESr2 = 0;
|
||||
reg IPL2r0 = 0;
|
||||
reg IPL2r1 = 0;
|
||||
reg RESDone = 0;
|
||||
reg Disable = 0;
|
||||
assign Park = ~Disable;
|
||||
always @(posedge CLK_FSB) begin
|
||||
RESr0 <= ~nRES; RESr1 <= RESr0; RESr2 <= RESr1;
|
||||
IPL2r0 <= ~nIPL2; IPL2r1 <= IPL2r0;
|
||||
if ( RESr0 && RESr1 && RESr2 && ~RESDone && IPL2r0 && IPL2r1) Disable <= 1;
|
||||
if (~RESr0 && ~RESr1 && RESr2) RESDone <= 1;
|
||||
end
|
||||
RefReq, RefUrgent,
|
||||
/* BERR and QoS speed limit output */
|
||||
BERRTimeout, QoSReady,
|
||||
/* Reset, switch, button */
|
||||
SW[3:1], nRESin, nRESout, nIPL2,
|
||||
/* Configuration outputs */
|
||||
nBR_IOB, FastROMEN, C20MEN, C25MEN);
|
||||
|
||||
FSB fsb(
|
||||
/* MC68HC000 interface */
|
||||
|
|
@ -145,9 +138,9 @@ module WarpSE(
|
|||
/* AS cycle detection */
|
||||
BACT,
|
||||
/* Ready and IA inputs */
|
||||
Ready_RAM, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable,
|
||||
Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady),
|
||||
/* BERR inputs */
|
||||
(~SCSICS && TimeoutB), BERR_IOBS,
|
||||
(~IOCS && BERRTimeout), BERR_IOBS,
|
||||
/* Interrupt acknowledge select */
|
||||
IACS);
|
||||
|
||||
|
|
|
|||
|
|
@ -22,3 +22,6 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt verilog -optimize speed -htmlr
|
|||
XSLTProcess WarpSE_build.xml
|
||||
tsim -intstyle ise WarpSE WarpSE.nga
|
||||
taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
|
||||
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||
|
|
|
|||
|
|
@ -78,16 +78,16 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1648475110" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1233756204182495024" xil_pn:start_ts="1648475056">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<transform xil_pn:end_ts="1662236554" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1233756204182495024" xil_pn:start_ts="1662236533">
|
||||
<status xil_pn:value="FailedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<outfile xil_pn:name=".lso"/>
|
||||
<outfile xil_pn:name="WarpSE.lso"/>
|
||||
<outfile xil_pn:name="WarpSE.ngc"/>
|
||||
<outfile xil_pn:name="WarpSE.ngr"/>
|
||||
<outfile xil_pn:name="WarpSE.prj"/>
|
||||
<outfile xil_pn:name="WarpSE.stx"/>
|
||||
<outfile xil_pn:name="WarpSE.syr"/>
|
||||
<outfile xil_pn:name="WarpSE.xst"/>
|
||||
<outfile xil_pn:name="WarpSE_xst.xrpt"/>
|
||||
|
|
@ -103,6 +103,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|||
|
||||
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total CPU time to Xst completion: 0.84 secs
|
||||
Total CPU time to Xst completion: 0.97 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total CPU time to Xst completion: 0.87 secs
|
||||
Total CPU time to Xst completion: 0.98 secs
|
||||
|
||||
--> Reading design: WarpSE.prj
|
||||
|
||||
|
|
@ -76,423 +76,36 @@ wysiwyg : NO
|
|||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling verilog file "../RAM.v" in library work
|
||||
Compiling verilog file "../IOBS.v" in library work
|
||||
ERROR:HDLCompilers:28 - "../RAM.v" line 63 'BACTr' has not been declared
|
||||
ERROR:HDLCompilers:26 - "../RAM.v" line 69 unexpected token: ';'
|
||||
ERROR:HDLCompilers:26 - "../RAM.v" line 75 unexpected token: 'begin'
|
||||
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting ';', found ')'
|
||||
ERROR:HDLCompilers:26 - "../RAM.v" line 76 unexpected token: '<='
|
||||
Module <RAM> compiled
|
||||
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting 'endmodule', found '0'
|
||||
Compiling verilog file "../IOBS.v" in library work
|
||||
Compiling verilog file "../IOBM.v" in library work
|
||||
Module <IOBS> compiled
|
||||
Compiling verilog file "../FSB.v" in library work
|
||||
Module <IOBM> compiled
|
||||
ERROR:HDLCompilers:28 - "../FSB.v" line 59 'BERR' has not been declared
|
||||
Compiling verilog file "../CS.v" in library work
|
||||
Module <FSB> compiled
|
||||
Compiling verilog file "../CNT.v" in library work
|
||||
Module <CS> compiled
|
||||
Compiling verilog file "../WarpSE.v" in library work
|
||||
ERROR:HDLCompilers:28 - "../CNT.v" line 29 'RefREQ' has not been declared
|
||||
ERROR:HDLCompilers:28 - "../CNT.v" line 30 'RefREQ' has not been declared
|
||||
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting ';', found '='
|
||||
Module <CNT> compiled
|
||||
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting 'endmodule', found '0'
|
||||
Compiling verilog file "../WarpSE.v" in library work
|
||||
Module <WarpSE> compiled
|
||||
No errors in compilation
|
||||
Analysis of file <"WarpSE.prj"> succeeded.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for module <WarpSE> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <CS> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <RAM> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <IOBS> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <IOBM> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <CNT> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <FSB> in library <work>.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing top module <WarpSE>.
|
||||
Module <WarpSE> is correct for synthesis.
|
||||
|
||||
Analyzing module <CS> in library <work>.
|
||||
Module <CS> is correct for synthesis.
|
||||
|
||||
Analyzing module <RAM> in library <work>.
|
||||
Module <RAM> is correct for synthesis.
|
||||
|
||||
Analyzing module <IOBS> in library <work>.
|
||||
Module <IOBS> is correct for synthesis.
|
||||
|
||||
Analyzing module <IOBM> in library <work>.
|
||||
Module <IOBM> is correct for synthesis.
|
||||
|
||||
Analyzing module <CNT> in library <work>.
|
||||
Module <CNT> is correct for synthesis.
|
||||
|
||||
Analyzing module <FSB> in library <work>.
|
||||
Module <FSB> is correct for synthesis.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
|
||||
Synthesizing Unit <CS>.
|
||||
Related source file is "../CS.v".
|
||||
Found 1-bit register for signal <nOverlay0>.
|
||||
Found 1-bit register for signal <nOverlay1>.
|
||||
Summary:
|
||||
inferred 2 D-type flip-flop(s).
|
||||
Unit <CS> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <RAM>.
|
||||
Related source file is "../RAM.v".
|
||||
Found finite state machine <FSM_0> for signal <RS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 8 |
|
||||
| Transitions | 18 |
|
||||
| Inputs | 6 |
|
||||
| Outputs | 9 |
|
||||
| Clock | CLK (rising_edge) |
|
||||
| Power Up State | 000 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <nCAS>.
|
||||
Found 1-bit register for signal <BACTr>.
|
||||
Found 1-bit register for signal <Once>.
|
||||
Found 1-bit register for signal <RAMDIS1>.
|
||||
Found 1-bit register for signal <RAMDIS2>.
|
||||
Found 1-bit register for signal <RAMReady>.
|
||||
Found 1-bit register for signal <RASEL>.
|
||||
Found 1-bit register for signal <RefRAS>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 6 D-type flip-flop(s).
|
||||
Unit <RAM> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <IOBS>.
|
||||
Related source file is "../IOBS.v".
|
||||
Found finite state machine <FSM_1> for signal <PS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 4 |
|
||||
| Transitions | 10 |
|
||||
| Inputs | 5 |
|
||||
| Outputs | 5 |
|
||||
| Clock | CLK (rising_edge) |
|
||||
| Power Up State | 00 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <BERR>.
|
||||
Found 1-bit register for signal <IOREQ>.
|
||||
Found 1-bit register for signal <IORW0>.
|
||||
Found 1-bit register for signal <IOL0>.
|
||||
Found 1-bit register for signal <IOU0>.
|
||||
Found 1-bit register for signal <ALE0>.
|
||||
Found 1-bit register for signal <ALE1>.
|
||||
Found 1-bit register for signal <Clear1>.
|
||||
Found 1-bit register for signal <IOACTr>.
|
||||
Found 1-bit register for signal <IOL1>.
|
||||
Found 1-bit register for signal <IOReady>.
|
||||
Found 1-bit register for signal <IORW1>.
|
||||
Found 1-bit register for signal <IOU1>.
|
||||
Found 1-bit register for signal <Load1>.
|
||||
Found 1-bit register for signal <Once>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 9 D-type flip-flop(s).
|
||||
Unit <IOBS> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <IOBM>.
|
||||
Related source file is "../IOBM.v".
|
||||
Found finite state machine <FSM_2> for signal <IOS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 8 |
|
||||
| Transitions | 16 |
|
||||
| Inputs | 7 |
|
||||
| Outputs | 8 |
|
||||
| Clock | C16M (rising_edge) |
|
||||
| Power Up State | 000 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <IOBERR>.
|
||||
Found 1-bit register for signal <nASout>.
|
||||
Found 1-bit register for signal <IOACT>.
|
||||
Found 1-bit register for signal <nLDS>.
|
||||
Found 1-bit register for signal <nUDS>.
|
||||
Found 1-bit register for signal <nDinLE>.
|
||||
Found 1-bit register for signal <nDoutOE>.
|
||||
Found 1-bit register for signal <ALE0>.
|
||||
Found 1-bit register for signal <nVMA>.
|
||||
Found 1-bit register for signal <BERRrf>.
|
||||
Found 1-bit register for signal <BERRrr>.
|
||||
Found 1-bit register for signal <BG>.
|
||||
Found 1-bit register for signal <BGr0>.
|
||||
Found 1-bit register for signal <BGr1>.
|
||||
Found 1-bit register for signal <DTACKrf>.
|
||||
Found 1-bit register for signal <DTACKrr>.
|
||||
Found 1-bit register for signal <Er>.
|
||||
Found 1-bit register for signal <Er2>.
|
||||
Found 5-bit up counter for signal <ES>.
|
||||
Found 1-bit register for signal <ETACK>.
|
||||
Found 1-bit register for signal <IOREQr>.
|
||||
Found 1-bit register for signal <RESrf>.
|
||||
Found 1-bit register for signal <RESrr>.
|
||||
Found 1-bit register for signal <VPArf>.
|
||||
Found 1-bit register for signal <VPArr>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 1 Counter(s).
|
||||
inferred 22 D-type flip-flop(s).
|
||||
Unit <IOBM> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <CNT>.
|
||||
Related source file is "../CNT.v".
|
||||
Found 1-bit register for signal <TimeoutA>.
|
||||
Found 1-bit register for signal <TimeoutB>.
|
||||
Found 8-bit up counter for signal <RefCnt>.
|
||||
Found 1-bit register for signal <RefDone>.
|
||||
Found 1-bit register for signal <TimeoutBPre>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
Unit <CNT> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <FSB>.
|
||||
Related source file is "../FSB.v".
|
||||
Found 1-bit register for signal <nDTACK>.
|
||||
Found 1-bit register for signal <ASrf>.
|
||||
Found 1-bit register for signal <BERR0r>.
|
||||
Found 1-bit register for signal <BERR1r>.
|
||||
Found 1-bit register for signal <Ready0r>.
|
||||
Found 1-bit register for signal <Ready1r>.
|
||||
Found 1-bit register for signal <Ready2r>.
|
||||
Found 1-bit register for signal <VPA>.
|
||||
Summary:
|
||||
inferred 1 D-type flip-flop(s).
|
||||
Unit <FSB> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <WarpSE>.
|
||||
Related source file is "../WarpSE.v".
|
||||
WARNING:Xst:647 - Input <SW<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Found 1-bit tristate buffer for signal <nAS_IOB>.
|
||||
Found 1-bit tristate buffer for signal <nLDS_IOB>.
|
||||
Found 1-bit tristate buffer for signal <nUDS_IOB>.
|
||||
Found 1-bit tristate buffer for signal <nVMA_IOB>.
|
||||
Found 1-bit register for signal <Disable>.
|
||||
Found 1-bit register for signal <IPL2r0>.
|
||||
Found 1-bit register for signal <IPL2r1>.
|
||||
Found 1-bit register for signal <RESDone>.
|
||||
Found 1-bit register for signal <RESr0>.
|
||||
Found 1-bit register for signal <RESr1>.
|
||||
Found 1-bit register for signal <RESr2>.
|
||||
Summary:
|
||||
inferred 7 D-type flip-flop(s).
|
||||
inferred 4 Tristate(s).
|
||||
Unit <WarpSE> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Counters : 2
|
||||
5-bit up counter : 1
|
||||
8-bit up counter : 1
|
||||
# Registers : 68
|
||||
1-bit register : 68
|
||||
# Tristates : 4
|
||||
1-bit tristate buffer : 4
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Analyzing FSM <FSM_2> for best encoding.
|
||||
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:3]> with gray encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
-------------------
|
||||
000 | 000
|
||||
001 | 001
|
||||
010 | 011
|
||||
011 | 010
|
||||
100 | 110
|
||||
101 | 111
|
||||
110 | 101
|
||||
111 | 100
|
||||
-------------------
|
||||
Analyzing FSM <FSM_1> for best encoding.
|
||||
Optimizing FSM <iobs/PS/FSM> on signal <PS[1:2]> with johnson encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
-------------------
|
||||
00 | 00
|
||||
11 | 01
|
||||
10 | 11
|
||||
01 | 10
|
||||
-------------------
|
||||
Analyzing FSM <FSM_0> for best encoding.
|
||||
Optimizing FSM <ram/RS/FSM> on signal <RS[1:3]> with compact encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
-------------------
|
||||
000 | 000
|
||||
010 | 010
|
||||
101 | 001
|
||||
001 | 101
|
||||
011 | 011
|
||||
100 | 111
|
||||
111 | 100
|
||||
110 | 110
|
||||
-------------------
|
||||
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone.
|
||||
You should achieve better results by setting this init to 1.
|
||||
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable.
|
||||
You should achieve better results by setting this init to 1.
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# FSMs : 3
|
||||
# Counters : 2
|
||||
5-bit up counter : 1
|
||||
8-bit up counter : 1
|
||||
# Registers : 47
|
||||
Flip-Flops : 47
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
WARNING:Xst:1426 - The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE.
|
||||
You should achieve better results by setting this init to 1.
|
||||
WARNING:Xst:1426 - The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE.
|
||||
You should achieve better results by setting this init to 1.
|
||||
|
||||
Optimizing unit <WarpSE> ...
|
||||
implementation constraint: INIT=r : RESr0
|
||||
implementation constraint: INIT=r : RESr1
|
||||
implementation constraint: INIT=r : RESr2
|
||||
implementation constraint: INIT=r : IPL2r0
|
||||
implementation constraint: INIT=r : IPL2r1
|
||||
implementation constraint: INIT=r : Disable
|
||||
implementation constraint: INIT=r : RESDone
|
||||
implementation constraint: INIT=r : ram/RAMReady
|
||||
implementation constraint: INIT=r : ram/RASEL
|
||||
implementation constraint: INIT=r : ram/RAMDIS1
|
||||
implementation constraint: INIT=r : ram/RefRAS
|
||||
implementation constraint: INIT=r : ram/RAMDIS2
|
||||
implementation constraint: INIT=r : ram/Once
|
||||
implementation constraint: INIT=r : iobs/IOACTr
|
||||
implementation constraint: INIT=r : ram/RS_FSM_FFd1
|
||||
implementation constraint: INIT=r : iobs/Once
|
||||
implementation constraint: INIT=r : cs/nOverlay0
|
||||
implementation constraint: INIT=r : cs/nOverlay1
|
||||
implementation constraint: INIT=r : iobs/PS_FSM_FFd1
|
||||
implementation constraint: INIT=r : iobs/PS_FSM_FFd2
|
||||
implementation constraint: INIT=r : iobm/ETACK
|
||||
implementation constraint: INIT=r : iobm/BGr0
|
||||
implementation constraint: INIT=r : iobm/BGr1
|
||||
implementation constraint: INIT=r : iobm/BG
|
||||
implementation constraint: INIT=r : iobm/IOREQr
|
||||
implementation constraint: INIT=r : fsb/ASrf
|
||||
implementation constraint: INIT=r : ram/RS_FSM_FFd2
|
||||
implementation constraint: INIT=r : cnt/RefDone
|
||||
implementation constraint: INIT=r : cnt/RefCnt_0
|
||||
implementation constraint: INIT=r : cnt/RefCnt_1
|
||||
implementation constraint: INIT=r : cnt/RefCnt_2
|
||||
implementation constraint: INIT=r : cnt/RefCnt_3
|
||||
implementation constraint: INIT=r : cnt/RefCnt_4
|
||||
implementation constraint: INIT=r : cnt/RefCnt_5
|
||||
implementation constraint: INIT=r : cnt/RefCnt_6
|
||||
implementation constraint: INIT=r : cnt/RefCnt_7
|
||||
implementation constraint: INIT=r : ram/RS_FSM_FFd3
|
||||
implementation constraint: INIT=r : iobm/IOS_FSM_FFd1
|
||||
implementation constraint: INIT=r : iobm/IOS_FSM_FFd2
|
||||
implementation constraint: INIT=r : iobm/IOS_FSM_FFd3
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : WarpSE.ngr
|
||||
Top Level Output File Name : WarpSE
|
||||
Output Format : NGC
|
||||
Optimization Goal : Speed
|
||||
Keep Hierarchy : No
|
||||
Target Technology : XC9500XL CPLDs
|
||||
Macro Preserve : YES
|
||||
XOR Preserve : YES
|
||||
Clock Enable : YES
|
||||
wysiwyg : NO
|
||||
|
||||
Design Statistics
|
||||
# IOs : 75
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 596
|
||||
# AND2 : 165
|
||||
# AND3 : 25
|
||||
# AND4 : 15
|
||||
# AND5 : 3
|
||||
# AND6 : 1
|
||||
# AND7 : 1
|
||||
# AND8 : 3
|
||||
# GND : 1
|
||||
# INV : 265
|
||||
# OR2 : 98
|
||||
# OR3 : 5
|
||||
# OR4 : 1
|
||||
# VCC : 1
|
||||
# XOR2 : 12
|
||||
# FlipFlops/Latches : 89
|
||||
# FD : 60
|
||||
# FDCE : 29
|
||||
# Tri-States : 1
|
||||
# BUFE : 1
|
||||
# IO Buffers : 74
|
||||
# IBUF : 39
|
||||
# OBUF : 31
|
||||
# OBUFE : 4
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 39.00 secs
|
||||
Total CPU time to Xst completion: 38.76 secs
|
||||
|
||||
Analysis of file <"WarpSE.prj"> failed.
|
||||
-->
|
||||
|
||||
Total memory usage is 236884 kilobytes
|
||||
Total memory usage is 190552 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 5 ( 0 filtered)
|
||||
Number of errors : 11 ( 0 filtered)
|
||||
Number of warnings : 0 ( 0 filtered)
|
||||
Number of infos : 0 ( 0 filtered)
|
||||
|
||||
|
|
|
|||
|
|
@ -2,30 +2,31 @@
|
|||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (09/03/2022 - 16:22:34)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpSE.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD> No Errors </TD>
|
||||
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>2 Errors</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>WarpSE</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Synthesized</TD>
|
||||
<TD>Synthesized (Failed)</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc95144xl-10TQ100</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
<font color="red"; face="Arial"><b>X </b></font>
|
||||
<A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/*.xmsgs?&DataKey=Error'>11 Errors (11 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/*.xmsgs?&DataKey=Warning'>5 Warnings (0 new)</A></TD>
|
||||
<TD ALIGN=LEFT>No Warnings</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
|
|
@ -43,7 +44,7 @@ No Errors</TD>
|
|||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\WarpSE_envsettings.html'>
|
||||
<A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
|
|
@ -65,9 +66,9 @@ System Settings</A>
|
|||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed May 25 00:14:13 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>5 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Mon Mar 28 09:45:45 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Out of Date</TD><TD>Mon Mar 28 09:46:19 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>2 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Sep 3 16:22:35 2022</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Error'>11 Errors (11 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Mon Mar 28 09:45:45 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Out of Date</TD><TD>Mon Mar 28 09:46:19 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>2 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
|
|
@ -77,5 +78,5 @@ System Settings</A>
|
|||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 05/25/2022 - 21:10:23</center>
|
||||
<br><center><b>Date Generated:</b> 09/03/2022 - 17:36:27</center>
|
||||
</BODY></HTML>
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Mon Mar 28 09:44:30 2022">
|
||||
<application stringID="Xst" timeStamp="Sat Sep 03 16:22:30 2022">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
|
|
@ -78,63 +78,9 @@
|
|||
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
|
||||
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="2"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="68">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="68"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="4">
|
||||
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_FSMS" value="3"/>
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="2"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="47">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="47"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REPORT">
|
||||
<section stringID="XST_FINAL_RESULTS">
|
||||
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpSE.ngr"/>
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="WarpSE"/>
|
||||
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
|
||||
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
|
||||
<item stringID="XST_KEEP_HIERARCHY" value="No"/>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_STATISTICS">
|
||||
<item stringID="XST_IOS" value="75"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="596">
|
||||
<item dataType="int" stringID="XST_AND2" value="165"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="25"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="15"/>
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="265"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="98"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="12"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="89">
|
||||
<item dataType="int" stringID="XST_FD" value="60"/>
|
||||
<item dataType="int" stringID="XST_FDCE" value="29"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="1"></item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="74">
|
||||
<item dataType="int" stringID="XST_IBUF" value="39"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="31"/>
|
||||
</item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="5"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="11"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
|
||||
</section>
|
||||
</application>
|
||||
|
|
|
|||
|
|
@ -8,25 +8,19 @@
|
|||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/CNT.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Warp-SE/cpld/CNT.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/CS.v" into library work</arg>
|
||||
<msg type="error" file="ProjectMgmt" num="806" >"<arg fmt="%s" index="1">Z:/Warp-SE/cpld/CNT.v</arg>" Line <arg fmt="%d" index="2">127</arg>. <arg fmt="%s" index="3">Syntax error near "<=".</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/FSB.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Warp-SE/cpld/IOBM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/IOBM.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Warp-SE/cpld/RAM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/IOBS.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/RAM.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/WarpSE.v" into library work</arg>
|
||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Warp-SE/cpld/WarpSE.v" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
|
|
|||
|
|
@ -5,23 +5,37 @@
|
|||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">SW<2></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">"../RAM.v" line 63 </arg>'<arg fmt="%s" index="2">BACTr</arg>' has not been declared
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">RESDone</arg>.
|
||||
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../RAM.v</arg>" line <arg fmt="%d" index="2">69</arg> <arg fmt="%s" index="3">unexpected token: ';'</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">Disable</arg>.
|
||||
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../RAM.v</arg>" line <arg fmt="%d" index="2">75</arg> <arg fmt="%s" index="3">unexpected token: 'begin'</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">RESDone</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">WarpSE</arg>.
|
||||
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../RAM.v</arg>" line <arg fmt="%d" index="2">76</arg> <arg fmt="%s" index="3">expecting ';', found ')'</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">Disable</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">WarpSE</arg>.
|
||||
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../RAM.v</arg>" line <arg fmt="%d" index="2">76</arg> <arg fmt="%s" index="3">unexpected token: '<='</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../RAM.v</arg>" line <arg fmt="%d" index="2">76</arg> <arg fmt="%s" index="3">expecting 'endmodule', found '0'</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">"../FSB.v" line 59 </arg>'<arg fmt="%s" index="2">BERR</arg>' has not been declared
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">"../CNT.v" line 29 </arg>'<arg fmt="%s" index="2">RefREQ</arg>' has not been declared
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">"../CNT.v" line 30 </arg>'<arg fmt="%s" index="2">RefREQ</arg>' has not been declared
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../CNT.v</arg>" line <arg fmt="%d" index="2">34</arg> <arg fmt="%s" index="3">expecting ';', found '='</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="HDLCompilers" num="26" delta="new" >"<arg fmt="%s" index="1">../CNT.v</arg>" line <arg fmt="%d" index="2">34</arg> <arg fmt="%s" index="3">expecting 'endmodule', found '0'</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
|
|
|||
|
|
@ -25,13 +25,13 @@
|
|||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>Generate Timing</SelectedItem>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>Generate Timing</CurrentItem>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2022-05-25T21:10:24</DateModified>
|
||||
<DateModified>2022-09-03T14:17:57</DateModified>
|
||||
<ModuleName>WarpSE</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>//192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
|
||||
<SavedFilePath>Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>Z:/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2022-03-28T09:29:43</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Mon Mar 28 09:44:18 2022">
|
||||
<application name="pn" timeStamp="Sat Sep 03 16:22:17 2022">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1648475072
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1648475072
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1648475072
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1648475072
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1662227042
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1662227042
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1662227042
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1648475072
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1648475072
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1648475071
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1662227042
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1662227042
|
||||
MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1648473402
|
||||
|
|
|
|||
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Loading…
Reference in New Issue