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More comments in RAM controller

This commit is contained in:
Zane Kaminski 2023-04-15 07:12:24 -04:00
parent 5d8cb62df3
commit c003bd2581
1 changed files with 7 additions and 3 deletions
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10
cpld/RAM.v
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@ -61,10 +61,14 @@ module RAM(
assign RA[01] = !RASEL ? A[10] : A[02];
assign RA[00] = !RASEL ? A[09] : A[01];
wire RS0toRef = (RefReq && BACT && !BACTr && !RAMCS0X) ||
(RefUrg && !RASEN) ||
wire RS0toRef = // Refresh during first clock of non-RAM access
(RefReq && BACT && !BACTr && !RAMCS0X) ||
// Urgent refresh while bus inactive
(RefUrg && !BACT) ||
// Urgent refresh during non-RAM access
(RefUrg && BACT && !RAMCS0X) ||
(RefUrg && !BACT);
// Urgent refresh if RAM is disabled
(RefUrg && !RASEN);
always @(posedge CLK) begin
case (RS[2:0])