mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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Merge branch 'dev' of https://github.com/garrettsworkshop/Warp-SE into dev
This commit is contained in:
Zane Kaminski
commit
c267021391
10
cpld/CNT.v
10
cpld/CNT.v
@ -55,7 +55,7 @@ module CNT(
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* 4096 states == 57.516 ms
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* During operation (IS==3) long timer counts from 0 to 3
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* starting at first sound RAM access.
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* 4 states == 56.168 us */
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* Period is 28.124 us - 42.240 us */
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reg [11:0] LTimer;
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reg LTimerTC;
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always @(posedge CLK) begin
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@ -81,21 +81,21 @@ module CNT(
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wire ISTC = EFall && TimerTC && LTimerTC;
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always @(posedge CLK) begin
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case (IS[1:0])
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2'h0: begin
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0: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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if (ISTC) IS <= 1;
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end 2'h1: begin
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end 1: begin
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AoutOE <= 0;
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nRESout <= 0;
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nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
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if (ISTC && nIPL2r) IS <= 2;
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end 2'h2: begin
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end 2: begin
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AoutOE <= !nBR_IOB;
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nRESout <= 0;
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if (ISTC) IS <= 3;
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end 2'h3: begin
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end 3: begin
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nRESout <= 1; // Release reset
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IS <= 3;
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end
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42
cpld/CS.v
42
cpld/CS.v
@ -10,41 +10,37 @@ module CS(
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/* Overlay control */
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reg nOverlay = 0; wire Overlay = !nOverlay;
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reg ODCSr;
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always @(posedge CLK) begin
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ODCSr <= ROMCS4X && BACT;
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if (!BACT) begin
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if (!nRES) nOverlay <= 0;
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else if (ODCSr) nOverlay <= 1;
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end
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if (!BACT && !nRES) nOverlay <= 0;
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else if (BACT && ROMCS4X) nOverlay <= 1;
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end
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/* ROM select signals */
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assign ROMCS4X = A[23:20]==4'h4;
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assign ROMCS = ((A[23:20]==4'h0) && Overlay) || ROMCS4X;
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assign ROMCS = (A[23:20]==4'h0 && Overlay) || ROMCS4X;
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assign SndROMCS = ROMCS4X &&
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(A[20:8]==12'h36C || A[20:8]==12'h36D || A[20:8]==12'h36F);
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/* RAM select signals */
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assign RAMCS0X = A[23:22]==2'b00;
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assign RAMCS = RAMCS0X && !Overlay;
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wire VidRAMCSWR64k = RAMCS0X && !nWE && (A[23:20]==4'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF
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wire VidRAMCSWR64k = RAMCS0X && !nWE && A[23:16]==8'h3F; // 3F0000-3FFFFF
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wire VidRAMCSWR = VidRAMCSWR64k && (
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(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
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(A[15:12]==4'h3) || // 4096 bytes video
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(A[15:12]==4'h4) || // 4096 bytes video
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(A[15:12]==4'h5) || // 4096 bytes video
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(A[15:12]==4'h6) || // 4096 bytes video
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(A[15:12]==4'h7) || // 3200 bytes video, 896 bytes RAM
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(A[15:12]==4'hA) || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
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(A[15:12]==4'hB) || // 4096 bytes video
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(A[15:12]==4'hC) || // 4096 bytes video
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(A[15:12]==4'hD) || // 4096 bytes video
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(A[15:12]==4'hE) || // 4096 bytes video
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(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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A[15:12]==4'h2 || // 1792 bytes RAM, 2304 bytes video
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A[15:12]==4'h3 || // 4096 bytes video
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A[15:12]==4'h4 || // 4096 bytes video
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A[15:12]==4'h5 || // 4096 bytes video
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A[15:12]==4'h6 || // 4096 bytes video
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A[15:12]==4'h7 || // 3200 bytes video, 896 bytes RAM
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A[15:12]==4'hA || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
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A[15:12]==4'hB || // 4096 bytes video
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A[15:12]==4'hC || // 4096 bytes video
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A[15:12]==4'hD || // 4096 bytes video
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A[15:12]==4'hE || // 4096 bytes video
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A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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assign SndRAMCSWR = VidRAMCSWR64k && (
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((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) ||
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((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
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((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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/* Select signals - IOB domain */
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assign IACS = A[23:16]==8'hFF; // IACK
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@ -60,6 +56,6 @@ module CS(
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A[23:20]==4'h6 || // empty
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A[23:20]==4'h5 || // SCSI
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(A[23:20]==4'h4 && Overlay) || // ROM once
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VidRAMCSWR; // Write to video RAM
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VidRAMCSWR; // Write to video RAM
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assign IOPWCS = VidRAMCSWR;
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endmodule
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@ -18,10 +18,9 @@ module FSB(
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/* DTACK/VPA control */
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wire Ready = QoSReady &&
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((RAMCS && RAMReady && !IOPWCS) ||
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(RAMCS && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS) || (IONPReady));
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wire Ready = (QoSReady && RAMCS && RAMReady && !IOPWCS) ||
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(QoSReady && RAMCS && RAMReady && IOPWCS && IOPWReady) ||
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(QoSReady && ROMCS) || (IONPReady);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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21
cpld/IOBS.v
21
cpld/IOBS.v
@ -6,7 +6,7 @@ module IOBS(
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/* Select signals */
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input IOCS, input IOPWCS, input ROMCS,
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/* FSB cycle termination outputs */
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output reg IONPReady, output reg IOPWReady, output reg nBERR_FSB,
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output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
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/* Read data OE control */
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output nDinOE,
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/* IOB master controller interface */
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@ -42,11 +42,8 @@ module IOBS(
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reg Sent = 0;
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/* FIFO secondary level control */
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reg Load1;
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reg Clear1;
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reg IORW1;
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reg IOL1;
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reg IOU1;
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reg Load1; reg Clear1;
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reg IORW1; reg IOL1; reg IOU1;
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always @(posedge CLK) begin // ALE and R/W load control
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// If write currently posting (TS!=0),
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// I/O selected, and FIFO secondary level empty
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@ -128,19 +125,13 @@ module IOBS(
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else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
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end
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/* Nonposted ready */
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always @(posedge CLK) begin
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/* Nonposted and posted ready */
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assign IOPWReady = !ALE1; // Posted write reaedy
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always @(posedge CLK) begin // Nonposted read/write ready
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if (!BACT) IONPReady <= 0;
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else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
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end
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/* Posted ready */
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always @(posedge CLK) begin
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if (Clear1) IOPWReady <= 1;
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else if (Load1) IOPWReady <= 0;
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else IOPWReady <= !ALE1;
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end
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/* BERR control */
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always @(posedge CLK) begin
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if (!BACT) nBERR_FSB <= 1;
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10
cpld/RAM.v
10
cpld/RAM.v
@ -4,7 +4,7 @@ module RAM(
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/* AS cycle detection */
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input BACT,
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/* Select and ready signals */
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input RAMCS, input ROMCS, output reg RAMReady,
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input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady,
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/* Refresh Counter Interface */
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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@ -16,8 +16,8 @@ module RAM(
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/* RAM control state */
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reg [2:0] RS = 0;
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reg RAMEN = 0;
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reg Once = 0;
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reg RAMEN = 0;
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reg RASEL = 0;
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reg CAS = 0;
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reg RASrr = 0;
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@ -59,8 +59,10 @@ module RAM(
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[00] = !RASEL ? A[09] : A[01];
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wire RefFromRS0 = ((RefReq && !BACT) ||
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(RefUrg && !BACT));
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wire RefFromRS0 = ((RefReq && BACT && !BACTr && !RAMCS0X) ||
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(RefUrg && !BACT) ||
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && BACT && !RAMEN && !nWE));
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wire RefFromRS2 = RefUrg;
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wire RAMStart = BACT && RAMCS && RAMEN;
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always @(posedge CLK) begin
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@ -75,7 +75,7 @@ module WarpSE(
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/* AS cycle detection */
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BACT,
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/* Select and ready signals */
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RAMCS, ROMCS, RAMReady,
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RAMCS, RAMCS0X, ROMCS, RAMReady,
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/* Refresh Counter Interface */
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RefReq, RefUrg,
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/* DRAM and NOR flash interface */
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