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Merge branch 'dev' of https://github.com/garrettsworkshop/Warp-SE into dev

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This commit is contained in:
Zane Kaminski 2023-04-09 23:18:40 -04:00
commit c267021391
6 changed files with 40 additions and 52 deletions
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10
cpld/CNT.v
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@ -55,7 +55,7 @@ module CNT(
* 4096 states == 57.516 ms * 4096 states == 57.516 ms
* During operation (IS==3) long timer counts from 0 to 3 * During operation (IS==3) long timer counts from 0 to 3
* starting at first sound RAM access. * starting at first sound RAM access.
* 4 states == 56.168 us */ * Period is 28.124 us - 42.240 us */
reg [11:0] LTimer; reg [11:0] LTimer;
reg LTimerTC; reg LTimerTC;
always @(posedge CLK) begin always @(posedge CLK) begin
@ -81,21 +81,21 @@ module CNT(
wire ISTC = EFall && TimerTC && LTimerTC; wire ISTC = EFall && TimerTC && LTimerTC;
always @(posedge CLK) begin always @(posedge CLK) begin
case (IS[1:0]) case (IS[1:0])
2'h0: begin 0: begin
AoutOE <= 0; // Tristate PDS address and control AoutOE <= 0; // Tristate PDS address and control
nRESout <= 0; // Hold reset low nRESout <= 0; // Hold reset low
nBR_IOB <= 0; // Default to request bus nBR_IOB <= 0; // Default to request bus
if (ISTC) IS <= 1; if (ISTC) IS <= 1;
end 2'h1: begin end 1: begin
AoutOE <= 0; AoutOE <= 0;
nRESout <= 0; nRESout <= 0;
nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
if (ISTC && nIPL2r) IS <= 2; if (ISTC && nIPL2r) IS <= 2;
end 2'h2: begin end 2: begin
AoutOE <= !nBR_IOB; AoutOE <= !nBR_IOB;
nRESout <= 0; nRESout <= 0;
if (ISTC) IS <= 3; if (ISTC) IS <= 3;
end 2'h3: begin end 3: begin
nRESout <= 1; // Release reset nRESout <= 1; // Release reset
IS <= 3; IS <= 3;
end end

40
cpld/CS.v
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@ -10,41 +10,37 @@ module CS(
/* Overlay control */ /* Overlay control */
reg nOverlay = 0; wire Overlay = !nOverlay; reg nOverlay = 0; wire Overlay = !nOverlay;
reg ODCSr;
always @(posedge CLK) begin always @(posedge CLK) begin
ODCSr <= ROMCS4X && BACT; if (!BACT && !nRES) nOverlay <= 0;
if (!BACT) begin else if (BACT && ROMCS4X) nOverlay <= 1;
if (!nRES) nOverlay <= 0;
else if (ODCSr) nOverlay <= 1;
end
end end
/* ROM select signals */ /* ROM select signals */
assign ROMCS4X = A[23:20]==4'h4; assign ROMCS4X = A[23:20]==4'h4;
assign ROMCS = ((A[23:20]==4'h0) && Overlay) || ROMCS4X; assign ROMCS = (A[23:20]==4'h0 && Overlay) || ROMCS4X;
assign SndROMCS = ROMCS4X && assign SndROMCS = ROMCS4X &&
(A[20:8]==12'h36C || A[20:8]==12'h36D || A[20:8]==12'h36F); (A[20:8]==12'h36C || A[20:8]==12'h36D || A[20:8]==12'h36F);
/* RAM select signals */ /* RAM select signals */
assign RAMCS0X = A[23:22]==2'b00; assign RAMCS0X = A[23:22]==2'b00;
assign RAMCS = RAMCS0X && !Overlay; assign RAMCS = RAMCS0X && !Overlay;
wire VidRAMCSWR64k = RAMCS0X && !nWE && (A[23:20]==4'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF wire VidRAMCSWR64k = RAMCS0X && !nWE && A[23:16]==8'h3F; // 3F0000-3FFFFF
wire VidRAMCSWR = VidRAMCSWR64k && ( wire VidRAMCSWR = VidRAMCSWR64k && (
(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video A[15:12]==4'h2 || // 1792 bytes RAM, 2304 bytes video
(A[15:12]==4'h3) || // 4096 bytes video A[15:12]==4'h3 || // 4096 bytes video
(A[15:12]==4'h4) || // 4096 bytes video A[15:12]==4'h4 || // 4096 bytes video
(A[15:12]==4'h5) || // 4096 bytes video A[15:12]==4'h5 || // 4096 bytes video
(A[15:12]==4'h6) || // 4096 bytes video A[15:12]==4'h6 || // 4096 bytes video
(A[15:12]==4'h7) || // 3200 bytes video, 896 bytes RAM A[15:12]==4'h7 || // 3200 bytes video, 896 bytes RAM
(A[15:12]==4'hA) || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video A[15:12]==4'hA || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
(A[15:12]==4'hB) || // 4096 bytes video A[15:12]==4'hB || // 4096 bytes video
(A[15:12]==4'hC) || // 4096 bytes video A[15:12]==4'hC || // 4096 bytes video
(A[15:12]==4'hD) || // 4096 bytes video A[15:12]==4'hD || // 4096 bytes video
(A[15:12]==4'hE) || // 4096 bytes video A[15:12]==4'hE || // 4096 bytes video
(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
assign SndRAMCSWR = VidRAMCSWR64k && ( assign SndRAMCSWR = VidRAMCSWR64k && (
((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) || ((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3)))); ((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
/* Select signals - IOB domain */ /* Select signals - IOB domain */
assign IACS = A[23:16]==8'hFF; // IACK assign IACS = A[23:16]==8'hFF; // IACK

7
cpld/FSB.v
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@ -18,10 +18,9 @@ module FSB(
/* DTACK/VPA control */ /* DTACK/VPA control */
wire Ready = QoSReady && wire Ready = (QoSReady && RAMCS && RAMReady && !IOPWCS) ||
((RAMCS && RAMReady && !IOPWCS) || (QoSReady && RAMCS && RAMReady && IOPWCS && IOPWReady) ||
(RAMCS && RAMReady && IOPWCS && IOPWReady) || (QoSReady && ROMCS) || (IONPReady);
(ROMCS) || (IONPReady));
always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS); always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
always @(posedge FCLK, posedge nAS) begin always @(posedge FCLK, posedge nAS) begin
if (nAS) nVPA <= 1; if (nAS) nVPA <= 1;

21
cpld/IOBS.v
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@ -6,7 +6,7 @@ module IOBS(
/* Select signals */ /* Select signals */
input IOCS, input IOPWCS, input ROMCS, input IOCS, input IOPWCS, input ROMCS,
/* FSB cycle termination outputs */ /* FSB cycle termination outputs */
output reg IONPReady, output reg IOPWReady, output reg nBERR_FSB, output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
/* Read data OE control */ /* Read data OE control */
output nDinOE, output nDinOE,
/* IOB master controller interface */ /* IOB master controller interface */
@ -42,11 +42,8 @@ module IOBS(
reg Sent = 0; reg Sent = 0;
/* FIFO secondary level control */ /* FIFO secondary level control */
reg Load1; reg Load1; reg Clear1;
reg Clear1; reg IORW1; reg IOL1; reg IOU1;
reg IORW1;
reg IOL1;
reg IOU1;
always @(posedge CLK) begin // ALE and R/W load control always @(posedge CLK) begin // ALE and R/W load control
// If write currently posting (TS!=0), // If write currently posting (TS!=0),
// I/O selected, and FIFO secondary level empty // I/O selected, and FIFO secondary level empty
@ -128,19 +125,13 @@ module IOBS(
else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1; else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
end end
/* Nonposted ready */ /* Nonposted and posted ready */
always @(posedge CLK) begin assign IOPWReady = !ALE1; // Posted write reaedy
always @(posedge CLK) begin // Nonposted read/write ready
if (!BACT) IONPReady <= 0; if (!BACT) IONPReady <= 0;
else if (Sent && !IOPWCS && IODONE) IONPReady <= 1; else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
end end
/* Posted ready */
always @(posedge CLK) begin
if (Clear1) IOPWReady <= 1;
else if (Load1) IOPWReady <= 0;
else IOPWReady <= !ALE1;
end
/* BERR control */ /* BERR control */
always @(posedge CLK) begin always @(posedge CLK) begin
if (!BACT) nBERR_FSB <= 1; if (!BACT) nBERR_FSB <= 1;

10
cpld/RAM.v
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@ -4,7 +4,7 @@ module RAM(
/* AS cycle detection */ /* AS cycle detection */
input BACT, input BACT,
/* Select and ready signals */ /* Select and ready signals */
input RAMCS, input ROMCS, output reg RAMReady, input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady,
/* Refresh Counter Interface */ /* Refresh Counter Interface */
input RefReqIn, input RefUrgIn, input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */ /* DRAM and NOR flash interface */
@ -16,8 +16,8 @@ module RAM(
/* RAM control state */ /* RAM control state */
reg [2:0] RS = 0; reg [2:0] RS = 0;
reg RAMEN = 0;
reg Once = 0; reg Once = 0;
reg RAMEN = 0;
reg RASEL = 0; reg RASEL = 0;
reg CAS = 0; reg CAS = 0;
reg RASrr = 0; reg RASrr = 0;
@ -59,8 +59,10 @@ module RAM(
assign RA[01] = !RASEL ? A[10] : A[02]; assign RA[01] = !RASEL ? A[10] : A[02];
assign RA[00] = !RASEL ? A[09] : A[01]; assign RA[00] = !RASEL ? A[09] : A[01];
wire RefFromRS0 = ((RefReq && !BACT) || wire RefFromRS0 = ((RefReq && BACT && !BACTr && !RAMCS0X) ||
(RefUrg && !BACT)); (RefUrg && !BACT) ||
(RefUrg && BACT && !RAMCS0X) ||
(RefUrg && BACT && !RAMEN && !nWE));
wire RefFromRS2 = RefUrg; wire RefFromRS2 = RefUrg;
wire RAMStart = BACT && RAMCS && RAMEN; wire RAMStart = BACT && RAMCS && RAMEN;
always @(posedge CLK) begin always @(posedge CLK) begin

2
cpld/WarpSE.v
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@ -75,7 +75,7 @@ module WarpSE(
/* AS cycle detection */ /* AS cycle detection */
BACT, BACT,
/* Select and ready signals */ /* Select and ready signals */
RAMCS, ROMCS, RAMReady, RAMCS, RAMCS0X, ROMCS, RAMReady,
/* Refresh Counter Interface */ /* Refresh Counter Interface */
RefReq, RefUrg, RefReq, RefUrg,
/* DRAM and NOR flash interface */ /* DRAM and NOR flash interface */