Macintosh-HW/Warp-SE
1
0
Fork 0
mirror of https://github.com/garrettsworkshop/Warp-SE.git synced 2024-12-26 08:32:11 +00:00
Code Issues Projects Releases Wiki Activity

Revert "Revert "Share IOPWReady with ALE1 in IOBS""

Browse Source 
This reverts commit 388e381dff.
This commit is contained in:
Zane Kaminski 2023-04-09 23:26:05 -04:00
parent 388e381dff
commit cf1b0ec03b
1 changed files with 6 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
cpld/IOBS.v
View File

@ -6,7 +6,7 @@ module IOBS(
/* Select signals */ /* Select signals */
input IOCS, input IOPWCS, input ROMCS, input IOCS, input IOPWCS, input ROMCS,
/* FSB cycle termination outputs */ /* FSB cycle termination outputs */
output reg IONPReady, output reg IOPWReady, output reg nBERR_FSB, output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
/* Read data OE control */ /* Read data OE control */
output nDinOE, output nDinOE,
/* IOB master controller interface */ /* IOB master controller interface */
@ -42,11 +42,8 @@ module IOBS(
reg Sent = 0; reg Sent = 0;
/* FIFO secondary level control */ /* FIFO secondary level control */
reg Load1; reg Load1; reg Clear1;
reg Clear1; reg IORW1; reg IOL1; reg IOU1;
reg IORW1;
reg IOL1;
reg IOU1;
always @(posedge CLK) begin // ALE and R/W load control always @(posedge CLK) begin // ALE and R/W load control
// If write currently posting (TS!=0), // If write currently posting (TS!=0),
// I/O selected, and FIFO secondary level empty // I/O selected, and FIFO secondary level empty
@ -128,19 +125,13 @@ module IOBS(
else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1; else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
end end
/* Nonposted ready */ /* Nonposted and posted ready */
always @(posedge CLK) begin assign IOPWReady = !ALE1; // Posted write reaedy
always @(posedge CLK) begin // Nonposted read/write ready
if (!BACT) IONPReady <= 0; if (!BACT) IONPReady <= 0;
else if (Sent && !IOPWCS && IODONE) IONPReady <= 1; else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
end end
/* Posted ready */
always @(posedge CLK) begin
if (Clear1) IOPWReady <= 1;
else if (Load1) IOPWReady <= 0;
else IOPWReady <= !ALE1;
end
/* BERR control */ /* BERR control */
always @(posedge CLK) begin always @(posedge CLK) begin
if (!BACT) nBERR_FSB <= 1; if (!BACT) nBERR_FSB <= 1;