Compiled
This commit is contained in:
Zane Kaminski
parent
5d8cb62df3
commit
f26657823e
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@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of warnings: 0
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Total memory usage is 155620 kilobytes
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Total memory usage is 155300 kilobytes
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Writing NGD file "WarpSE.ngd" ...
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Total REAL time to NGDBUILD completion: 3 sec
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@ -907,3 +907,14 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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@ -49,6 +49,7 @@ nVPA_FSB: MAXTRANS(0.0);
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nRAS: MAXTRANS(0.0);
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nBR_IOB: MAXTRANS(0.0);
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RA<3>: MAXTRANS(0.0);
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nDTACK_FSB: MAXTRANS(0.0);
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RA<0>: MAXTRANS(0.0);
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RA<10>: MAXTRANS(0.0);
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RA<1>: MAXTRANS(0.0);
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@ -59,12 +60,11 @@ RA<6>: MAXTRANS(0.0);
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RA<7>: MAXTRANS(0.0);
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RA<8>: MAXTRANS(0.0);
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RA<9>: MAXTRANS(0.0);
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nOE: MAXTRANS(0.0);
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nROMWE: MAXTRANS(0.0);
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nADoutLE0: MAXTRANS(0.0);
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nCAS: MAXTRANS(0.0);
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nDTACK_FSB: MAXTRANS(0.0);
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nDinLE: MAXTRANS(0.0);
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nOE: MAXTRANS(0.0);
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RA<11>: MAXTRANS(0.0);
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nADoutLE1: MAXTRANS(0.0);
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nAoutOE: MAXTRANS(0.0);
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@ -79,16 +79,6 @@ ENDPORTDATA
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/* timing arc data */
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TIMINGDATA
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ARCDATA
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A_FSB<1>_RA<0>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<9>_RA<0>_delay:
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CELL_RISE(scalar) {
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@ -100,7 +90,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<7>_RA<10>_delay:
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A_FSB<1>_RA<0>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -119,6 +109,16 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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A_FSB<7>_RA<10>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<20>_RA<11>_delay:
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CELL_RISE(scalar) {
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@ -160,7 +160,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<7>_RA<2>_delay:
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A_FSB<16>_RA<2>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -170,7 +170,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<16>_RA<2>_delay:
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A_FSB<7>_RA<2>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -199,6 +199,16 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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A_FSB<3>_RA<4>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<11>_RA<4>_delay:
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CELL_RISE(scalar) {
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@ -210,7 +220,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<3>_RA<4>_delay:
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A_FSB<4>_RA<5>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -222,20 +232,10 @@ ENDARCDATA
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ARCDATA
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A_FSB<12>_RA<5>_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<4>_RA<5>_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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@ -259,16 +259,6 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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A_FSB<14>_RA<7>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<6>_RA<7>_delay:
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CELL_RISE(scalar) {
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@ -280,7 +270,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<18>_RA<8>_delay:
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A_FSB<14>_RA<7>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -300,7 +290,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<15>_RA<9>_delay:
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A_FSB<18>_RA<8>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -319,6 +309,16 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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A_FSB<15>_RA<9>_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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nAS_FSB_nDinOE_delay:
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CELL_RISE(scalar) {
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@ -330,7 +330,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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nWE_FSB_nDinOE_delay:
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A_FSB<23>_nDinOE_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -349,6 +349,16 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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nWE_FSB_nDinOE_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<21>_nDinOE_delay:
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CELL_RISE(scalar) {
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@ -370,27 +380,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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A_FSB<23>_nDinOE_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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nAS_FSB_nOE_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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nWE_FSB_nOE_delay:
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nWE_FSB_nRAMLWE_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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}
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@ -410,12 +400,12 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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nWE_FSB_nRAMLWE_delay:
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nWE_FSB_nRAMUWE_delay:
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CELL_RISE(scalar) {
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VALUES("10");
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VALUES("11");
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}
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CELL_FALL(scalar) {
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VALUES("10");
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VALUES("11");
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}
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ENDARCDATA
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@ -430,7 +420,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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nWE_FSB_nRAMUWE_delay:
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nAS_FSB_nRAS_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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}
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@ -449,16 +439,6 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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nAS_FSB_nRAS_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<23>_nRAS_delay:
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CELL_RISE(scalar) {
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@ -472,60 +452,60 @@ ENDARCDATA
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ARCDATA
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A_FSB<22>_nROMCS_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<20>_nROMCS_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<23>_nROMCS_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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A_FSB<21>_nROMCS_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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nWE_FSB_nROMWE_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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ARCDATA
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nAS_FSB_nROMWE_delay:
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CELL_RISE(scalar) {
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VALUES("11");
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VALUES("10");
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}
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CELL_FALL(scalar) {
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VALUES("11");
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VALUES("10");
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}
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ENDARCDATA
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@ -629,6 +609,16 @@ CELL_FALL(scalar) {
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}
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ENDARCDATA
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ARCDATA
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FCLK_nDTACK_FSB_delay:
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CELL_RISE(scalar) {
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VALUES("5.8");
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}
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CELL_FALL(scalar) {
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VALUES("5.8");
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}
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ENDARCDATA
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ARCDATA
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FCLK_RA<0>_delay:
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CELL_RISE(scalar) {
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@ -682,10 +672,10 @@ ENDARCDATA
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ARCDATA
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FCLK_RA<5>_delay:
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CELL_RISE(scalar) {
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VALUES("14.5");
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VALUES("13.5");
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}
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CELL_FALL(scalar) {
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VALUES("14.5");
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VALUES("13.5");
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}
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ENDARCDATA
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@ -750,7 +740,7 @@ CELL_FALL(scalar) {
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ENDARCDATA
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ARCDATA
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FCLK_nDTACK_FSB_delay:
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FCLK_nOE_delay:
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CELL_RISE(scalar) {
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VALUES("5.8");
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}
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|
@ -822,10 +812,10 @@ ENDARCDATA
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|||
ARCDATA
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||||
FCLK_nROMCS_delay:
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||||
CELL_RISE(scalar) {
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VALUES("14.5");
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||||
VALUES("13.5");
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||||
}
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||||
CELL_FALL(scalar) {
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||||
VALUES("14.5");
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||||
VALUES("13.5");
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}
|
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ENDARCDATA
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||||
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@ -902,112 +892,112 @@ ENDARCDATA
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|||
ARCDATA
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||||
A_FSB<10>_FCLK_setup:
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||||
CONSTRAINT(scalar) {
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||||
VALUES("20");
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||||
VALUES("19.6");
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||||
}
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ENDARCDATA
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ARCDATA
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||||
A_FSB<11>_FCLK_setup:
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||||
CONSTRAINT(scalar) {
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||||
VALUES("20");
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||||
VALUES("19.6");
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||||
}
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||||
ENDARCDATA
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||||
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||||
ARCDATA
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||||
A_FSB<12>_FCLK_setup:
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||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
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||||
VALUES("19.6");
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||||
}
|
||||
ENDARCDATA
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||||
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||||
ARCDATA
|
||||
A_FSB<13>_FCLK_setup:
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||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
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||||
VALUES("19.6");
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||||
}
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||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<14>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<15>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<16>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<17>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<18>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<19>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<20>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<21>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<22>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<23>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<8>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<9>_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
|
|
@ -1056,119 +1046,119 @@ ENDARCDATA
|
|||
ARCDATA
|
||||
nWE_FSB_FCLK_setup:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("20");
|
||||
VALUES("19.6");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<10>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<11>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<12>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<13>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<14>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<15>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<16>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<17>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<18>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<19>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<20>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<21>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<22>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<23>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<8>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
ARCDATA
|
||||
A_FSB<9>_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
|
|
@ -1217,7 +1207,7 @@ ENDARCDATA
|
|||
ARCDATA
|
||||
nWE_FSB_FCLK_hold:
|
||||
CONSTRAINT(scalar) {
|
||||
VALUES("-13.5");
|
||||
VALUES("-13.1");
|
||||
}
|
||||
ENDARCDATA
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1681113893" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681113885">
|
||||
<transform xil_pn:end_ts="1681550500" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681550485">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -87,7 +87,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1681113899" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681113893">
|
||||
<transform xil_pn:end_ts="1681550506" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681550500">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpSE.bld"/>
|
||||
|
|
@ -96,12 +96,10 @@
|
|||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1681113915" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681113899">
|
||||
<transform xil_pn:end_ts="1681550522" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681550506">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="WarpSE.gyd"/>
|
||||
<outfile xil_pn:name="WarpSE.mfd"/>
|
||||
<outfile xil_pn:name="WarpSE.nga"/>
|
||||
|
|
@ -116,14 +114,16 @@
|
|||
<outfile xil_pn:name="WarpSE_html"/>
|
||||
<outfile xil_pn:name="WarpSE_pad.csv"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1681113917" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681113915">
|
||||
<transform xil_pn:end_ts="1681550524" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681550522">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="WarpSE.jed"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1681114088" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681114086">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<transform xil_pn:end_ts="1681173277" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681173275">
|
||||
<status xil_pn:value="AbortedRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
|
|
|
|||
|
|
@ -76,44 +76,43 @@ nVPA_FSB S:PIN93
|
|||
;The remaining section of the .gyd file is for documentation purposes only.
|
||||
;It shows where your internal equations were placed in the last successful fit.
|
||||
|
||||
PARTITION FB1_1 ram/BACTr nRESout iobs/Clear1 iobm/Er
|
||||
fsb/ASrf cnt/nIPL2r cnt/Er<1> cnt/Er<0>
|
||||
ALE0S $OpTx$$OpTx$FX_DC$348_INV$535 iobs/TS_FSM_FFd1 iobs/IOU1
|
||||
iobs/IOL1 cnt/Timer<0> RefUrg IOBERR
|
||||
iobm/ES<2> cnt/Timer<1>
|
||||
PARTITION FB2_3 ram/RS_FSM_FFd6 ram/RS_FSM_FFd4 ram/RS_FSM_FFd3 ram/RS_FSM_FFd2
|
||||
ram/RS_FSM_FFd1 ram/RASrf iobs/IODONEr iobs/IOACTr
|
||||
PARTITION FB1_1 ram/RS_FSM_FFd3 ram/RS_FSM_FFd2 ram/RS_FSM_FFd1 cnt/Er<1>
|
||||
cnt/Er<0> ram/RefDone iobs/IOU1 iobs/IOL1
|
||||
cnt/TimerTC cnt/Timer<0> cnt/IS_FSM_FFd2 RefUrg
|
||||
RefReq iobm/ES<2> cnt/Timer<1> cnt/Timer<3>
|
||||
cnt/Timer<2> ram/RS_FSM_FFd7
|
||||
PARTITION FB2_4 ram/RASrf ram/DTACKr iobs/IODONEr iobs/IOACTr
|
||||
iobm/VPAr iobm/IOWRREQr iobm/IOS_FSM_FFd5 iobm/IOS_FSM_FFd4
|
||||
iobm/IOS_FSM_FFd1 iobm/IORDREQr iobm/C8Mr iobm/IOS_FSM_FFd2
|
||||
|
||||
PARTITION FB3_1 EXP10_ cnt/WS<0> ram/RefDone ram/RS_FSM_FFd7
|
||||
ram/RS_FSM_FFd5 cnt/WS<2> cnt/WS<1> EXP11_
|
||||
nDTACK_FSB_OBUF ram/RS_FSM_FFd8 EXP12_ ram/RASEN
|
||||
EXP13_ ram/CAS ram/RS_FSM_FFd9 EXP14_
|
||||
nROMWE_OBUF RAMReady
|
||||
PARTITION FB4_1 EXP15_ nAoutOE_OBUF cnt/LTimer<9> cnt/LTimer<8>
|
||||
nDoutOE_OBUF nDinOE_OBUF cnt/LTimer<7> N0
|
||||
cnt/LTimer<11> cnt/LTimer<10> nVPA_FSB_OBUF IONPReady
|
||||
EXP16_ cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2 EXP17_ cnt/LTimer<1>
|
||||
EXP18_ cnt/LTimer<0>
|
||||
PARTITION FB5_1 QoSReady nROMCS_OBUF ram/RASEL cs/nOverlay
|
||||
nCAS_OBUF nOE_OBUF cnt/WS<3> ram/RASrr
|
||||
RA_4_OBUF iobs/Load1 RA_11_OBUF RA_5_OBUF
|
||||
iobs/Sent RA_2_OBUF RA_6_OBUF EXP19_
|
||||
IORDREQ EXP20_
|
||||
iobm/IOS_FSM_FFd1 iobm/IORDREQr iobm/Er iobm/C8Mr
|
||||
cnt/nIPL2r iobm/IOS_FSM_FFd2 IOBERR
|
||||
PARTITION FB3_1 EXP10_ QoSReady cnt/WS<2> ram/RS_FSM_FFd6
|
||||
ram/RS_FSM_FFd5 iobs/TS_FSM_FFd1 ram/RASEL cs/nOverlay
|
||||
nDTACK_FSB_OBUF cnt/WS<3> cnt/WS<1> iobs/Load1
|
||||
iobs/Clear1 EXP11_ IORDREQ iobs/Sent
|
||||
nROMWE_OBUF ram/RS_FSM_FFd4
|
||||
PARTITION FB4_1 EXP12_ nAoutOE_OBUF EXP13_
|
||||
PARTITION FB4_5 nDoutOE_OBUF nDinOE_OBUF ram/BACTr N0
|
||||
nRESout fsb/ASrf nVPA_FSB_OBUF cnt/LTimerTC
|
||||
ALE0S $OpTx$$OpTx$FX_DC$350_INV$537 EXP14_ cnt/LTimer<1>
|
||||
EXP15_ cnt/LTimer<0>
|
||||
PARTITION FB5_1 ram/RS_FSM_FFd8 nROMCS_OBUF EXP16_ EXP17_
|
||||
nCAS_OBUF nOE_OBUF EXP18_ cnt/WS<0>
|
||||
RA_4_OBUF ram/RASEN RA_11_OBUF RA_5_OBUF
|
||||
RAMReady RA_2_OBUF RA_6_OBUF IONPReady
|
||||
EXP19_ ram/RASrr
|
||||
PARTITION FB6_1 iobm/IOS_FSM_FFd6 nVMA_IOBout iobm/IOS_FSM_FFd7 iobm/IOS_FSM_FFd3
|
||||
iobm/ES<0> iobm/ES<3> iobm/ES<1> iobm/DoutOE
|
||||
nLDS_IOBout IODONE nUDS_IOBout nAS_IOBout
|
||||
iobm/IOS0 nADoutLE1_OBUF nADoutLE0_OBUF ALE0M
|
||||
nDinLE_OBUF IOACT
|
||||
PARTITION FB7_1 cnt/LTimerTC RA_1_OBUF cnt/TimerTC cnt/IS_FSM_FFd2
|
||||
RA_7_OBUF RA_0_OBUF RefReq RA_8_OBUF
|
||||
RA_10_OBUF cnt/LTimer<6> RA_9_OBUF C25MEN_OBUF
|
||||
cnt/LTimer<5> cnt/LTimer<4> cnt/LTimer<3> cnt/LTimer<2>
|
||||
cnt/Timer<3> cnt/Timer<2>
|
||||
PARTITION FB8_1 IOL0 RA_11_OBUF$BUF0 iobs/TS_FSM_FFd2 EXP21_
|
||||
nRAS_OBUF nRAMLWE_OBUF EXP22_ nRAMUWE_OBUF
|
||||
IOWRREQ EXP23_ EXP24_ nBERR_FSB_OBUF
|
||||
EXP25_ IOU0 nBR_IOB_OBUF cnt/IS_FSM_FFd1
|
||||
iobs/IORW1 EXP26_
|
||||
PARTITION FB7_1 cnt/LTimer<9> RA_1_OBUF cnt/LTimer<8> cnt/LTimer<7>
|
||||
RA_7_OBUF RA_0_OBUF cnt/LTimer<6> RA_8_OBUF
|
||||
RA_10_OBUF cnt/LTimer<5> RA_9_OBUF C25MEN_OBUF
|
||||
cnt/LTimer<4> cnt/LTimer<3> cnt/LTimer<2> cnt/LTimer<11>
|
||||
cnt/LTimer<10> cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
|
||||
PARTITION FB8_1 IOL0 RA_11_OBUF$BUF0 iobs/TS_FSM_FFd2 EXP20_
|
||||
nRAS_OBUF nRAMLWE_OBUF EXP21_ nRAMUWE_OBUF
|
||||
IOWRREQ EXP22_ EXP23_ nBERR_FSB_OBUF
|
||||
EXP24_ IOU0 nBR_IOB_OBUF cnt/IS_FSM_FFd1
|
||||
iobs/IORW1 EXP25_
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -48,6 +48,7 @@ OUTPUT S:PIN93 = nVPA_FSB;
|
|||
OUTPUT S:PIN64 = nRAS;
|
||||
OUTPUT S:PIN72 = nBR_IOB;
|
||||
OUTPUT S:PIN41 = RA<3>;
|
||||
OUTPUT S:PIN28 = nDTACK_FSB;
|
||||
OUTPUT S:PIN53 = RA<0>;
|
||||
OUTPUT S:PIN55 = RA<10>;
|
||||
OUTPUT S:PIN50 = RA<1>;
|
||||
|
|
@ -58,12 +59,11 @@ OUTPUT S:PIN46 = RA<6>;
|
|||
OUTPUT S:PIN52 = RA<7>;
|
||||
OUTPUT S:PIN54 = RA<8>;
|
||||
OUTPUT S:PIN56 = RA<9>;
|
||||
OUTPUT S:PIN37 = nOE;
|
||||
OUTPUT S:PIN34 = nROMWE;
|
||||
OUTPUT S:PIN85 = nADoutLE0;
|
||||
OUTPUT S:PIN36 = nCAS;
|
||||
OUTPUT S:PIN28 = nDTACK_FSB;
|
||||
OUTPUT S:PIN86 = nDinLE;
|
||||
OUTPUT S:PIN37 = nOE;
|
||||
OUTPUT S:PIN63 = RA<11>;
|
||||
OUTPUT S:PIN82 = nADoutLE1;
|
||||
OUTPUT S:PIN87 = nAoutOE;
|
||||
|
|
@ -75,44 +75,42 @@ OUTPUT S:PIN35 = nROMCS;
|
|||
OUTPUT S:PIN58 = C25MEN;
|
||||
|
||||
/* timing arc definitions */
|
||||
A_FSB<1>_RA<0>_delay: DELAY A_FSB<1> RA<0>;
|
||||
A_FSB<9>_RA<0>_delay: DELAY A_FSB<9> RA<0>;
|
||||
A_FSB<7>_RA<10>_delay: DELAY A_FSB<7> RA<10>;
|
||||
A_FSB<1>_RA<0>_delay: DELAY A_FSB<1> RA<0>;
|
||||
A_FSB<17>_RA<10>_delay: DELAY A_FSB<17> RA<10>;
|
||||
A_FSB<7>_RA<10>_delay: DELAY A_FSB<7> RA<10>;
|
||||
A_FSB<20>_RA<11>_delay: DELAY A_FSB<20> RA<11>;
|
||||
A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
|
||||
A_FSB<2>_RA<1>_delay: DELAY A_FSB<2> RA<1>;
|
||||
A_FSB<10>_RA<1>_delay: DELAY A_FSB<10> RA<1>;
|
||||
A_FSB<7>_RA<2>_delay: DELAY A_FSB<7> RA<2>;
|
||||
A_FSB<16>_RA<2>_delay: DELAY A_FSB<16> RA<2>;
|
||||
A_FSB<7>_RA<2>_delay: DELAY A_FSB<7> RA<2>;
|
||||
A_FSB<20>_RA<3>_delay: DELAY A_FSB<20> RA<3>;
|
||||
A_FSB<19>_RA<3>_delay: DELAY A_FSB<19> RA<3>;
|
||||
A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
|
||||
A_FSB<3>_RA<4>_delay: DELAY A_FSB<3> RA<4>;
|
||||
A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
|
||||
A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
|
||||
A_FSB<4>_RA<5>_delay: DELAY A_FSB<4> RA<5>;
|
||||
A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
|
||||
A_FSB<5>_RA<6>_delay: DELAY A_FSB<5> RA<6>;
|
||||
A_FSB<13>_RA<6>_delay: DELAY A_FSB<13> RA<6>;
|
||||
A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
|
||||
A_FSB<6>_RA<7>_delay: DELAY A_FSB<6> RA<7>;
|
||||
A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
|
||||
A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
|
||||
A_FSB<21>_RA<8>_delay: DELAY A_FSB<21> RA<8>;
|
||||
A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
|
||||
A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
|
||||
A_FSB<8>_RA<9>_delay: DELAY A_FSB<8> RA<9>;
|
||||
A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
|
||||
nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
|
||||
nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
|
||||
A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
|
||||
A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
|
||||
nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
|
||||
A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
|
||||
A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
|
||||
A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
|
||||
nAS_FSB_nOE_delay: DELAY nAS_FSB nOE;
|
||||
nWE_FSB_nOE_delay: DELAY nWE_FSB nOE;
|
||||
nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
|
||||
nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
|
||||
nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
|
||||
nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
|
||||
nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
|
||||
A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
|
||||
nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
|
||||
nAS_FSB_nRAS_delay: DELAY nAS_FSB nRAS;
|
||||
A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
|
||||
A_FSB<23>_nRAS_delay: DELAY A_FSB<23> nRAS;
|
||||
A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
|
||||
A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
|
||||
|
|
@ -130,6 +128,7 @@ FCLK_nVPA_FSB_delay: DELAY FCLK nVPA_FSB;
|
|||
FCLK_nRAS_delay: DELAY FCLK nRAS;
|
||||
FCLK_nBR_IOB_delay: DELAY FCLK nBR_IOB;
|
||||
FCLK_RA<3>_delay: DELAY FCLK RA<3>;
|
||||
FCLK_nDTACK_FSB_delay: DELAY FCLK nDTACK_FSB;
|
||||
FCLK_RA<0>_delay: DELAY FCLK RA<0>;
|
||||
FCLK_RA<10>_delay: DELAY FCLK RA<10>;
|
||||
FCLK_RA<1>_delay: DELAY FCLK RA<1>;
|
||||
|
|
@ -142,7 +141,7 @@ FCLK_RA<8>_delay: DELAY FCLK RA<8>;
|
|||
FCLK_RA<9>_delay: DELAY FCLK RA<9>;
|
||||
FCLK_nADoutLE0_delay: DELAY FCLK nADoutLE0;
|
||||
FCLK_nCAS_delay: DELAY FCLK nCAS;
|
||||
FCLK_nDTACK_FSB_delay: DELAY FCLK nDTACK_FSB;
|
||||
FCLK_nOE_delay: DELAY FCLK nOE;
|
||||
FCLK_RA<11>_delay: DELAY FCLK RA<11>;
|
||||
FCLK_nADoutLE1_delay: DELAY FCLK nADoutLE1;
|
||||
FCLK_nAoutOE_delay: DELAY FCLK nAoutOE;
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -1,7 +1,7 @@
|
|||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
4-10-2023 4:05AM
|
||||
4-15-2023 5:21AM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||
|
|
|
|||
|
|
@ -15,4 +15,4 @@
|
|||
sr (SLOW|FAST|slow|fast) "SLOW"
|
||||
dir (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
|
||||
]>
|
||||
<ibis><part arch="xc9500xl" device="XC95144XL" pkg="TQ100" spg="-10"/><pin dir="input" nm="A_FSB<23>" no="24"/><pin dir="input" nm="A_FSB<22>" no="20"/><pin dir="input" nm="A_FSB<21>" no="19"/><pin dir="input" nm="A_FSB<20>" no="18"/><pin dir="input" nm="A_FSB<19>" no="17"/><pin dir="input" nm="A_FSB<18>" no="16"/><pin dir="input" nm="A_FSB<17>" no="15"/><pin dir="input" nm="A_FSB<16>" no="14"/><pin dir="input" nm="A_FSB<15>" no="13"/><pin dir="input" nm="A_FSB<13>" no="11"/><pin dir="input" nm="A_FSB<12>" no="10"/><pin dir="input" nm="C8M" no="23"/><pin dir="input" nm="C16M" no="22"/><pin dir="input" nm="A_FSB<14>" no="12"/><pin dir="input" nm="A_FSB<11>" no="9"/><pin dir="input" nm="A_FSB<10>" no="8"/><pin dir="input" nm="FCLK" no="27"/><pin dir="input" nm="nWE_FSB" no="29"/><pin dir="input" nm="nAS_FSB" no="32"/><pin dir="input" nm="A_FSB<8>" no="6"/><pin dir="input" nm="A_FSB<9>" no="7"/><pin dir="input" nm="nBERR_IOB" no="76"/><pin dir="input" nm="nDTACK_IOB" no="78"/><pin dir="input" nm="nLDS_FSB" no="30"/><pin dir="input" nm="nUDS_FSB" no="33"/><pin dir="input" nm="E" no="25"/><pin dir="input" nm="nIPL2" no="92"/><pin dir="input" nm="nVPA_IOB" no="77"/><pin dir="input" nm="A_FSB<1>" no="94"/><pin dir="input" nm="A_FSB<7>" no="4"/><pin dir="input" nm="A_FSB<2>" no="95"/><pin dir="input" nm="A_FSB<3>" no="96"/><pin dir="input" nm="A_FSB<4>" no="97"/><pin dir="input" nm="A_FSB<5>" no="2"/><pin dir="input" nm="A_FSB<6>" no="3"/><pin dir="output" nm="nVMA_IOB" no="74" sr="fast"/><pin dir="output" nm="nAS_IOB" no="81" sr="fast"/><pin dir="output" nm="nLDS_IOB" no="79" sr="fast"/><pin dir="output" nm="nUDS_IOB" no="80" sr="fast"/><pin dir="output" nm="nBERR_FSB" no="70" sr="fast"/><pin dir="output" nm="nVPA_FSB" no="93" sr="fast"/><pin dir="output" nm="nRAS" no="64" sr="fast"/><pin dir="output" nm="nBR_IOB" no="72" sr="fast"/><pin dir="output" nm="RA<3>" no="41" sr="fast"/><pin dir="output" nm="RA<0>" no="53" sr="fast"/><pin dir="output" nm="RA<10>" no="55" sr="fast"/><pin dir="output" nm="RA<1>" no="50" sr="fast"/><pin dir="output" nm="RA<2>" no="43" sr="fast"/><pin dir="output" nm="RA<4>" no="40" sr="fast"/><pin dir="output" nm="RA<5>" no="42" sr="fast"/><pin dir="output" nm="RA<6>" no="46" sr="fast"/><pin dir="output" nm="RA<7>" no="52" sr="fast"/><pin dir="output" nm="RA<8>" no="54" sr="fast"/><pin dir="output" nm="RA<9>" no="56" sr="fast"/><pin dir="output" nm="nOE" no="37" sr="fast"/><pin dir="output" nm="nROMWE" no="34" sr="fast"/><pin dir="output" nm="nADoutLE0" no="85" sr="fast"/><pin dir="output" nm="nCAS" no="36" sr="fast"/><pin dir="output" nm="nDTACK_FSB" no="28" sr="fast"/><pin dir="output" nm="nDinLE" no="86" sr="fast"/><pin dir="output" nm="RA<11>" no="63" sr="fast"/><pin dir="output" nm="nADoutLE1" no="82" sr="fast"/><pin dir="output" nm="nAoutOE" no="87" sr="fast"/><pin dir="output" nm="nDinOE" no="90" sr="fast"/><pin dir="output" nm="nDoutOE" no="89" sr="fast"/><pin dir="output" nm="nRAMLWE" no="65" sr="fast"/><pin dir="output" nm="nRAMUWE" no="66" sr="fast"/><pin dir="output" nm="nROMCS" no="35" sr="fast"/><pin dir="output" nm="C25MEN" no="58" sr="fast"/><pin dir="bidir" nm="nRES" no="91" sr="fast"/></ibis>
|
||||
<ibis><part arch="xc9500xl" device="XC95144XL" pkg="TQ100" spg="-10"/><pin dir="input" nm="A_FSB<23>" no="24"/><pin dir="input" nm="A_FSB<22>" no="20"/><pin dir="input" nm="A_FSB<21>" no="19"/><pin dir="input" nm="A_FSB<20>" no="18"/><pin dir="input" nm="A_FSB<19>" no="17"/><pin dir="input" nm="A_FSB<18>" no="16"/><pin dir="input" nm="A_FSB<17>" no="15"/><pin dir="input" nm="A_FSB<16>" no="14"/><pin dir="input" nm="A_FSB<15>" no="13"/><pin dir="input" nm="A_FSB<13>" no="11"/><pin dir="input" nm="A_FSB<12>" no="10"/><pin dir="input" nm="C8M" no="23"/><pin dir="input" nm="C16M" no="22"/><pin dir="input" nm="A_FSB<14>" no="12"/><pin dir="input" nm="A_FSB<11>" no="9"/><pin dir="input" nm="A_FSB<10>" no="8"/><pin dir="input" nm="FCLK" no="27"/><pin dir="input" nm="nWE_FSB" no="29"/><pin dir="input" nm="nAS_FSB" no="32"/><pin dir="input" nm="A_FSB<8>" no="6"/><pin dir="input" nm="A_FSB<9>" no="7"/><pin dir="input" nm="nBERR_IOB" no="76"/><pin dir="input" nm="nDTACK_IOB" no="78"/><pin dir="input" nm="nLDS_FSB" no="30"/><pin dir="input" nm="nUDS_FSB" no="33"/><pin dir="input" nm="E" no="25"/><pin dir="input" nm="nIPL2" no="92"/><pin dir="input" nm="nVPA_IOB" no="77"/><pin dir="input" nm="A_FSB<1>" no="94"/><pin dir="input" nm="A_FSB<7>" no="4"/><pin dir="input" nm="A_FSB<2>" no="95"/><pin dir="input" nm="A_FSB<3>" no="96"/><pin dir="input" nm="A_FSB<4>" no="97"/><pin dir="input" nm="A_FSB<5>" no="2"/><pin dir="input" nm="A_FSB<6>" no="3"/><pin dir="output" nm="nVMA_IOB" no="74" sr="fast"/><pin dir="output" nm="nAS_IOB" no="81" sr="fast"/><pin dir="output" nm="nLDS_IOB" no="79" sr="fast"/><pin dir="output" nm="nUDS_IOB" no="80" sr="fast"/><pin dir="output" nm="nBERR_FSB" no="70" sr="fast"/><pin dir="output" nm="nVPA_FSB" no="93" sr="fast"/><pin dir="output" nm="nRAS" no="64" sr="fast"/><pin dir="output" nm="nBR_IOB" no="72" sr="fast"/><pin dir="output" nm="RA<3>" no="41" sr="fast"/><pin dir="output" nm="nDTACK_FSB" no="28" sr="fast"/><pin dir="output" nm="RA<0>" no="53" sr="fast"/><pin dir="output" nm="RA<10>" no="55" sr="fast"/><pin dir="output" nm="RA<1>" no="50" sr="fast"/><pin dir="output" nm="RA<2>" no="43" sr="fast"/><pin dir="output" nm="RA<4>" no="40" sr="fast"/><pin dir="output" nm="RA<5>" no="42" sr="fast"/><pin dir="output" nm="RA<6>" no="46" sr="fast"/><pin dir="output" nm="RA<7>" no="52" sr="fast"/><pin dir="output" nm="RA<8>" no="54" sr="fast"/><pin dir="output" nm="RA<9>" no="56" sr="fast"/><pin dir="output" nm="nROMWE" no="34" sr="fast"/><pin dir="output" nm="nADoutLE0" no="85" sr="fast"/><pin dir="output" nm="nCAS" no="36" sr="fast"/><pin dir="output" nm="nDinLE" no="86" sr="fast"/><pin dir="output" nm="nOE" no="37" sr="fast"/><pin dir="output" nm="RA<11>" no="63" sr="fast"/><pin dir="output" nm="nADoutLE1" no="82" sr="fast"/><pin dir="output" nm="nAoutOE" no="87" sr="fast"/><pin dir="output" nm="nDinOE" no="90" sr="fast"/><pin dir="output" nm="nDoutOE" no="89" sr="fast"/><pin dir="output" nm="nRAMLWE" no="65" sr="fast"/><pin dir="output" nm="nRAMUWE" no="66" sr="fast"/><pin dir="output" nm="nROMCS" no="35" sr="fast"/><pin dir="output" nm="C25MEN" no="58" sr="fast"/><pin dir="bidir" nm="nRES" no="91" sr="fast"/></ibis>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -3,14 +3,14 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.10 secs
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total CPU time to Xst completion: 0.31 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.10 secs
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total CPU time to Xst completion: 0.33 secs
|
||||
|
||||
--> Reading design: WarpSE.prj
|
||||
|
||||
|
|
@ -152,19 +152,20 @@ Synthesizing Unit <RAM>.
|
|||
Related source file is "../RAM.v".
|
||||
Found finite state machine <FSM_0> for signal <RS>.
|
||||
-----------------------------------------------------------------------
|
||||
| States | 9 |
|
||||
| Transitions | 21 |
|
||||
| Inputs | 7 |
|
||||
| Outputs | 9 |
|
||||
| States | 8 |
|
||||
| Transitions | 14 |
|
||||
| Inputs | 6 |
|
||||
| Outputs | 8 |
|
||||
| Clock | CLK (rising_edge) |
|
||||
| Power Up State | 0000 |
|
||||
| Power Up State | 000 |
|
||||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <nCAS>.
|
||||
Found 1-bit register for signal <nOE>.
|
||||
Found 1-bit register for signal <RAMReady>.
|
||||
Found 1-bit register for signal <BACTr>.
|
||||
Found 1-bit register for signal <CAS>.
|
||||
Found 1-bit register for signal <DTACKr>.
|
||||
Found 1-bit register for signal <RASEL>.
|
||||
Found 1-bit register for signal <RASEN>.
|
||||
Found 1-bit register for signal <RASrf>.
|
||||
|
|
@ -172,7 +173,7 @@ Synthesizing Unit <RAM>.
|
|||
Found 1-bit register for signal <RefDone>.
|
||||
Summary:
|
||||
inferred 1 Finite State Machine(s).
|
||||
inferred 8 D-type flip-flop(s).
|
||||
inferred 9 D-type flip-flop(s).
|
||||
Unit <RAM> synthesized.
|
||||
|
||||
|
||||
|
|
@ -318,8 +319,8 @@ Macro Statistics
|
|||
2-bit adder : 1
|
||||
# Counters : 3
|
||||
4-bit up counter : 3
|
||||
# Registers : 67
|
||||
1-bit register : 66
|
||||
# Registers : 68
|
||||
1-bit register : 67
|
||||
2-bit register : 1
|
||||
# Tristates : 5
|
||||
1-bit tristate buffer : 5
|
||||
|
|
@ -364,20 +365,19 @@ Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
|
|||
01 | 10
|
||||
-------------------
|
||||
Analyzing FSM <FSM_0> for best encoding.
|
||||
Optimizing FSM <ram/RS/FSM> on signal <RS[1:9]> with one-hot encoding.
|
||||
--------------------
|
||||
Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
|
||||
-------------------
|
||||
State | Encoding
|
||||
--------------------
|
||||
0000 | 000000001
|
||||
1000 | 000000010
|
||||
0001 | 000000100
|
||||
0010 | 000001000
|
||||
0011 | 000010000
|
||||
1001 | 000100000
|
||||
1010 | 001000000
|
||||
1011 | 010000000
|
||||
1111 | 100000000
|
||||
--------------------
|
||||
-------------------
|
||||
000 | 00000001
|
||||
100 | 00000010
|
||||
001 | 00000100
|
||||
010 | 00001000
|
||||
011 | 00010000
|
||||
101 | 00100000
|
||||
110 | 01000000
|
||||
111 | 10000000
|
||||
-------------------
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
|
@ -389,8 +389,8 @@ Macro Statistics
|
|||
2-bit adder : 1
|
||||
# Counters : 3
|
||||
4-bit up counter : 3
|
||||
# Registers : 47
|
||||
Flip-Flops : 47
|
||||
# Registers : 48
|
||||
Flip-Flops : 48
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
|
@ -404,9 +404,8 @@ Optimizing unit <CS> ...
|
|||
implementation constraint: INIT=r : nOverlay
|
||||
|
||||
Optimizing unit <RAM> ...
|
||||
implementation constraint: INIT=s : RS_FSM_FFd9
|
||||
implementation constraint: INIT=s : RS_FSM_FFd8
|
||||
implementation constraint: INIT=r : RASEL
|
||||
implementation constraint: INIT=r : CAS
|
||||
implementation constraint: INIT=r : RASrr
|
||||
implementation constraint: INIT=r : RASEN
|
||||
implementation constraint: INIT=r : RS_FSM_FFd1
|
||||
|
|
@ -416,7 +415,6 @@ Optimizing unit <RAM> ...
|
|||
implementation constraint: INIT=r : RS_FSM_FFd5
|
||||
implementation constraint: INIT=r : RS_FSM_FFd6
|
||||
implementation constraint: INIT=r : RS_FSM_FFd7
|
||||
implementation constraint: INIT=r : RS_FSM_FFd8
|
||||
implementation constraint: INIT=r : RASrf
|
||||
|
||||
Optimizing unit <IOBS> ...
|
||||
|
|
@ -480,17 +478,17 @@ Design Statistics
|
|||
# IOs : 75
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 710
|
||||
# AND2 : 222
|
||||
# AND3 : 30
|
||||
# BELS : 672
|
||||
# AND2 : 211
|
||||
# AND3 : 29
|
||||
# AND4 : 12
|
||||
# AND5 : 2
|
||||
# AND7 : 2
|
||||
# AND8 : 5
|
||||
# AND8 : 4
|
||||
# GND : 6
|
||||
# INV : 277
|
||||
# OR2 : 119
|
||||
# OR3 : 10
|
||||
# INV : 262
|
||||
# OR2 : 105
|
||||
# OR3 : 14
|
||||
# OR4 : 4
|
||||
# VCC : 1
|
||||
# XOR2 : 20
|
||||
|
|
@ -507,12 +505,12 @@ Cell Usage :
|
|||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 5.00 secs
|
||||
Total CPU time to Xst completion: 5.14 secs
|
||||
Total REAL time to Xst completion: 6.00 secs
|
||||
Total CPU time to Xst completion: 5.44 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 267972 kilobytes
|
||||
Total memory usage is 266948 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 3 ( 0 filtered)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ Design: WarpSE
|
|||
Device: XC95144XL-10-TQ100
|
||||
Speed File: Version 3.0
|
||||
Program: Timing Report Generator: version P.20131013
|
||||
Date: Mon Apr 10 04:08:07 2023
|
||||
Date: Mon Apr 10 20:34:36 2023
|
||||
|
||||
Performance Summary:
|
||||
|
||||
|
|
@ -17,16 +17,16 @@ Clock net 'FCLK' path delays:
|
|||
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
|
||||
Clock Pad 'FCLK' to Output Pad 'nRES' (GCK)
|
||||
|
||||
Clock to Setup (tCYC) : 20.5ns (2 macrocell levels)
|
||||
Clock to Setup (tCYC) : 20.1ns (2 macrocell levels)
|
||||
Clock to Q, net 'cnt/IS_FSM_FFd1.Q' to DFF Setup(D) at 'cnt/LTimer<0>.D' (GCK)
|
||||
Target FF drives output net 'cnt/LTimer<0>'
|
||||
|
||||
Setup to Clock at the Pad (tSU) : 17.0ns (1 macrocell levels)
|
||||
Setup to Clock at the Pad (tSU) : 16.6ns (1 macrocell levels)
|
||||
Data signal 'A_FSB<23>' to DFF D input Pin at 'cnt/LTimer<0>.D'
|
||||
Clock pad 'FCLK' (GCK)
|
||||
|
||||
Minimum Clock Period: 20.5ns
|
||||
Maximum Internal Clock Speed: 48.7Mhz
|
||||
Minimum Clock Period: 20.1ns
|
||||
Maximum Internal Clock Speed: 49.7Mhz
|
||||
(Limited by Cycle Time)
|
||||
|
||||
Clock net 'C16M' path delays:
|
||||
|
|
@ -84,13 +84,12 @@ RA<1> 10.0
|
|||
RA<2> 10.0
|
||||
RA<3> 10.0
|
||||
RA<4> 10.0
|
||||
RA<5> 11.0
|
||||
RA<5> 10.0
|
||||
RA<6> 10.0
|
||||
RA<7> 10.0
|
||||
RA<8> 10.0
|
||||
RA<9> 10.0
|
||||
nDinOE
|
||||
nOE
|
||||
nRAMLWE
|
||||
nRAMUWE
|
||||
nRAS
|
||||
|
|
@ -118,17 +117,16 @@ RA<1> 10.0
|
|||
RA<2> 10.0
|
||||
RA<3> 10.0
|
||||
RA<4> 10.0
|
||||
RA<5> 11.0
|
||||
RA<5> 10.0
|
||||
RA<6> 10.0
|
||||
RA<7> 10.0
|
||||
RA<8> 10.0
|
||||
RA<9> 10.0
|
||||
nDinOE 10.0 10.0 10.0 10.0
|
||||
nOE
|
||||
nRAMLWE
|
||||
nRAMUWE
|
||||
nRAS 11.0 11.0
|
||||
nROMCS 11.0 11.0 11.0 11.0
|
||||
nROMCS 10.0 10.0 10.0 10.0
|
||||
nROMWE
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
|
@ -158,12 +156,11 @@ RA<7>
|
|||
RA<8>
|
||||
RA<9>
|
||||
nDinOE 10.0 10.0
|
||||
nOE 10.0 10.0
|
||||
nRAMLWE 10.0 10.0
|
||||
nRAMUWE 11.0 11.0
|
||||
nRAS 11.0
|
||||
nROMCS
|
||||
nROMWE 11.0 11.0
|
||||
nROMWE 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock Pad to Output Pad (tCO) (nsec)
|
||||
|
|
@ -187,7 +184,7 @@ RA<1> 13.5
|
|||
RA<2> 13.5
|
||||
RA<3> 13.5
|
||||
RA<4> 13.5
|
||||
RA<5> 14.5
|
||||
RA<5> 13.5
|
||||
RA<6> 13.5
|
||||
RA<7> 13.5
|
||||
RA<8> 13.5
|
||||
|
|
@ -203,11 +200,12 @@ nDTACK_FSB 5.8
|
|||
nDinLE 5.8
|
||||
nDoutOE 13.5 13.5
|
||||
nLDS_IOB 5.8 14.5
|
||||
nOE 5.8
|
||||
nRAMLWE 13.5
|
||||
nRAMUWE 14.5
|
||||
nRAS 14.5
|
||||
nRES 14.5
|
||||
nROMCS 14.5
|
||||
nROMCS 13.5
|
||||
nUDS_IOB 5.8 14.5
|
||||
nVMA_IOB 5.8 14.5
|
||||
nVPA_FSB 5.8
|
||||
|
|
@ -227,22 +225,22 @@ nVPA_FSB 5.8
|
|||
\
|
||||
To \------------------
|
||||
|
||||
A_FSB<10> 17.0
|
||||
A_FSB<11> 17.0
|
||||
A_FSB<12> 17.0
|
||||
A_FSB<13> 17.0
|
||||
A_FSB<14> 17.0
|
||||
A_FSB<15> 17.0
|
||||
A_FSB<16> 17.0
|
||||
A_FSB<17> 17.0
|
||||
A_FSB<18> 17.0
|
||||
A_FSB<19> 17.0
|
||||
A_FSB<20> 17.0
|
||||
A_FSB<21> 17.0
|
||||
A_FSB<22> 17.0
|
||||
A_FSB<23> 17.0
|
||||
A_FSB<8> 17.0
|
||||
A_FSB<9> 17.0
|
||||
A_FSB<10> 16.6
|
||||
A_FSB<11> 16.6
|
||||
A_FSB<12> 16.6
|
||||
A_FSB<13> 16.6
|
||||
A_FSB<14> 16.6
|
||||
A_FSB<15> 16.6
|
||||
A_FSB<16> 16.6
|
||||
A_FSB<17> 16.6
|
||||
A_FSB<18> 16.6
|
||||
A_FSB<19> 16.6
|
||||
A_FSB<20> 16.6
|
||||
A_FSB<21> 16.6
|
||||
A_FSB<22> 16.6
|
||||
A_FSB<23> 16.6
|
||||
A_FSB<8> 16.6
|
||||
A_FSB<9> 16.6
|
||||
C8M 6.5
|
||||
E 6.5 6.5
|
||||
nAS_FSB 16.6
|
||||
|
|
@ -253,7 +251,7 @@ nLDS_FSB 6.5
|
|||
nRES 6.5 6.5
|
||||
nUDS_FSB 6.5
|
||||
nVPA_IOB 6.5
|
||||
nWE_FSB 17.0
|
||||
nWE_FSB 16.6
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
|
|
@ -282,11 +280,11 @@ nWE_FSB 17.0
|
|||
ALE0S.D
|
||||
IOL0.D 11.0
|
||||
IONPReady.D 11.0
|
||||
IORDREQ.D 11.0
|
||||
IORDREQ.D 10.0
|
||||
IOU0.D 11.0
|
||||
IOWRREQ.D 10.0
|
||||
QoSReady.D 10.0
|
||||
RAMReady.D 11.4 11.0
|
||||
RAMReady.D 11.0 11.0
|
||||
RefReq.CE 10.0
|
||||
RefReq.D
|
||||
RefUrg.CE 10.0
|
||||
|
|
@ -305,7 +303,7 @@ cnt/LTimer<5>.D 10.0
|
|||
cnt/LTimer<6>.D 10.0
|
||||
cnt/LTimer<7>.D 10.0
|
||||
cnt/LTimer<8>.D 10.0
|
||||
cnt/LTimer<9>.D 10.0
|
||||
cnt/LTimer<9>.D 11.0
|
||||
cnt/LTimerTC.D
|
||||
cnt/Timer<0>.CE 10.0
|
||||
cnt/Timer<0>.D 10.0
|
||||
|
|
@ -334,25 +332,25 @@ nADoutLE1.D
|
|||
nAoutOE.D
|
||||
nBERR_FSB.D
|
||||
nBR_IOB.D
|
||||
nCAS.D
|
||||
nDTACK_FSB.D 11.4 11.0 11.4
|
||||
nCAS.D 11.0 11.0
|
||||
nDTACK_FSB.D 11.0 10.0 11.0
|
||||
nOE.D
|
||||
nRESout.D
|
||||
nVPA_FSB.D 11.0
|
||||
nVPA_FSB.D 10.0
|
||||
ram/BACTr.D
|
||||
ram/CAS.D 11.4 11.0
|
||||
ram/DTACKr.D
|
||||
ram/RASEL.D
|
||||
ram/RASEN.D 11.0 11.0
|
||||
ram/RASrf.D
|
||||
ram/RASrr.D
|
||||
ram/RASrr.D 10.0
|
||||
ram/RS_FSM_FFd1.D
|
||||
ram/RS_FSM_FFd2.D
|
||||
ram/RS_FSM_FFd3.D
|
||||
ram/RS_FSM_FFd4.D
|
||||
ram/RS_FSM_FFd5.D
|
||||
ram/RS_FSM_FFd6.D
|
||||
ram/RS_FSM_FFd7.D
|
||||
ram/RS_FSM_FFd7.D 11.0 10.0
|
||||
ram/RS_FSM_FFd8.D 11.0 11.0
|
||||
ram/RS_FSM_FFd9.D 11.4 11.4
|
||||
ram/RefDone.D 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
|
@ -394,10 +392,10 @@ RefUrg.D
|
|||
cnt/Er<1>.D
|
||||
cnt/IS_FSM_FFd1.D 10.0 10.0 10.0
|
||||
cnt/IS_FSM_FFd2.D 10.0 10.0 10.0
|
||||
cnt/LTimer<0>.D 19.1 20.5 20.5 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
||||
cnt/LTimer<0>.D 19.1 20.1 20.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
||||
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<1>.D 19.1 20.5 20.5 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
||||
cnt/LTimer<1>.D 19.1 20.1 20.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
||||
cnt/LTimer<2>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<3>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<4>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
|
|
@ -405,7 +403,7 @@ cnt/LTimer<5>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
|||
cnt/LTimer<6>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<7>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<9>.D 11.0 10.0 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/Timer<0>.CE 10.0
|
||||
cnt/Timer<0>.D 10.0
|
||||
|
|
@ -436,10 +434,11 @@ nBERR_FSB.D
|
|||
nBR_IOB.D 10.0 10.0
|
||||
nCAS.D
|
||||
nDTACK_FSB.D
|
||||
nOE.D
|
||||
nRESout.D 10.0 10.0
|
||||
nVPA_FSB.D
|
||||
ram/BACTr.D
|
||||
ram/CAS.D
|
||||
ram/DTACKr.D
|
||||
ram/RASEL.D
|
||||
ram/RASEN.D
|
||||
ram/RASrf.D
|
||||
|
|
@ -452,7 +451,6 @@ ram/RS_FSM_FFd5.D
|
|||
ram/RS_FSM_FFd6.D
|
||||
ram/RS_FSM_FFd7.D
|
||||
ram/RS_FSM_FFd8.D
|
||||
ram/RS_FSM_FFd9.D
|
||||
ram/RefDone.D
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
|
@ -505,7 +503,7 @@ cnt/LTimer<5>.D 10.0
|
|||
cnt/LTimer<6>.D 10.0 10.0
|
||||
cnt/LTimer<7>.D 10.0 10.0 10.0
|
||||
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/LTimer<9>.D 11.0 11.0 11.0 11.0 10.0
|
||||
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0
|
||||
cnt/Timer<0>.CE
|
||||
cnt/Timer<0>.D 10.0
|
||||
|
|
@ -536,10 +534,11 @@ nBERR_FSB.D
|
|||
nBR_IOB.D
|
||||
nCAS.D
|
||||
nDTACK_FSB.D
|
||||
nOE.D
|
||||
nRESout.D
|
||||
nVPA_FSB.D
|
||||
ram/BACTr.D
|
||||
ram/CAS.D
|
||||
ram/DTACKr.D
|
||||
ram/RASEL.D
|
||||
ram/RASEN.D
|
||||
ram/RASrf.D
|
||||
|
|
@ -552,7 +551,6 @@ ram/RS_FSM_FFd5.D
|
|||
ram/RS_FSM_FFd6.D
|
||||
ram/RS_FSM_FFd7.D
|
||||
ram/RS_FSM_FFd8.D
|
||||
ram/RS_FSM_FFd9.D
|
||||
ram/RefDone.D
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
|
@ -582,11 +580,11 @@ ram/RefDone.D
|
|||
ALE0S.D
|
||||
IOL0.D 11.0 11.0
|
||||
IONPReady.D 11.0
|
||||
IORDREQ.D 11.4 11.4 10.0
|
||||
IORDREQ.D 11.0 11.0 10.0
|
||||
IOU0.D 11.4 11.0
|
||||
IOWRREQ.D 11.0 11.0 10.0
|
||||
QoSReady.D 11.4 11.4 11.4 11.4 19.1
|
||||
RAMReady.D 11.4
|
||||
RAMReady.D 11.0
|
||||
RefReq.CE
|
||||
RefReq.D
|
||||
RefUrg.CE
|
||||
|
|
@ -594,10 +592,10 @@ RefUrg.D
|
|||
cnt/Er<1>.D
|
||||
cnt/IS_FSM_FFd1.D 10.0 10.0
|
||||
cnt/IS_FSM_FFd2.D 10.0
|
||||
cnt/LTimer<0>.D 19.1 20.5
|
||||
cnt/LTimer<0>.D 19.1 20.1
|
||||
cnt/LTimer<10>.D 10.0
|
||||
cnt/LTimer<11>.D 10.0
|
||||
cnt/LTimer<1>.D 19.1 20.5
|
||||
cnt/LTimer<1>.D 19.1 20.1
|
||||
cnt/LTimer<2>.D 10.0
|
||||
cnt/LTimer<3>.D 10.0
|
||||
cnt/LTimer<4>.D 10.0
|
||||
|
|
@ -605,7 +603,7 @@ cnt/LTimer<5>.D 10.0
|
|||
cnt/LTimer<6>.D 10.0
|
||||
cnt/LTimer<7>.D 10.0
|
||||
cnt/LTimer<8>.D 10.0
|
||||
cnt/LTimer<9>.D 10.0
|
||||
cnt/LTimer<9>.D 11.0
|
||||
cnt/LTimerTC.D
|
||||
cnt/Timer<0>.CE
|
||||
cnt/Timer<0>.D 10.0
|
||||
|
|
@ -618,7 +616,7 @@ cnt/Timer<3>.D 10.0
|
|||
cnt/TimerTC.CE
|
||||
cnt/TimerTC.D
|
||||
cnt/WS<0>.D 10.0 10.0
|
||||
cnt/WS<1>.D 11.0 11.0 11.0
|
||||
cnt/WS<1>.D 10.0 10.0 11.0
|
||||
cnt/WS<2>.D 10.0 10.0 10.0 10.0
|
||||
cnt/WS<3>.D 10.0 10.0 10.0 10.0 10.0
|
||||
cs/nOverlay.D 10.0 10.0
|
||||
|
|
@ -627,32 +625,32 @@ iobs/IOL1.CE
|
|||
iobs/IORW1.D 11.0
|
||||
iobs/IOU1.CE
|
||||
iobs/Load1.D 11.0
|
||||
iobs/Sent.D 11.0 11.0
|
||||
iobs/Sent.D 11.4 11.4
|
||||
iobs/TS_FSM_FFd1.D 10.0
|
||||
iobs/TS_FSM_FFd2.D 11.4 11.0 10.0
|
||||
iobs/TS_FSM_FFd2.D 11.0 10.0 10.0
|
||||
nADoutLE1.D 10.0
|
||||
nAoutOE.D
|
||||
nBERR_FSB.D 10.0
|
||||
nBR_IOB.D 10.0
|
||||
nCAS.D
|
||||
nDTACK_FSB.D 11.0
|
||||
nCAS.D 11.0
|
||||
nDTACK_FSB.D 10.0
|
||||
nOE.D 11.0
|
||||
nRESout.D
|
||||
nVPA_FSB.D 11.0
|
||||
nVPA_FSB.D 10.0
|
||||
ram/BACTr.D 10.0
|
||||
ram/CAS.D 11.0 11.4
|
||||
ram/DTACKr.D
|
||||
ram/RASEL.D 10.0 10.0
|
||||
ram/RASEN.D 11.4
|
||||
ram/RASEN.D 11.0
|
||||
ram/RASrf.D
|
||||
ram/RASrr.D 10.0 10.0
|
||||
ram/RS_FSM_FFd1.D
|
||||
ram/RS_FSM_FFd2.D
|
||||
ram/RS_FSM_FFd3.D
|
||||
ram/RS_FSM_FFd4.D
|
||||
ram/RS_FSM_FFd5.D 10.0
|
||||
ram/RS_FSM_FFd6.D
|
||||
ram/RS_FSM_FFd7.D 10.0 10.0
|
||||
ram/RS_FSM_FFd8.D 11.0
|
||||
ram/RS_FSM_FFd9.D 11.4 11.4
|
||||
ram/RS_FSM_FFd5.D
|
||||
ram/RS_FSM_FFd6.D 10.0 10.0
|
||||
ram/RS_FSM_FFd7.D 11.0
|
||||
ram/RS_FSM_FFd8.D 11.0 11.0
|
||||
ram/RefDone.D
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
|
@ -682,7 +680,7 @@ ram/RefDone.D
|
|||
ALE0S.D 10.0
|
||||
IOL0.D 11.0 10.0 10.0 11.4 11.4
|
||||
IONPReady.D 11.0 11.0
|
||||
IORDREQ.D 11.0 11.0 10.0 11.4 11.4
|
||||
IORDREQ.D 11.0 10.0 10.0 11.0 11.0
|
||||
IOU0.D 11.0 10.0 10.0 11.4 11.4
|
||||
IOWRREQ.D 10.0 11.0 11.0 11.0 11.0
|
||||
QoSReady.D
|
||||
|
|
@ -727,19 +725,20 @@ iobs/IOL1.CE 10.0
|
|||
iobs/IORW1.D 11.0 11.0 11.0 11.0 11.0
|
||||
iobs/IOU1.CE 10.0
|
||||
iobs/Load1.D 11.0 11.0 11.0 11.0
|
||||
iobs/Sent.D 11.0 11.0 11.0 11.0
|
||||
iobs/Sent.D 11.4 11.4 11.4 11.4
|
||||
iobs/TS_FSM_FFd1.D 10.0 10.0
|
||||
iobs/TS_FSM_FFd2.D 10.0 10.0 11.4 11.4
|
||||
iobs/TS_FSM_FFd2.D 10.0 10.0 11.0 11.0
|
||||
nADoutLE1.D 10.0 10.0
|
||||
nAoutOE.D 11.0
|
||||
nBERR_FSB.D 10.0
|
||||
nBR_IOB.D
|
||||
nCAS.D
|
||||
nDTACK_FSB.D 11.4
|
||||
nDTACK_FSB.D 11.0
|
||||
nOE.D
|
||||
nRESout.D
|
||||
nVPA_FSB.D
|
||||
ram/BACTr.D
|
||||
ram/CAS.D
|
||||
ram/DTACKr.D
|
||||
ram/RASEL.D
|
||||
ram/RASEN.D
|
||||
ram/RASrf.D
|
||||
|
|
@ -752,30 +751,29 @@ ram/RS_FSM_FFd5.D
|
|||
ram/RS_FSM_FFd6.D
|
||||
ram/RS_FSM_FFd7.D
|
||||
ram/RS_FSM_FFd8.D
|
||||
ram/RS_FSM_FFd9.D
|
||||
ram/RefDone.D
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: FCLK)
|
||||
|
||||
\ From n n r r r r r r r r
|
||||
\ B B a a a a a a a a
|
||||
\ E R m m m m m m m m
|
||||
\ R _ / / / / / / / /
|
||||
\ R I B C R R R R R R
|
||||
\ _ O A A A S S S S S
|
||||
\ F B C S S _ _ _ _ _
|
||||
\ S . T . E F F F F F
|
||||
\ B Q r Q N S S S S S
|
||||
\ . . . M M M M M
|
||||
\ Q Q Q _ _ _ _ _
|
||||
\ F F F F F
|
||||
\ F F F F F
|
||||
\ d d d d d
|
||||
\ 1 2 3 4 5
|
||||
\ . . . . .
|
||||
\ Q Q Q Q Q
|
||||
\ From n n n r r r r r r r
|
||||
\ B B D a a a a a a a
|
||||
\ E R T m m m m m m m
|
||||
\ R _ A / / / / / / /
|
||||
\ R I C B D R R R R R
|
||||
\ _ O K A T A A S S S
|
||||
\ F B _ C A S S _ _ _
|
||||
\ S . F T C E r F F F
|
||||
\ B Q S r K N r S S S
|
||||
\ . B . r . . M M M
|
||||
\ Q . Q . Q Q _ _ _
|
||||
\ Q Q F F F
|
||||
\ F F F
|
||||
\ d d d
|
||||
\ 1 2 3
|
||||
\ . . .
|
||||
\ Q Q Q
|
||||
\
|
||||
To \------------------------------------------------------------
|
||||
|
||||
|
|
@ -786,7 +784,7 @@ IORDREQ.D
|
|||
IOU0.D
|
||||
IOWRREQ.D
|
||||
QoSReady.D
|
||||
RAMReady.D 11.4 10.0 11.4 11.0 11.0 10.0 11.4
|
||||
RAMReady.D 11.0 10.0 11.0
|
||||
RefReq.CE
|
||||
RefReq.D
|
||||
RefUrg.CE
|
||||
|
|
@ -834,126 +832,126 @@ nADoutLE1.D
|
|||
nAoutOE.D 11.0
|
||||
nBERR_FSB.D 11.0
|
||||
nBR_IOB.D 10.0
|
||||
nCAS.D 10.0
|
||||
nCAS.D 11.0 10.0 11.0 10.0 10.0 10.0
|
||||
nDTACK_FSB.D
|
||||
nOE.D 11.0 11.0
|
||||
nRESout.D
|
||||
nVPA_FSB.D
|
||||
ram/BACTr.D
|
||||
ram/CAS.D 11.4 10.0 11.0
|
||||
ram/RASEL.D 10.0
|
||||
ram/RASEN.D 11.0 11.4 10.0 10.0 10.0 10.0 11.0
|
||||
ram/DTACKr.D 10.0
|
||||
ram/RASEL.D 10.0 10.0
|
||||
ram/RASEN.D 11.0 10.0 11.0
|
||||
ram/RASrf.D
|
||||
ram/RASrr.D 10.0 10.0
|
||||
ram/RS_FSM_FFd1.D 10.0
|
||||
ram/RS_FSM_FFd2.D 10.0
|
||||
ram/RS_FSM_FFd3.D 10.0
|
||||
ram/RS_FSM_FFd4.D
|
||||
ram/RS_FSM_FFd5.D 10.0
|
||||
ram/RS_FSM_FFd6.D
|
||||
ram/RS_FSM_FFd7.D 10.0
|
||||
ram/RS_FSM_FFd8.D 11.0 10.0 11.0
|
||||
ram/RS_FSM_FFd9.D 11.4 11.4 10.0 11.0
|
||||
ram/RefDone.D 10.0 10.0 10.0 10.0
|
||||
ram/RASrr.D 10.0 10.0
|
||||
ram/RS_FSM_FFd1.D 10.0 10.0
|
||||
ram/RS_FSM_FFd2.D 10.0 10.0 10.0
|
||||
ram/RS_FSM_FFd3.D
|
||||
ram/RS_FSM_FFd4.D 10.0
|
||||
ram/RS_FSM_FFd5.D 10.0
|
||||
ram/RS_FSM_FFd6.D 10.0
|
||||
ram/RS_FSM_FFd7.D 11.0 10.0
|
||||
ram/RS_FSM_FFd8.D 11.0 11.0 11.0
|
||||
ram/RefDone.D 10.0 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: FCLK)
|
||||
|
||||
\ From r r r r r
|
||||
\ a a a a a
|
||||
\ m m m m m
|
||||
\ / / / / /
|
||||
\ R R R R R
|
||||
\ S S S S e
|
||||
\ _ _ _ _ f
|
||||
\ F F F F D
|
||||
\ S S S S o
|
||||
\ M M M M n
|
||||
\ _ _ _ _ e
|
||||
\ F F F F .
|
||||
\ F F F F Q
|
||||
\ d d d d
|
||||
\ 6 7 8 9
|
||||
\ . . . .
|
||||
\ Q Q Q Q
|
||||
\
|
||||
To \------------------------------
|
||||
\ From r r r r r r
|
||||
\ a a a a a a
|
||||
\ m m m m m m
|
||||
\ / / / / / /
|
||||
\ R R R R R R
|
||||
\ S S S S S e
|
||||
\ _ _ _ _ _ f
|
||||
\ F F F F F D
|
||||
\ S S S S S o
|
||||
\ M M M M M n
|
||||
\ _ _ _ _ _ e
|
||||
\ F F F F F .
|
||||
\ F F F F F Q
|
||||
\ d d d d d
|
||||
\ 4 5 6 7 8
|
||||
\ . . . . .
|
||||
\ Q Q Q Q Q
|
||||
\
|
||||
To \------------------------------------
|
||||
|
||||
ALE0S.D
|
||||
IOL0.D
|
||||
IONPReady.D
|
||||
IORDREQ.D
|
||||
IOU0.D
|
||||
IOWRREQ.D
|
||||
QoSReady.D
|
||||
RAMReady.D 11.4 11.4 10.0 11.4 11.4
|
||||
RefReq.CE
|
||||
RefReq.D
|
||||
RefUrg.CE
|
||||
RefUrg.D
|
||||
cnt/Er<1>.D
|
||||
cnt/IS_FSM_FFd1.D
|
||||
cnt/IS_FSM_FFd2.D
|
||||
cnt/LTimer<0>.D
|
||||
cnt/LTimer<10>.D
|
||||
cnt/LTimer<11>.D
|
||||
cnt/LTimer<1>.D
|
||||
cnt/LTimer<2>.D
|
||||
cnt/LTimer<3>.D
|
||||
cnt/LTimer<4>.D
|
||||
cnt/LTimer<5>.D
|
||||
cnt/LTimer<6>.D
|
||||
cnt/LTimer<7>.D
|
||||
cnt/LTimer<8>.D
|
||||
cnt/LTimer<9>.D
|
||||
cnt/LTimerTC.D
|
||||
cnt/Timer<0>.CE
|
||||
cnt/Timer<0>.D
|
||||
cnt/Timer<1>.CE
|
||||
cnt/Timer<1>.D
|
||||
cnt/Timer<2>.CE
|
||||
cnt/Timer<2>.D
|
||||
cnt/Timer<3>.CE
|
||||
cnt/Timer<3>.D
|
||||
cnt/TimerTC.CE
|
||||
cnt/TimerTC.D
|
||||
cnt/WS<0>.D
|
||||
cnt/WS<1>.D
|
||||
cnt/WS<2>.D
|
||||
cnt/WS<3>.D
|
||||
cs/nOverlay.D
|
||||
iobs/Clear1.D
|
||||
iobs/IOL1.CE
|
||||
iobs/IORW1.D
|
||||
iobs/IOU1.CE
|
||||
iobs/Load1.D
|
||||
iobs/Sent.D
|
||||
iobs/TS_FSM_FFd1.D
|
||||
iobs/TS_FSM_FFd2.D
|
||||
nADoutLE1.D
|
||||
nAoutOE.D
|
||||
nBERR_FSB.D
|
||||
nBR_IOB.D
|
||||
nCAS.D
|
||||
nDTACK_FSB.D
|
||||
nRESout.D
|
||||
nVPA_FSB.D
|
||||
ram/BACTr.D
|
||||
ram/CAS.D 10.0 10.0 11.4 11.4
|
||||
ram/RASEL.D 10.0 10.0
|
||||
ram/RASEN.D 10.0 10.0 10.0 11.4 11.0
|
||||
ram/RASrf.D 10.0
|
||||
ram/RASrr.D 10.0 10.0
|
||||
ram/RS_FSM_FFd1.D
|
||||
ram/RS_FSM_FFd2.D
|
||||
ram/RS_FSM_FFd3.D
|
||||
ram/RS_FSM_FFd4.D 10.0
|
||||
ram/RS_FSM_FFd5.D 10.0
|
||||
ram/RS_FSM_FFd6.D 10.0
|
||||
ram/RS_FSM_FFd7.D 10.0
|
||||
ram/RS_FSM_FFd8.D 11.0 11.0
|
||||
ram/RS_FSM_FFd9.D 11.4 11.0
|
||||
ram/RefDone.D 10.0 10.0
|
||||
ALE0S.D
|
||||
IOL0.D
|
||||
IONPReady.D
|
||||
IORDREQ.D
|
||||
IOU0.D
|
||||
IOWRREQ.D
|
||||
QoSReady.D
|
||||
RAMReady.D 11.0 11.0 11.0 10.0 11.0
|
||||
RefReq.CE
|
||||
RefReq.D
|
||||
RefUrg.CE
|
||||
RefUrg.D
|
||||
cnt/Er<1>.D
|
||||
cnt/IS_FSM_FFd1.D
|
||||
cnt/IS_FSM_FFd2.D
|
||||
cnt/LTimer<0>.D
|
||||
cnt/LTimer<10>.D
|
||||
cnt/LTimer<11>.D
|
||||
cnt/LTimer<1>.D
|
||||
cnt/LTimer<2>.D
|
||||
cnt/LTimer<3>.D
|
||||
cnt/LTimer<4>.D
|
||||
cnt/LTimer<5>.D
|
||||
cnt/LTimer<6>.D
|
||||
cnt/LTimer<7>.D
|
||||
cnt/LTimer<8>.D
|
||||
cnt/LTimer<9>.D
|
||||
cnt/LTimerTC.D
|
||||
cnt/Timer<0>.CE
|
||||
cnt/Timer<0>.D
|
||||
cnt/Timer<1>.CE
|
||||
cnt/Timer<1>.D
|
||||
cnt/Timer<2>.CE
|
||||
cnt/Timer<2>.D
|
||||
cnt/Timer<3>.CE
|
||||
cnt/Timer<3>.D
|
||||
cnt/TimerTC.CE
|
||||
cnt/TimerTC.D
|
||||
cnt/WS<0>.D
|
||||
cnt/WS<1>.D
|
||||
cnt/WS<2>.D
|
||||
cnt/WS<3>.D
|
||||
cs/nOverlay.D
|
||||
iobs/Clear1.D
|
||||
iobs/IOL1.CE
|
||||
iobs/IORW1.D
|
||||
iobs/IOU1.CE
|
||||
iobs/Load1.D
|
||||
iobs/Sent.D
|
||||
iobs/TS_FSM_FFd1.D
|
||||
iobs/TS_FSM_FFd2.D
|
||||
nADoutLE1.D
|
||||
nAoutOE.D
|
||||
nBERR_FSB.D
|
||||
nBR_IOB.D
|
||||
nCAS.D 11.0 10.0 11.0 11.0 11.0
|
||||
nDTACK_FSB.D
|
||||
nOE.D
|
||||
nRESout.D
|
||||
nVPA_FSB.D
|
||||
ram/BACTr.D
|
||||
ram/DTACKr.D
|
||||
ram/RASEL.D 10.0 10.0 10.0
|
||||
ram/RASEN.D 11.0 10.0 11.0
|
||||
ram/RASrf.D 10.0
|
||||
ram/RASrr.D 10.0 10.0 10.0 10.0
|
||||
ram/RS_FSM_FFd1.D
|
||||
ram/RS_FSM_FFd2.D
|
||||
ram/RS_FSM_FFd3.D 10.0
|
||||
ram/RS_FSM_FFd4.D 10.0
|
||||
ram/RS_FSM_FFd5.D 10.0 10.0
|
||||
ram/RS_FSM_FFd6.D 10.0
|
||||
ram/RS_FSM_FFd7.D 10.0 11.0 11.0
|
||||
ram/RS_FSM_FFd8.D 11.0 11.0 11.0
|
||||
ram/RefDone.D 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -5,7 +5,7 @@
|
|||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Mon Apr 10 04:04:57 2023">
|
||||
<application stringID="NgdBuild" timeStamp="Sat Apr 15 05:21:44 2023">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
|
|
@ -66,8 +66,8 @@
|
|||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="222"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="211"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="12"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="68"/>
|
||||
|
|
@ -76,25 +76,25 @@
|
|||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="277"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="262"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="119"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="105"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="14"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="222"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="211"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="12"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="77"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="41"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="277"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="262"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="119"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="105"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="14"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
4-10-2023 4:05AM
|
||||
4-15-2023 5:21AM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
|
|
|||
|
|
|
@ -5,7 +5,7 @@
|
|||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Mon Apr 10 04:04:47 2023">
|
||||
<application stringID="Xst" timeStamp="Sat Apr 15 05:21:34 2023">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
|
|
@ -79,8 +79,8 @@
|
|||
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
||||
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="67">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="66"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="68">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="67"/>
|
||||
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="5">
|
||||
|
|
@ -93,8 +93,8 @@
|
|||
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
||||
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="47">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="47"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="48">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="48"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
|
|
@ -114,13 +114,13 @@
|
|||
<item stringID="XST_IOS" value="75"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="710">
|
||||
<item dataType="int" stringID="XST_AND2" value="222"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="30"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="672">
|
||||
<item dataType="int" stringID="XST_AND2" value="211"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="29"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="12"/>
|
||||
<item dataType="int" stringID="XST_GND" value="6"/>
|
||||
<item dataType="int" stringID="XST_INV" value="277"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="119"/>
|
||||
<item dataType="int" stringID="XST_INV" value="262"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="105"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="20"/>
|
||||
</item>
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681113892
|
||||
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681550499
|
||||
OK
|
||||
|
|
|
|||
|
|
@ -23,13 +23,13 @@
|
|||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
<SelectedItem/>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
<CurrentItem/>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
|
|
@ -64,13 +64,13 @@
|
|||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>Generate Timing</SelectedItem>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>Generate Timing</CurrentItem>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
|
||||
<CurrentView>Implementation</CurrentView>
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2023-04-10T03:54:15</DateModified>
|
||||
<DateModified>2023-04-15T05:22:02</DateModified>
|
||||
<ModuleName>WarpSE</ModuleName>
|
||||
<SummaryTimeStamp>2023-04-09T23:24:43</SummaryTimeStamp>
|
||||
<SummaryTimeStamp>2023-04-10T19:23:46</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2023-04-07T01:51:28</DateInitialized>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Mon Apr 10 04:04:46 2023">
|
||||
<application name="pn" timeStamp="Sat Apr 15 05:21:26 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="7132971001B64D51887D7F260ADC77C3" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,7 +1,7 @@
|
|||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681113887
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1681113887
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681113887
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681113887
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681113887
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681113887
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681113887
|
||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681550494
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1681550494
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681550494
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681550494
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681550494
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681550494
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681550494
|
||||
|
|
|
|||
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Loading…
Reference in New Issue