mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-21 17:31:47 +00:00
0.7a-fastscsi compiled
This commit is contained in:
Zane Kaminski
parent
1c2b6508f8
commit
f7e3ae2376
@ -17,14 +17,14 @@ module SET(
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always @(posedge CLK) begin
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if (!nPOR) begin
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SlowTimeout[3:0] <= 4'h0;
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SlowTimeout[3:0] <= 4'hF;
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SlowIACK <= 1;
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SlowVIA <= 1;
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SlowIWM <= 1;
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SlowSCC <= 1;
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SlowSCSI <= 1;
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SlowSCSI <= 0;
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SlowSnd <= 1;
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SlowClockGate <= 0;
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SlowClockGate <= 1;
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end else if (SetWRr) begin
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SlowTimeout[3:0] <= A[11:8];
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SlowIACK <= A[7];
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5163
cpld/XC95144XL/WarpSE-0.7a-fastscsi.svf
Normal file
5163
cpld/XC95144XL/WarpSE-0.7a-fastscsi.svf
Normal file
File diff suppressed because it is too large
Load Diff
@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of warnings: 0
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Total memory usage is 155008 kilobytes
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Total memory usage is 154688 kilobytes
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Writing NGD file "WarpSE.ngd" ...
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Total REAL time to NGDBUILD completion: 3 sec
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@ -1262,3 +1262,10 @@ XSLTProcess WarpSE_build.xml
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tsim -intstyle ise WarpSE WarpSE.nga
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taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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xst -intstyle ise -ifn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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XSLTProcess WarpSE_build.xml
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tsim -intstyle ise WarpSE WarpSE.nga
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taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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@ -70,7 +70,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1728682919" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728682912">
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<transform xil_pn:end_ts="1728683116" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728683108">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -90,7 +90,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1728682924" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728682919">
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<transform xil_pn:end_ts="1728683122" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728683116">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpSE.bld"/>
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@ -99,7 +99,7 @@
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<outfile xil_pn:name="_ngo"/>
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<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1728682950" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728682924">
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<transform xil_pn:end_ts="1728683148" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728683122">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -119,12 +119,12 @@
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<outfile xil_pn:name="WarpSE_html"/>
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<outfile xil_pn:name="WarpSE_pad.csv"/>
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</transform>
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<transform xil_pn:end_ts="1728682967" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728682965">
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<transform xil_pn:end_ts="1728683158" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728683156">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpSE.jed"/>
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</transform>
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<transform xil_pn:end_ts="1728682975" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728682975">
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<transform xil_pn:end_ts="1728683158" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728683158">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_impactbatch.log"/>
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@ -133,12 +133,14 @@
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<transform xil_pn:end_ts="1728682967" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_configureTargetDevice_CPLD" xil_pn:prop_ck="-742897827381199779" xil_pn:start_ts="1728682967">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="_impactbatch.log"/>
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<outfile xil_pn:name="ise_impact.cmd"/>
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</transform>
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<transform xil_pn:end_ts="1728682952" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728682950">
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<transform xil_pn:end_ts="1728683150" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728683148">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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@ -1,5 +1,5 @@
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Programmer Jedec Bit Map
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Date Extracted: Fri Oct 11 17:42:46 2024
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Date Extracted: Fri Oct 11 17:45:57 2024
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QF93312*
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QP100*
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@ -330,7 +330,7 @@ L0013632 000000 000000 000000 000000 000001 000000 000000 000000*
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||||
L0013680 000000 000000 000000 000000 000001 000000 000000 000000*
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L0013776 000000 000000 000000 000000 000001 000000 000000 000000*
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||||
L0013824 00001000 00000000 00000000 00000000 00011010 00000001 01001011 00000011*
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||||
L0013824 00000000 00000000 00000000 00000000 00011010 00000001 01001011 00000011*
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||||
L0013888 00000000 00000000 00000000 00000000 00011000 00000011 00011000 00000001*
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||||
L0013952 00000000 00000000 00000000 00000000 00001000 00000001 00000000 00000001*
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||||
L0014016 00000000 00000000 00000000 00000000 00000001 00000001 00010001 00000011*
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||||
@ -345,7 +345,7 @@ L0014496 000000 000000 000000 000001 000000 000000 000000 000000*
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||||
L0014544 000000 000000 000000 000000 000000 000000 001000 000000*
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L0014592 000000 000000 000000 000000 000000 000000 001100 000000*
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L0014640 000000 000000 000000 000000 000000 000000 000000 000000*
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L0014688 00000000 00000000 11111000 01000000 00000000 00000000 00010000 00000000*
|
||||
L0014688 00001000 00000000 11111000 01000000 00000000 00000000 00010000 00000000*
|
||||
L0014752 00000000 00000000 00000000 01000000 00000000 00000000 00000011 01000010*
|
||||
L0014816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01001010*
|
||||
L0014880 00000000 00000000 00000000 00000000 00000000 00000000 10000100 00001000*
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@ -360,7 +360,7 @@ L0015360 000000 000000 000000 100000 000000 000000 000000 000000*
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L0015408 000000 000000 000000 000000 000000 000000 000000 000000*
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L0015456 000000 000000 000000 000000 000000 000000 000000 000000*
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L0015504 000000 000000 000000 000000 000000 000000 000000 000000*
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L0015552 00000010 00000000 00000001 00000000 00000010 00010101 00000011 00000010*
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L0015552 00010010 00000000 00000001 00000000 00000010 00010101 00000011 00000010*
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L0015616 00000000 00000000 00010001 00000001 00000000 00010101 00000000 00000001*
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L0015680 00000000 00000000 00000011 00000000 00000000 00010101 00000001 00000000*
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L0015744 00000000 00000000 00000011 00000000 00000000 00010101 00000001 00000001*
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@ -375,7 +375,7 @@ L0016224 000000 000000 000000 000000 000000 000010 000000 000000*
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L0016272 000000 000000 000000 000000 000000 001100 000011 000000*
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L0016320 000000 000000 000000 000000 000000 001100 000000 000000*
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L0016368 000000 000000 000000 000000 000000 001000 000000 000000*
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L0016416 00010010 00000000 00000001 00000000 00000000 00000000 00001000 00000000*
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L0016416 00000010 00000000 00000001 00000000 00000000 00000000 00001000 00000000*
|
||||
L0016480 00000000 00000000 00000001 00000001 00000000 10000000 00001011 00000010*
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||||
L0016544 00000000 00000000 00000011 00000000 00000000 00001000 00001001 00000011*
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||||
L0016608 00000000 00000000 00000011 00000000 10000000 00000000 00001000 00000000*
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@ -420,18 +420,18 @@ L0018816 000000 000000 000000 000000 000001 000000 000000 000000*
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L0018864 000000 000000 000000 000000 000001 000000 000000 000000*
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L0019008 00000010 00000000 00000000 00000001 00000000 00000001 00000010 00000000*
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L0019072 00000000 00000000 00000010 00000011 00000010 00000000 00000000 00000000*
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L0019136 00000001 00000000 00000000 00000000 00000000 00000010 00000011 00000000*
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L0019200 00000001 00000000 00000000 00000000 00000000 00000010 00000000 00000010*
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L0019008 00000011 00000000 00000000 00000001 00000000 00000001 00000010 00000000*
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L0019072 00000001 00000000 00000010 00000011 00000010 00000000 00000000 00000000*
|
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L0019136 00000001 00000000 00000000 00000001 00000000 00000010 00000011 00000000*
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L0019200 00000000 00000000 00000000 00000001 00000000 00000010 00000000 00000010*
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L0019264 00000001 00000000 00000000 00000010 00000010 00000001 00000000 00000010*
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L0019328 00000001 00000000 00000001 00000011 00000010 00000010 00000000 00000010*
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||||
L0019392 00000001 00000000 00000001 00000010 00000000 00000001 00000001 00000000*
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L0019456 00000000 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
|
||||
L0019456 00000001 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
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||||
L0019520 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000*
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L0019584 000000 000000 000000 000000 000000 000000 000000 000000*
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L0019632 000000 001000 000000 000000 000000 100000 000000 000100*
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L0019680 000000 000000 000000 000000 000000 100000 000000 000000*
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L0019680 000000 000000 000000 000100 000000 100000 000000 000000*
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L0019776 000000 000000 000000 000000 000000 000000 000000 000000*
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L0019824 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -446,16 +446,16 @@ L0020320 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001
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||||
L0020384 00000000 00000000 00000010 00000000 00000000 00000011 00000000 00000010*
|
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L0020448 000000 000000 000000 000000 000000 000000 000000 000000*
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L0020496 000000 000000 000000 000000 000000 000000 000000 000000*
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L0020544 000000 000000 000000 000100 000001 000000 000000 000100*
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L0020544 000000 000000 000000 000000 000001 000000 000000 000100*
|
||||
L0020592 000000 000000 000000 000000 000001 000000 000000 000100*
|
||||
L0020640 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0020688 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0020736 00000000 00000000 00000000 00000000 00000000 00000000 00000011 00000010*
|
||||
L0020800 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010*
|
||||
L0020800 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00000010*
|
||||
L0020864 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0020928 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0020992 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000001*
|
||||
L0021056 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0021056 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0021120 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
|
||||
L0021184 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
|
||||
L0021248 00000000 00000000 00000010 00000000 00000000 00000001 00000000 00000000*
|
||||
@ -466,11 +466,11 @@ L0021456 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0021504 000000 000000 000000 000000 000000 000000 000000 100000*
|
||||
L0021552 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0021600 00000000 00000000 10000001 00000000 00000000 00001010 00000000 00000000*
|
||||
L0021664 00000000 00000000 00000000 00001000 00000000 00001000 00000011 00000010*
|
||||
L0021664 00000000 00000000 00000000 00000000 00000000 00001000 00000011 00000010*
|
||||
L0021728 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000010*
|
||||
L0021792 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000000*
|
||||
L0021856 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000*
|
||||
L0021920 00000100 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
|
||||
L0021920 00000000 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
|
||||
L0021984 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0022048 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
|
||||
L0022112 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
|
||||
@ -1020,7 +1020,7 @@ L0053376 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0053424 000000 000000 000000 010000 000000 000000 000000 100000*
|
||||
L0053472 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0053520 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0053568 00000010 00000000 00000010 00000010 00000001 00000000 00000000 00000000*
|
||||
L0053568 00000010 00000000 00000010 00001010 00000001 00000000 00000000 00000000*
|
||||
L0053632 00000000 00000010 00000001 00000000 00000001 00000010 00000001 00000010*
|
||||
L0053696 00000000 00000010 00000001 00000010 00000000 00000010 00000011 00000000*
|
||||
L0053760 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
@ -1035,7 +1035,7 @@ L0054240 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0054288 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0054336 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0054384 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0054432 00000000 00000001 00000010 00001010 00000001 00000000 00000001 00000011*
|
||||
L0054432 00000000 00000001 00000010 00000010 00000001 00000000 00000001 00000011*
|
||||
L0054496 00000000 00000001 00000000 00000010 00000001 00000001 00000011 00000001*
|
||||
L0054560 00000001 00000000 00000000 00000010 00000000 00000011 00000010 00000011*
|
||||
L0054624 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
@ -1240,7 +1240,7 @@ L0066048 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0066112 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
|
||||
L0066176 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
|
||||
L0066240 000000 000000 000000 000000 000000 000000 000010 000000*
|
||||
L0066288 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0066288 000000 000000 000000 000100 000000 000000 000000 000000*
|
||||
L0066336 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0066384 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0066432 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1255,7 +1255,7 @@ L0066912 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0066976 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067104 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067152 000000 000000 000000 000100 000000 000000 000000 000000*
|
||||
L0067152 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067200 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067248 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0067296 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1265,7 +1265,7 @@ L0067456 00000000 00000000 00000010 00000000 00000010 00000010 00001010 00000010
|
||||
L0067520 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
|
||||
L0067584 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
|
||||
L0067648 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067712 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067712 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0067776 00000010 00000010 00100010 00000010 00000010 00000010 00000110 00000010*
|
||||
L0067840 00000000 00000000 00000000 00000000 00000000 00000000 10000100 00000000*
|
||||
L0067904 00000000 00000000 00000000 00000000 00000000 00000000 10010100 00000000*
|
||||
@ -1280,7 +1280,7 @@ L0068320 00000000 00000000 00000000 00000000 00000000 00000000 01000000 00000000
|
||||
L0068384 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0068448 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0068512 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0068576 00010000 00000000 00000100 00000000 00000000 00000000 00000100 00000000*
|
||||
L0068576 00000000 00000000 00000100 00000000 00000000 00000000 00000100 00000000*
|
||||
L0068640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0068704 00000000 00000000 00100000 00000000 00000000 00000000 00010000 00000000*
|
||||
L0068768 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
@ -1296,7 +1296,7 @@ L0069248 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0069312 00000000 00000000 00000000 00000000 00000000 00010000 00000000 00000000*
|
||||
L0069376 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0069440 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0069504 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0069504 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0069568 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0069632 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0069696 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1311,7 +1311,7 @@ L0070112 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0070176 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0070240 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0070304 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0070368 00010000 00000000 00000000 00000000 00001000 00000000 00000000 00000000*
|
||||
L0070368 00000000 00000000 00000000 00000000 00001000 00000000 00000000 00000000*
|
||||
L0070432 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0070496 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0070560 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1446,7 +1446,7 @@ L0077888 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000
|
||||
L0077952 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078016 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078080 00000000 00000000 10000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078144 00000000 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078144 00000100 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078208 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078272 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078336 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
@ -1461,7 +1461,7 @@ L0078752 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
||||
L0078816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078880 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0078944 00000000 00000000 00001000 00000000 00000000 00000000 00000000 00010000*
|
||||
L0079008 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
|
||||
L0079008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
|
||||
L0079072 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
|
||||
L0079136 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
|
||||
L0079200 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
@ -1651,7 +1651,7 @@ L0089712 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0089760 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0089808 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0089856 00000000 00000000 00000000 10100000 00000000 00000000 00000000 00000000*
|
||||
L0089920 00001000 00000000 00000100 00000100 00000000 00000000 00010000 00000000*
|
||||
L0089920 00000000 00000000 00000100 00000100 00000000 00000000 00010000 00000000*
|
||||
L0089984 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
|
||||
L0090048 00000000 00000000 00000000 00100100 00000000 00000000 00010000 00000000*
|
||||
L0090112 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
|
||||
@ -1666,7 +1666,7 @@ L0090576 000000 000000 000000 000000 000000 000000 001000 000100*
|
||||
L0090624 000000 000000 000000 000010 000000 000000 001000 000000*
|
||||
L0090672 000000 000000 000000 000000 000000 000000 001000 000000*
|
||||
L0090720 00000000 00000100 10000000 00000000 00000000 00000000 10001100 00000000*
|
||||
L0090784 00000000 00000000 00000000 00000000 00000000 00000000 10100100 00000000*
|
||||
L0090784 00001000 00000000 00000000 00000000 00000000 00000000 10100100 00000000*
|
||||
L0090848 00000000 00000000 00000100 00000000 00000000 00000000 00001000 00000000*
|
||||
L0090912 00000000 00000000 01111000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0090976 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
@ -1681,7 +1681,7 @@ L0091440 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0091488 000000 000000 110100 000000 000000 000000 000000 000000*
|
||||
L0091536 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0091584 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000*
|
||||
L0091648 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000*
|
||||
L0091648 00010000 00000000 00000000 00000000 00000000 00000000 00000000 01000000*
|
||||
L0091712 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11001100*
|
||||
L0091776 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10001000*
|
||||
L0091840 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000*
|
||||
@ -1696,7 +1696,7 @@ L0092304 000000 000000 000000 000000 000000 000000 000000 001011*
|
||||
L0092352 000000 000000 000000 000000 000000 000000 000000 001011*
|
||||
L0092400 000000 000000 000000 000000 000000 000000 000000 001001*
|
||||
L0092448 00000000 00000000 00000000 00000000 00000000 10000000 00000000 00000000*
|
||||
L0092512 00010000 00000000 00000000 00000000 00000000 01000000 00000000 10001000*
|
||||
L0092512 00000000 00000000 00000000 00000000 00000000 01000000 00000000 10001000*
|
||||
L0092576 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0092640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
|
||||
L0092704 00000000 00000000 00000000 00000000 00000000 00000100 00000000 00000000*
|
||||
@ -1710,5 +1710,5 @@ L0093120 000000 000000 000000 000000 000000 000010 010000 000000*
|
||||
L0093168 000000 000000 000000 000000 000001 000000 000000 000000*
|
||||
L0093216 000000 000000 000000 000000 000000 000000 000000 000000*
|
||||
L0093264 000000 000000 000001 000000 000001 000000 000000 000000*
|
||||
C49F6*
|
||||
29DC
|
||||
C4BF6*
|
||||
29E9
|
||||
|
||||
@ -575,8 +575,8 @@ INPUTS | 4 | nPOR | SlowClockGate | set/SetWRr | A_FSB<1>
|
||||
INPUTMC | 3 | 0 | 17 | 0 | 16 | 6 | 3
|
||||
INPUTP | 1 | 149
|
||||
EQ | 3 |
|
||||
SlowClockGate.D = nPOR & SlowClockGate & !set/SetWRr
|
||||
# nPOR & A_FSB<1> & set/SetWRr;
|
||||
!SlowClockGate.D = nPOR & !SlowClockGate & !set/SetWRr
|
||||
# nPOR & !A_FSB<1> & set/SetWRr;
|
||||
SlowClockGate.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
@ -623,8 +623,8 @@ INPUTS | 4 | nPOR | SlowSCSI | set/SetWRr | A_FSB<3>
|
||||
INPUTMC | 3 | 0 | 17 | 0 | 12 | 6 | 3
|
||||
INPUTP | 1 | 155
|
||||
EQ | 3 |
|
||||
!SlowSCSI.D = nPOR & !SlowSCSI & !set/SetWRr
|
||||
# nPOR & !A_FSB<3> & set/SetWRr;
|
||||
SlowSCSI.D = nPOR & SlowSCSI & !set/SetWRr
|
||||
# nPOR & A_FSB<3> & set/SetWRr;
|
||||
SlowSCSI.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
@ -647,8 +647,8 @@ INPUTS | 4 | nPOR | SlowTimeout<0> | set/SetWRr | A_FSB<8>
|
||||
INPUTMC | 3 | 0 | 17 | 0 | 10 | 6 | 3
|
||||
INPUTP | 1 | 11
|
||||
EQ | 3 |
|
||||
SlowTimeout<0>.D = nPOR & SlowTimeout<0> & !set/SetWRr
|
||||
# nPOR & A_FSB<8> & set/SetWRr;
|
||||
!SlowTimeout<0>.D = nPOR & !SlowTimeout<0> & !set/SetWRr
|
||||
# nPOR & !A_FSB<8> & set/SetWRr;
|
||||
SlowTimeout<0>.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
@ -659,8 +659,8 @@ INPUTS | 4 | nPOR | SlowTimeout<1> | set/SetWRr | A_FSB<9>
|
||||
INPUTMC | 3 | 0 | 17 | 0 | 9 | 6 | 3
|
||||
INPUTP | 1 | 12
|
||||
EQ | 3 |
|
||||
SlowTimeout<1>.D = nPOR & SlowTimeout<1> & !set/SetWRr
|
||||
# nPOR & A_FSB<9> & set/SetWRr;
|
||||
!SlowTimeout<1>.D = nPOR & !SlowTimeout<1> & !set/SetWRr
|
||||
# nPOR & !A_FSB<9> & set/SetWRr;
|
||||
SlowTimeout<1>.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
@ -671,8 +671,8 @@ INPUTS | 4 | nPOR | SlowTimeout<2> | set/SetWRr | A_FSB<10>
|
||||
INPUTMC | 3 | 0 | 17 | 3 | 12 | 6 | 3
|
||||
INPUTP | 1 | 13
|
||||
EQ | 3 |
|
||||
SlowTimeout<2>.D = A_FSB<10> & nPOR & set/SetWRr
|
||||
# nPOR & SlowTimeout<2> & !set/SetWRr;
|
||||
!SlowTimeout<2>.D = !A_FSB<10> & nPOR & set/SetWRr
|
||||
# nPOR & !SlowTimeout<2> & !set/SetWRr;
|
||||
SlowTimeout<2>.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
@ -683,8 +683,8 @@ INPUTS | 4 | nPOR | SlowTimeout<3> | set/SetWRr | A_FSB<11>
|
||||
INPUTMC | 3 | 0 | 17 | 3 | 11 | 6 | 3
|
||||
INPUTP | 1 | 15
|
||||
EQ | 3 |
|
||||
SlowTimeout<3>.D = A_FSB<11> & nPOR & set/SetWRr
|
||||
# nPOR & SlowTimeout<3> & !set/SetWRr;
|
||||
!SlowTimeout<3>.D = !A_FSB<11> & nPOR & set/SetWRr
|
||||
# nPOR & !SlowTimeout<3> & !set/SetWRr;
|
||||
SlowTimeout<3>.CLK = FCLK; // GCK
|
||||
GLOBALS | 1 | 2 | FCLK
|
||||
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
10-11-2024 5:42PM
|
||||
10-11-2024 5:45PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
|
||||
cpldfit: version P.20131013 Xilinx Inc.
|
||||
Fitter Report
|
||||
Design Name: WarpSE Date: 10-11-2024, 5:42PM
|
||||
Design Name: WarpSE Date: 10-11-2024, 5:45PM
|
||||
Device Used: XC95144XL-10-TQ100
|
||||
Fitting Status: Successful
|
||||
|
||||
@ -982,8 +982,8 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
|
||||
RnW_IOB_OE <= NOT nAoutOE;
|
||||
|
||||
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
|
||||
SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(1) AND set/SetWRr));
|
||||
SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
|
||||
SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
|
||||
@ -998,28 +998,28 @@ SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
|
||||
SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
|
||||
SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(3) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
|
||||
SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(2) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout0: FDCPE port map (SlowTimeout(0),SlowTimeout_D(0),FCLK,'0','0');
|
||||
SlowTimeout_D(0) <= ((nPOR AND SlowTimeout(0) AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(8) AND set/SetWRr));
|
||||
SlowTimeout_D(0) <= ((nPOR AND NOT SlowTimeout(0) AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(8) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout1: FDCPE port map (SlowTimeout(1),SlowTimeout_D(1),FCLK,'0','0');
|
||||
SlowTimeout_D(1) <= ((nPOR AND SlowTimeout(1) AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(9) AND set/SetWRr));
|
||||
SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||||
SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||||
SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||||
SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
||||
|
||||
@ -3,13 +3,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Reading design: WarpSE.prj
|
||||
@ -446,15 +446,15 @@ Design Statistics
|
||||
# IOs : 80
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 686
|
||||
# AND2 : 214
|
||||
# BELS : 690
|
||||
# AND2 : 210
|
||||
# AND3 : 26
|
||||
# AND4 : 13
|
||||
# AND5 : 3
|
||||
# AND8 : 2
|
||||
# GND : 7
|
||||
# INV : 273
|
||||
# OR2 : 111
|
||||
# INV : 277
|
||||
# OR2 : 115
|
||||
# OR3 : 10
|
||||
# OR4 : 4
|
||||
# OR5 : 1
|
||||
@ -473,12 +473,12 @@ Cell Usage :
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 5.00 secs
|
||||
Total CPU time to Xst completion: 4.98 secs
|
||||
Total REAL time to Xst completion: 6.00 secs
|
||||
Total CPU time to Xst completion: 5.25 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 262688 kilobytes
|
||||
Total memory usage is 263456 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 3 ( 0 filtered)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
Binary file not shown.
@ -3,7 +3,7 @@
|
||||
|
||||
cpldfit: version P.20131013 Xilinx Inc.
|
||||
Fitter Report
|
||||
Design Name: WarpSE Date: 10-11-2024, 5:42PM
|
||||
Design Name: WarpSE Date: 10-11-2024, 5:45PM
|
||||
Device Used: XC95144XL-10-TQ100
|
||||
Fitting Status: Successful
|
||||
|
||||
@ -984,8 +984,8 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
|
||||
RnW_IOB_OE <= NOT nAoutOE;
|
||||
|
||||
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
|
||||
SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(1) AND set/SetWRr));
|
||||
SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
|
||||
SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
|
||||
@ -1000,28 +1000,28 @@ SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
|
||||
SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
|
||||
SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(3) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
|
||||
SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(2) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout0: FDCPE port map (SlowTimeout(0),SlowTimeout_D(0),FCLK,'0','0');
|
||||
SlowTimeout_D(0) <= ((nPOR AND SlowTimeout(0) AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(8) AND set/SetWRr));
|
||||
SlowTimeout_D(0) <= ((nPOR AND NOT SlowTimeout(0) AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(8) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout1: FDCPE port map (SlowTimeout(1),SlowTimeout_D(1),FCLK,'0','0');
|
||||
SlowTimeout_D(1) <= ((nPOR AND SlowTimeout(1) AND NOT set/SetWRr)
|
||||
OR (nPOR AND A_FSB(9) AND set/SetWRr));
|
||||
SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
|
||||
OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||||
SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||||
SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||||
SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
||||
|
||||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||||
SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
||||
|
||||
@ -218,8 +218,8 @@ FTCPE_RnW_IOB: FTCPE port map (RnW_IOB_I,RnW_IOB_T,NOT C16M,'0','0');
|
||||
<br/> RnW_IOB_OE <= NOT nAoutOE;
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
|
||||
<br/> SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND A_FSB(1) AND set/SetWRr));
|
||||
<br/> SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
|
||||
<br/> SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
|
||||
@ -234,28 +234,28 @@ FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
|
||||
<br/> OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
|
||||
<br/> SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
|
||||
<br/> SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND A_FSB(3) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
|
||||
<br/> SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT A_FSB(2) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowTimeout0: FDCPE port map (SlowTimeout(0),SlowTimeout_D(0),FCLK,'0','0');
|
||||
<br/> SlowTimeout_D(0) <= ((nPOR AND SlowTimeout(0) AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND A_FSB(8) AND set/SetWRr));
|
||||
<br/> SlowTimeout_D(0) <= ((nPOR AND NOT SlowTimeout(0) AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT A_FSB(8) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowTimeout1: FDCPE port map (SlowTimeout(1),SlowTimeout_D(1),FCLK,'0','0');
|
||||
<br/> SlowTimeout_D(1) <= ((nPOR AND SlowTimeout(1) AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND A_FSB(9) AND set/SetWRr));
|
||||
<br/> SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||||
<br/> SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||||
<br/> SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||||
<br/> SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||||
<br/> SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
|
||||
<br/> OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
||||
</td></tr><tr><td>
|
||||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||||
<br/> SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
var design = "WarpSE";
|
||||
var device = "XC95144XL";
|
||||
signals = new Array("ALE0M","ALE0S","ASrf","BACTr","GA22_SPECSIG","GA23_SPECSIG","IOACT","IODONE","IOL0","IONPReady","IOREQ","IORW","IOU0","MCKE","QoSEN","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RAMReady","RefReq","RefUrg","RnW_IOB","SlowClockGate","SlowIACK","SlowIWM","SlowSCC","SlowSCSI","SlowSnd","SlowTimeout0_SPECSIG","SlowTimeout1_SPECSIG","SlowTimeout2_SPECSIG","SlowTimeout3_SPECSIG","SlowVIA","cntC8Mr0_SPECSIG","cntC8Mr1_SPECSIG","cntC8Mr2_SPECSIG","cntC8Mr3_SPECSIG","cntEr0_SPECSIG","cntEr1_SPECSIG","cntIS0_SPECSIG","cntIS1_SPECSIG","cntLTimer0_SPECSIG","cntLTimer10_SPECSIG","cntLTimer11_SPECSIG","cntLTimer1_SPECSIG","cntLTimer2_SPECSIG","cntLTimer3_SPECSIG","cntLTimer4_SPECSIG","cntLTimer5_SPECSIG","cntLTimer6_SPECSIG","cntLTimer7_SPECSIG","cntLTimer8_SPECSIG","cntLTimer9_SPECSIG","cntLTimerTick_SPECSIG","cntQS0_SPECSIG","cntQS1_SPECSIG","cntQS2_SPECSIG","cntQS3_SPECSIG","cntQoSCSr_SPECSIG","cntTimer0_SPECSIG","cntTimer1_SPECSIG","cntTimer2_SPECSIG","cntTimer3_SPECSIG","cntTimerTick_SPECSIG","csOverlay_SPECSIG","iobmC8Mr_SPECSIG","iobmDoutOE_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmIOS_FSM_FFd5_SPECSIG","iobmIOS_FSM_FFd6_SPECSIG","iobmIOS_FSM_FFd7_SPECSIG","iobmVPAr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIODONEr0_SPECSIG","iobsIODONEr1_SPECSIG","iobsIODONErf_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsSent_SPECSIG","iobsTS_FSM_FFd1_SPECSIG","iobsTS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nBR_IOB","nBR_IOBout","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nPOR","nRAMLWE","nRAMUWE","nRAS","nRES","nRESout","nROMOE","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramCASEndEN_SPECSIG","ramRASEL_SPECSIG","ramRASEN_SPECSIG","ramRASrf_SPECSIG","ramRS0_SPECSIG","ramRS1_SPECSIG","ramRS2_SPECSIG","ramRefCAS_SPECSIG","ramRefDone_SPECSIG","setSetWRr_SPECSIG");
|
||||
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
|
||||
sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","ON","ON","ON","OFF","ON","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
|
||||
sigTypes = new Array("D","D","D","D","","","D","D","D","D","D","D","D","D","D","","","","","","","","","","","","","D","D","D","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","T","T","T","T","T","T","T","T","T","T","T","T","D","D","D","T","D","D","T","T","T","T","D","T","D","D","T","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","D","T","D","D","","D","D","D","T","","D","D","D","D","","","D","D","T","","","","","D","","","D","T","D","D","D","D","D","D","T","T","D","D","D");
|
||||
|
||||
|
||||
@ -264,21 +264,21 @@
|
||||
|
||||
pterms["FB1_9_2"]=new Array("cntTimerTick_SPECSIG");
|
||||
|
||||
pterms["FB1_10_1"]=new Array("nPOR","SlowTimeout1_SPECSIG","/setSetWRr_SPECSIG");
|
||||
pterms["FB1_10_1"]=new Array("nPOR","/SlowTimeout1_SPECSIG","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_10_2"]=new Array("nPOR","A_FSB9_SPECSIG","setSetWRr_SPECSIG");
|
||||
pterms["FB1_10_2"]=new Array("nPOR","/A_FSB9_SPECSIG","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_11_1"]=new Array("nPOR","SlowTimeout0_SPECSIG","/setSetWRr_SPECSIG");
|
||||
pterms["FB1_11_1"]=new Array("nPOR","/SlowTimeout0_SPECSIG","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_11_2"]=new Array("nPOR","A_FSB8_SPECSIG","setSetWRr_SPECSIG");
|
||||
pterms["FB1_11_2"]=new Array("nPOR","/A_FSB8_SPECSIG","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_12_1"]=new Array("nPOR","/SlowSnd","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_12_2"]=new Array("nPOR","/A_FSB2_SPECSIG","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_13_1"]=new Array("nPOR","/SlowSCSI","/setSetWRr_SPECSIG");
|
||||
pterms["FB1_13_1"]=new Array("nPOR","SlowSCSI","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_13_2"]=new Array("nPOR","/A_FSB3_SPECSIG","setSetWRr_SPECSIG");
|
||||
pterms["FB1_13_2"]=new Array("nPOR","A_FSB3_SPECSIG","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_14_1"]=new Array("nPOR","/SlowSCC","/setSetWRr_SPECSIG");
|
||||
|
||||
@ -292,9 +292,9 @@
|
||||
|
||||
pterms["FB1_16_2"]=new Array("nPOR","/A_FSB7_SPECSIG","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_17_1"]=new Array("nPOR","SlowClockGate","/setSetWRr_SPECSIG");
|
||||
pterms["FB1_17_1"]=new Array("nPOR","/SlowClockGate","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_17_2"]=new Array("nPOR","A_FSB1_SPECSIG","setSetWRr_SPECSIG");
|
||||
pterms["FB1_17_2"]=new Array("nPOR","/A_FSB1_SPECSIG","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB1_18_1"]=new Array("/nPOR","/cntC8Mr1_SPECSIG","cntC8Mr0_SPECSIG");
|
||||
|
||||
@ -460,13 +460,13 @@
|
||||
|
||||
pterms["FB4_11_2"]=new Array("nAS_FSB");
|
||||
|
||||
pterms["FB4_12_1"]=new Array("A_FSB11_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
pterms["FB4_12_1"]=new Array("/A_FSB11_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_12_2"]=new Array("nPOR","SlowTimeout3_SPECSIG","/setSetWRr_SPECSIG");
|
||||
pterms["FB4_12_2"]=new Array("nPOR","/SlowTimeout3_SPECSIG","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_13_1"]=new Array("A_FSB10_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
pterms["FB4_13_1"]=new Array("/A_FSB10_SPECSIG","nPOR","setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_13_2"]=new Array("nPOR","SlowTimeout2_SPECSIG","/setSetWRr_SPECSIG");
|
||||
pterms["FB4_13_2"]=new Array("nPOR","/SlowTimeout2_SPECSIG","/setSetWRr_SPECSIG");
|
||||
|
||||
pterms["FB4_14_1"]=new Array("/cntTimer1_SPECSIG","/cntTimer2_SPECSIG","cntTimer3_SPECSIG");
|
||||
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
<tr>
|
||||
<td width="40%"> <b>Date</b>
|
||||
</td>
|
||||
<td width="60%"> 10-11-2024, 5:42PM</td>
|
||||
<td width="60%"> 10-11-2024, 5:45PM</td>
|
||||
</tr>
|
||||
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
|
||||
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
<TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC95144XL</A>, -10 (3.0)</TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Fri Oct 11 17:42:31 2024
|
||||
<TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Fri Oct 11 17:45:49 2024
|
||||
</TD>
|
||||
</TR>
|
||||
<TR>
|
||||
@ -3882,7 +3882,7 @@ function AUTO_TS_F2P_BACTr_Q_to_nDinOE() {
|
||||
<SPAN CLASS="cpldta_text_normal">809</SPAN>
|
||||
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of Timing errors:</B></SPAN>
|
||||
<SPAN CLASS="cpldta_text_normal">809</SPAN>
|
||||
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Fri Oct 11 17:42:31 2024
|
||||
<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Fri Oct 11 17:45:49 2024
|
||||
</SPAN>
|
||||
<HR>
|
||||
</HTML>
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Fri Oct 11 17:42:03 2024">
|
||||
<application stringID="NgdBuild" timeStamp="Fri Oct 11 17:45:20 2024">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -66,7 +66,7 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="214"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="210"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
|
||||
@ -76,24 +76,24 @@
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="273"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="277"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="111"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="115"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="21"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="214"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="210"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="72"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="43"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="273"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="277"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="111"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="115"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
10-11-2024 5:42PM
|
||||
10-11-2024 5:45PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/11/2024 - 17:42:47)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/11/2024 - 17:45:58)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>WarpSE.xise</TD>
|
||||
@ -65,9 +65,9 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Oct 11 17:41:58 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Oct 11 17:42:03 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Fri Oct 11 17:42:24 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Oct 11 17:45:15 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Oct 11 17:45:20 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Fri Oct 11 17:45:41 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
@ -77,5 +77,5 @@ System Settings</A>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 10/11/2024 - 17:42:47</center>
|
||||
<br><center><b>Date Generated:</b> 10/11/2024 - 17:45:58</center>
|
||||
</BODY></HTML>
|
||||
@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Fri Oct 11 17:41:53 2024">
|
||||
<application stringID="Xst" timeStamp="Fri Oct 11 17:45:10 2024">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@ -118,13 +118,13 @@
|
||||
<item stringID="XST_IOS" value="80"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="686">
|
||||
<item dataType="int" stringID="XST_AND2" value="214"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="690">
|
||||
<item dataType="int" stringID="XST_AND2" value="210"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="26"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="13"/>
|
||||
<item dataType="int" stringID="XST_GND" value="7"/>
|
||||
<item dataType="int" stringID="XST_INV" value="273"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="111"/>
|
||||
<item dataType="int" stringID="XST_INV" value="277"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="115"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="21"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="113">
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728682918
|
||||
C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728683115
|
||||
OK
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2024-10-11T17:41:33</DateModified>
|
||||
<DateModified>2024-10-11T17:44:47</DateModified>
|
||||
<ModuleName>WarpSE</ModuleName>
|
||||
<SummaryTimeStamp>2024-10-09T06:57:43</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
|
||||
<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">4df80768333d4ba791d1d537de27744e</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">ffc5ddfd26c840d298216ab3e9bb5edf</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
|
||||
<TD><xtag-property name="TargetPackage"></xtag-property></TD>
|
||||
</TR>
|
||||
@ -29,7 +29,7 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
|
||||
<TD><xtag-property name="Date Generated">2024-10-11T17:43:43</xtag-property></TD>
|
||||
<TD><xtag-property name="Date Generated">2024-10-11T17:46:36</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
|
||||
<TD><xtag-property name="ToolFlow">IMPACT</xtag-property></TD>
|
||||
</TR>
|
||||
|
||||
@ -3,7 +3,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Project Information
|
||||
--------------------
|
||||
ProjectID=4df80768333d4ba791d1d537de27744e
|
||||
ProjectID=ffc5ddfd26c840d298216ab3e9bb5edf
|
||||
ProjectIteration=1
|
||||
|
||||
WebTalk Summary
|
||||
|
||||
@ -3,9 +3,9 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="impact" timeStamp="Fri Oct 11 17:43:42 2024">
|
||||
<application name="impact" timeStamp="Fri Oct 11 17:46:36 2024">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="4df80768333d4ba791d1d537de27744e"/>
|
||||
<property name="ProjectID" value="ffc5ddfd26c840d298216ab3e9bb5edf"/>
|
||||
<property name="ProjectIteration" value="1"/>
|
||||
</section>
|
||||
<section name="iMPACT Project Info" visible="true">
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Fri Oct 11 17:41:52 2024">
|
||||
<application name="pn" timeStamp="Fri Oct 11 17:45:09 2024">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="B70E14F6F6B943E9BF9FD5113EA04D70" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
||||
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728682913
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1728682913
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728682913
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728682913
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728682913
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728682913
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728682913
|
||||
MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728682913
|
||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728683110
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1728683110
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728683110
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728683110
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728683110
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728683110
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728683110
|
||||
MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728683110
|
||||
|
||||
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Loading…
Reference in New Issue
Block a user