mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-28 20:52:22 +00:00
834 lines
59 KiB
HTML
834 lines
59 KiB
HTML
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
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<h3 align='center'>Equations</h3>
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<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
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<tr><td>
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</td></tr><tr><td>
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********** Mapped Logic **********
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</td></tr><tr><td>
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FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
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<br/> ALE0M_D <= ((NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
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<br/> NOT iobm/IOS_FSM_FFd6)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> iobm/IOS_FSM_FFd2)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> iobm/IOS_FSM_FFd1)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M));
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</td></tr><tr><td>
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FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0');
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</td></tr><tr><td>
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FDCPE_ASrf: FDCPE port map (ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
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</td></tr><tr><td>
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FDCPE_BACTr: FDCPE port map (BACTr,BACTr_D,FCLK,'0','0');
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<br/> BACTr_D <= (nAS_FSB AND NOT ASrf);
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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GA(22) <= A_FSB(22);
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</td></tr><tr><td>
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</td></tr><tr><td>
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GA(23) <= A_FSB(23);
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</td></tr><tr><td>
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FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
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<br/> IOACT_D <= ((IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND
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<br/> NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
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<br/> NOT iobm/IOS_FSM_FFd6)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
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<br/> NOT iobm/IOS_FSM_FFd6)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT IOACT)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> iobm/IOS_FSM_FFd2)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> iobm/IOS_FSM_FFd1)
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<br/> OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
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<br/> NOT iobm/IOS_FSM_FFd6));
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</td></tr><tr><td>
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FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,C16M,'0','0');
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<br/> IODONE_D <= ((NOT nVMA_IOB AND NOT iobm/C8Mr AND NOT iobm/ES(0) AND
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<br/> iobm/IOS_FSM_FFd5 AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND iobm/ES(3))
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<br/> OR (IODONE AND NOT iobm/IOS_FSM_FFd7 AND iobm/C8Mr)
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<br/> OR (NOT nBERR_IOB AND NOT iobm/C8Mr AND iobm/IOS_FSM_FFd5)
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<br/> OR (IODONE AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd5)
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<br/> OR (NOT nVMA_IOB AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND
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<br/> NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND iobm/ES(3))
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<br/> OR (NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)
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<br/> OR (iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND NOT nRES.PIN)
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<br/> OR (iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND NOT nDTACK_IOB)
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<br/> OR (NOT iobm/C8Mr AND iobm/IOS_FSM_FFd5 AND NOT nRES.PIN)
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<br/> OR (NOT iobm/C8Mr AND iobm/IOS_FSM_FFd5 AND NOT nDTACK_IOB));
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</td></tr><tr><td>
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FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,FCLK,'0','0');
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<br/> IOL0_D <= ((iobs/TS_FSM_FFd1 AND IOL0)
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<br/> OR (NOT nLDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1)
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<br/> OR (iobs/IOL1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1));
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</td></tr><tr><td>
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FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
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<br/> IONPReady_D <= ((nAS_FSB AND NOT ASrf)
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<br/> OR (NOT iobs/Sent AND NOT IONPReady)
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<br/> OR (NOT IONPReady AND NOT iobs/IODONEr(0))
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<br/> OR (NOT IONPReady AND iobs/IODONEr(1))
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<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
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<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT IONPReady AND NOT nWE_FSB));
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</td></tr><tr><td>
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FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,FCLK,'0','0');
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<br/> IOREQ_D <= ((NOT A_FSB(21) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND nWE_FSB AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (NOT A_FSB(19) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (NOT A_FSB(18) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (NOT A_FSB(17) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (NOT A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
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<br/> OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
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<br/> OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
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<br/> OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT ASrf AND nADoutLE1)
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<br/> OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
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<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
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</td></tr><tr><td>
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FDCPE_IORW: FDCPE port map (IORW,IORW_D,FCLK,'0','0',IORW_CE);
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<br/> IORW_D <= ((nWE_FSB AND nADoutLE1)
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<br/> OR (iobs/IORW1 AND NOT nADoutLE1));
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<br/> IORW_CE <= (NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2);
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</td></tr><tr><td>
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FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,FCLK,'0','0');
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<br/> IOU0_D <= ((iobs/TS_FSM_FFd1 AND IOU0)
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<br/> OR (NOT nUDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1)
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<br/> OR (iobs/IOU1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1));
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</td></tr><tr><td>
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FDCPE_MCKE: FDCPE port map (MCKE,MCKE_D,NOT FCLK,'0',NOT nAS_FSB);
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<br/> MCKE_D <= ((QoSEN AND SlowClockGate AND NOT cnt/C8Mr(1) AND NOT ASrf)
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<br/> OR (QoSEN AND SlowClockGate AND cnt/C8Mr(0) AND NOT ASrf));
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</td></tr><tr><td>
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FDCPE_QoSEN: FDCPE port map (QoSEN,QoSEN_D,FCLK,'0','0',QoSEN_CE);
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<br/> QoSEN_D <= ((NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
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<br/> SlowTimeout(0))
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<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
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<br/> SlowTimeout(1))
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<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
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<br/> SlowTimeout(2))
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<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
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<br/> SlowTimeout(3)));
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<br/> QoSEN_CE <= (nAS_FSB AND NOT ASrf);
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(0) <= ((ram/RASEL AND A_FSB(1))
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<br/> OR (NOT ram/RASEL AND A_FSB(9)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(1) <= ((A_FSB(10) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(2)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(2) <= ((A_FSB(16) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(7)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(3) <= ((A_FSB(20) AND ram/RASEL)
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<br/> OR (A_FSB(19) AND NOT ram/RASEL));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(4) <= ((A_FSB(11) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(3)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(5) <= ((A_FSB(12) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(4)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(6) <= ((A_FSB(13) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(5)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(7) <= ((A_FSB(14) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(6)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(8) <= ((A_FSB(21) AND ram/RASEL)
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<br/> OR (A_FSB(18) AND NOT ram/RASEL));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(9) <= ((A_FSB(15) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(8)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(10) <= ((A_FSB(17) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(7)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(11) <= ((A_FSB(20) AND ram/RASEL)
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<br/> OR (A_FSB(19) AND NOT ram/RASEL));
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</td></tr><tr><td>
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FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
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<br/> RAMReady_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))
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<br/> OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
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<br/> OR (nAS_FSB AND NOT RefUrg AND NOT ram/RS(2) AND NOT ASrf)
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<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT ram/RS(0) AND
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<br/> NOT ram/RS(2))
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<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/RS(0) AND NOT ram/RS(2) AND
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<br/> ASrf)
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<br/> OR (ram/RefDone AND NOT ram/RS(2))
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<br/> OR (NOT RefReq AND NOT RefUrg AND NOT ram/RS(2))
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<br/> OR (NOT RefUrg AND ram/RS(0) AND NOT ram/RS(2))
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<br/> OR (NOT RefUrg AND NOT ram/RS(2) AND BACTr)
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<br/> OR (ram/RS(1) AND ram/RS(0) AND ram/RS(2)));
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</td></tr><tr><td>
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FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
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<br/> RefReq_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
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<br/> cnt/Timer(3));
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<br/> RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FDCPE_RefUrg: FDCPE port map (RefUrg,RefUrg_D,FCLK,'0','0',RefUrg_CE);
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<br/> RefUrg_D <= (NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3));
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<br/> RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_RnW_IOB: FTCPE port map (RnW_IOB_I,RnW_IOB_T,NOT C16M,'0','0');
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<br/> RnW_IOB_T <= ((NOT RnW_IOB AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> NOT iobm/IOS_FSM_FFd2)
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<br/> OR (RnW_IOB AND NOT IORW AND iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND
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<br/> iobm/IOREQr)
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<br/> OR (NOT RnW_IOB AND IORW AND NOT iobm/IOS_FSM_FFd3 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> NOT iobm/IOS_FSM_FFd2)
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<br/> OR (NOT RnW_IOB AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> NOT iobm/IOS_FSM_FFd2)
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<br/> OR (NOT RnW_IOB AND NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
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<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
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<br/> NOT iobm/IOS_FSM_FFd2));
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<br/> RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
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<br/> RnW_IOB_OE <= NOT nAoutOE;
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</td></tr><tr><td>
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FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
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<br/> SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
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<br/> SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(7) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowIWM: FDCPE port map (SlowIWM,SlowIWM_D,FCLK,'0','0');
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<br/> SlowIWM_D <= ((nPOR AND NOT SlowIWM AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(5) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
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<br/> SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
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<br/> SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
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<br/> OR (nPOR AND A_FSB(3) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
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<br/> SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(2) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowTimeout0: FDCPE port map (SlowTimeout(0),SlowTimeout_D(0),FCLK,'0','0');
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<br/> SlowTimeout_D(0) <= ((nPOR AND NOT SlowTimeout(0) AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(8) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowTimeout1: FDCPE port map (SlowTimeout(1),SlowTimeout_D(1),FCLK,'0','0');
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<br/> SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
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<br/> OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
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</td></tr><tr><td>
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FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
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<br/> SlowTimeout_D(2) <= ((NOT A_FSB(10) AND nPOR AND set/SetWRr)
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<br/> OR (nPOR AND NOT SlowTimeout(2) AND NOT set/SetWRr));
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</td></tr><tr><td>
|
|
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
|
<br/> SlowTimeout_D(3) <= ((NOT A_FSB(11) AND nPOR AND set/SetWRr)
|
|
<br/> OR (nPOR AND NOT SlowTimeout(3) AND NOT set/SetWRr));
|
|
</td></tr><tr><td>
|
|
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
|
<br/> SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
|
<br/> OR (nPOR AND NOT A_FSB(6) AND set/SetWRr));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/C8Mr0: FDCPE port map (cnt/C8Mr(0),C8M,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/C8Mr1: FDCPE port map (cnt/C8Mr(1),cnt/C8Mr(0),FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/C8Mr2: FDCPE port map (cnt/C8Mr(2),cnt/C8Mr(1),FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/C8Mr3: FDCPE port map (cnt/C8Mr(3),cnt/C8Mr(2),FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/IS0: FTCPE port map (cnt/IS(0),cnt/IS_T(0),FCLK,'0','0');
|
|
<br/> cnt/IS_T(0) <= ((NOT nPOR AND cnt/IS(0))
|
|
<br/> OR (nPOR AND NOT cnt/IS(1) AND cnt/LTimerTick)
|
|
<br/> OR (nPOR AND NOT cnt/IS(0) AND cnt/LTimerTick AND nIPL2));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/IS1: FDCPE port map (cnt/IS(1),cnt/IS_D(1),FCLK,'0','0');
|
|
<br/> cnt/IS_D(1) <= ((nPOR AND cnt/IS(1))
|
|
<br/> OR (nPOR AND cnt/IS(0) AND cnt/LTimerTick));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/TimerTick);
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/TimerTick);
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
<br/> cnt/LTimer(7));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
<br/> cnt/LTimer(7) AND cnt/LTimer(8));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
<br/> cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/TimerTick);
|
|
<br/> cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
|
<br/> cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
|
<br/> cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/LTimerTick: FDCPE port map (cnt/LTimerTick,cnt/LTimerTick_D,FCLK,'0','0');
|
|
<br/> cnt/LTimerTick_D <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
|
<br/> cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
|
<br/> cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
|
|
<br/> cnt/LTimer(11) AND cnt/TimerTick);
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/QS0: FDCPE port map (cnt/QS(0),cnt/QS_D(0),FCLK,'0','0');
|
|
<br/> cnt/QS_D(0) <= ((cnt/QS(0) AND cnt/TimerTick AND NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(0) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
|
<br/> NOT cnt/QoSCSr));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/QS1: FDCPE port map (cnt/QS(1),cnt/QS_D(1),FCLK,'0','0');
|
|
<br/> cnt/QS_D(1) <= ((cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(1) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(0) AND cnt/QS(1) AND cnt/TimerTick AND
|
|
<br/> NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND NOT cnt/QoSCSr));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/QS2: FTCPE port map (cnt/QS(2),cnt/QS_T(2),FCLK,'0','0');
|
|
<br/> cnt/QS_T(2) <= ((NOT cnt/QS(2) AND cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND cnt/QS(2) AND
|
|
<br/> cnt/TimerTick AND NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND cnt/QS(3) AND
|
|
<br/> cnt/TimerTick));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/QS3: FDCPE port map (cnt/QS(3),cnt/QS_D(3),FCLK,'0','0');
|
|
<br/> cnt/QS_D(3) <= ((NOT cnt/QS(3) AND NOT cnt/QoSCSr)
|
|
<br/> OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND
|
|
<br/> cnt/TimerTick AND NOT cnt/QoSCSr));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/QoSCSr: FDCPE port map (cnt/QoSCSr,cnt/QoSCSr_D,FCLK,'0','0');
|
|
<br/> cnt/QoSCSr_D <= ((NOT nRES.PIN)
|
|
<br/> OR (NOT A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND SlowIWM)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
|
<br/> NOT A_FSB(22) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
|
<br/> NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(9))
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
|
<br/> NOT A_FSB(22) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
|
<br/> NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(8))
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
|
<br/> NOT A_FSB(22) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
|
<br/> NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(9))
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
|
<br/> NOT A_FSB(22) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
|
<br/> NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(8))
|
|
<br/> OR (A_FSB(20) AND A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
|
<br/> SlowSCC)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND SlowIACK)
|
|
<br/> OR (A_FSB(21) AND NOT A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND SlowVIA)
|
|
<br/> OR (NOT A_FSB(21) AND A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND SlowSCSI));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
|
|
<br/> cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
|
<br/> cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
<br/> cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/Timer1: FTCPE port map (cnt/Timer(1),cnt/Timer_T(1),FCLK,'0','0',cnt/Timer_CE(1));
|
|
<br/> cnt/Timer_T(1) <= ((cnt/Timer(0))
|
|
<br/> OR (cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3) AND
|
|
<br/> NOT cnt/Er(0) AND cnt/Er(1)));
|
|
<br/> cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/Timer2: FTCPE port map (cnt/Timer(2),cnt/Timer_T(2),FCLK,'0','0',cnt/Timer_CE(2));
|
|
<br/> cnt/Timer_T(2) <= (cnt/Timer(0) AND cnt/Timer(1));
|
|
<br/> cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/Timer3: FTCPE port map (cnt/Timer(3),cnt/Timer_T(3),FCLK,'0','0',cnt/Timer_CE(3));
|
|
<br/> cnt/Timer_T(3) <= ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
|
|
<br/> OR (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
|
<br/> cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1)));
|
|
<br/> cnt/Timer_CE(3) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/TimerTick: FDCPE port map (cnt/TimerTick,cnt/TimerTick_D,FCLK,'0','0');
|
|
<br/> cnt/TimerTick_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
|
<br/> cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cs/Overlay: FTCPE port map (cs/Overlay,cs/Overlay_T,FCLK,'0','0');
|
|
<br/> cs/Overlay_T <= ((nAS_FSB AND NOT cs/Overlay AND NOT nRES.PIN AND NOT ASrf)
|
|
<br/> OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND cs/Overlay)
|
|
<br/> OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
|
<br/> cs/Overlay AND ASrf));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/DoutOE: FDCPE port map (iobm/DoutOE,iobm/DoutOE_D,C16M,'0','0');
|
|
<br/> iobm/DoutOE_D <= ((iobm/IOS_FSM_FFd3 AND iobm/DoutOE)
|
|
<br/> OR (iobm/IOS_FSM_FFd4 AND iobm/DoutOE)
|
|
<br/> OR (iobm/IOS_FSM_FFd5 AND iobm/DoutOE)
|
|
<br/> OR (iobm/IOS_FSM_FFd6 AND iobm/DoutOE)
|
|
<br/> OR (NOT IORW AND iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND
|
|
<br/> iobm/IOREQr));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
|
|
<br/> iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er)
|
|
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND E)
|
|
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND NOT iobm/Er));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
|
|
<br/> iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
|
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
|
<br/> OR (NOT E AND iobm/Er)
|
|
<br/> OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3)));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
|
|
<br/> iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er)
|
|
<br/> OR (iobm/ES(2) AND NOT E AND iobm/Er));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
|
|
<br/> iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND E)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er)
|
|
<br/> OR (iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> iobm/ES(3)));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd2_D <= (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr);
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd3_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4)
|
|
<br/> OR (IODONE AND NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd6_D <= (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOREQr AND
|
|
<br/> NOT nAoutOE);
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1)
|
|
<br/> OR (NOT iobm/C8Mr AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1 AND
|
|
<br/> NOT nAoutOE));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
|
|
<br/> iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2);
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IODONEr0: FDCPE port map (iobs/IODONEr(0),iobs/IODONErf,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IODONEr1: FDCPE port map (iobs/IODONEr(1),iobs/IODONEr(0),FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IODONErf: FDCPE port map (iobs/IODONErf,IODONE,NOT FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
</td></tr><tr><td>
|
|
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
|
|
<br/> iobs/IORW1_T <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND
|
|
<br/> nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
|
|
<br/> nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND ASrf AND
|
|
<br/> nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND ASrf AND
|
|
<br/> nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
|
|
<br/> iobs/Load1_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND ASrf AND nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobs/Sent: FTCPE port map (iobs/Sent,iobs/Sent_T,FCLK,'0','0');
|
|
<br/> iobs/Sent_T <= ((A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND NOT iobs/Sent AND
|
|
<br/> NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND NOT iobs/Sent AND
|
|
<br/> NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND nADoutLE1)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
|
<br/> NOT QoSEN AND NOT nWE_FSB AND ASrf AND nADoutLE1)
|
|
<br/> OR (nAS_FSB AND iobs/Sent AND NOT ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND
|
|
<br/> NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (A_FSB(23) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1)
|
|
<br/> OR (NOT nAS_FSB AND NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
|
|
<br/> iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2)
|
|
<br/> OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0');
|
|
<br/> iobs/TS_FSM_FFd2_D <= ((NOT A_FSB(19) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(18) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(17) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(21) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(20) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND nWE_FSB AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
|
<br/> OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
|
|
<br/> OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
<br/> OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT ASrf AND nADoutLE1)
|
|
<br/> OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
|
<br/> NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
|
</td></tr><tr><td>
|
|
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
|
|
<br/> nADoutLE1_D <= ((iobs/Load1)
|
|
<br/> OR (NOT iobs/Clear1 AND NOT nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
|
|
<br/> nAS_IOB <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
|
<br/> nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
|
|
<br/> nAS_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
|
|
<br/> nAoutOE_D <= (cnt/IS(1) AND cnt/IS(0) AND NOT nBR_IOBout);
|
|
</td></tr><tr><td>
|
|
FTCPE_nBERR_FSB: FTCPE port map (nBERR_FSB,nBERR_FSB_T,FCLK,'0','0');
|
|
<br/> nBERR_FSB_T <= ((nAS_FSB AND NOT nBERR_FSB AND NOT ASrf)
|
|
<br/> OR (NOT nAS_FSB AND iobs/Sent AND NOT nBERR_IOB AND nBERR_FSB AND
|
|
<br/> iobs/IODONEr(0) AND NOT iobs/IODONEr(1))
|
|
<br/> OR (iobs/Sent AND NOT nBERR_IOB AND nBERR_FSB AND
|
|
<br/> iobs/IODONEr(0) AND ASrf AND NOT iobs/IODONEr(1)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nBR_IOB_I <= '0';
|
|
<br/> nBR_IOB <= nBR_IOB_I when nBR_IOB_OE = '1' else 'Z';
|
|
<br/> nBR_IOB_OE <= NOT nBR_IOBout;
|
|
</td></tr><tr><td>
|
|
FDCPE_nBR_IOBout: FDCPE port map (nBR_IOBout,nBR_IOBout_D,FCLK,'0','0');
|
|
<br/> nBR_IOBout_D <= ((cnt/IS(1) AND nBR_IOBout)
|
|
<br/> OR (cnt/IS(1) AND NOT cnt/IS(0) AND NOT nIPL2));
|
|
</td></tr><tr><td>
|
|
FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,ram/RefCAS,nCAS_PRE);
|
|
<br/> nCAS_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (NOT ram/RS(1) AND NOT ram/RS(0) AND ram/RS(2)));
|
|
<br/> nCAS_PRE <= (nAS_FSB AND ram/CASEndEN);
|
|
</td></tr><tr><td>
|
|
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0',nAS_FSB);
|
|
<br/> nDTACK_FSB_D <= ((NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22))
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT IONPReady AND NOT nWE_FSB AND
|
|
<br/> NOT nADoutLE1)
|
|
<br/> OR (A_FSB(23) AND NOT IONPReady)
|
|
<br/> OR (QoSEN AND NOT IONPReady)
|
|
<br/> OR (A_FSB(21) AND A_FSB(22) AND NOT IONPReady)
|
|
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT IONPReady));
|
|
</td></tr><tr><td>
|
|
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
|
|
<br/> nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nDinOE <= NOT (((A_FSB(23) AND NOT nAS_FSB AND nWE_FSB AND BACTr)
|
|
<br/> OR (A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND nWE_FSB AND
|
|
<br/> BACTr)
|
|
<br/> OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND nWE_FSB AND
|
|
<br/> BACTr)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nDoutOE <= NOT ((iobm/DoutOE AND NOT nAoutOE));
|
|
</td></tr><tr><td>
|
|
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
|
|
<br/> nLDS_IOB <= ((NOT IOL0)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
|
<br/> nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
|
|
<br/> nLDS_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
FDCPE_nOE: FDCPE port map (nOE,nOE_D,FCLK,'0',nAS_FSB);
|
|
<br/> nOE_D <= (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/Overlay AND nWE_FSB);
|
|
</td></tr><tr><td>
|
|
FTCPE_nPOR: FTCPE port map (nPOR,nPOR_T,FCLK,'0','0');
|
|
<br/> nPOR_T <= ((NOT nPOR AND NOT cnt/C8Mr(1) AND cnt/C8Mr(0))
|
|
<br/> OR (nPOR AND cnt/C8Mr(1) AND cnt/C8Mr(0) AND cnt/C8Mr(2) AND
|
|
<br/> cnt/C8Mr(3))
|
|
<br/> OR (nPOR AND NOT cnt/C8Mr(1) AND NOT cnt/C8Mr(0) AND NOT cnt/C8Mr(2) AND
|
|
<br/> NOT cnt/C8Mr(3)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRAMLWE <= NOT ((NOT nLDS_FSB AND NOT nWE_FSB AND ram/RASEL));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRAS <= NOT (((ram/RASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT cs/Overlay AND
|
|
<br/> ram/RASEN)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRES_I <= '0';
|
|
<br/> nRES <= nRES_I when nRES_OE = '1' else 'Z';
|
|
<br/> nRES_OE <= NOT nRESout;
|
|
</td></tr><tr><td>
|
|
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
|
|
<br/> nRESout_D <= ((cnt/IS(1) AND cnt/IS(0) AND cnt/LTimerTick)
|
|
<br/> OR (cnt/IS(1) AND cnt/IS(0) AND nRESout));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nROMOE <= NOT (((NOT nAS_FSB AND cs/Overlay AND nWE_FSB)
|
|
<br/> OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND nWE_FSB)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nROMWE <= NOT ((NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
|
<br/> NOT nAS_FSB AND NOT nWE_FSB));
|
|
</td></tr><tr><td>
|
|
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
|
|
<br/> nUDS_IOB <= ((NOT IOU0)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
<br/> NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
|
<br/> nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
|
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<br/> nUDS_IOB_OE <= NOT nAoutOE;
|
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</td></tr><tr><td>
|
|
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,NOT C8M,'0','0');
|
|
<br/> nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3))
|
|
<br/> OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND IOACT AND iobm/VPAr));
|
|
<br/> nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
|
|
<br/> nVMA_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
|
|
<br/> nVPA_FSB_D <= (A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
|
<br/> IONPReady);
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/CASEndEN: FDCPE port map (ram/CASEndEN,ram/CASEndEN_D,NOT FCLK,'0','0');
|
|
<br/> ram/CASEndEN_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2)));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
|
|
<br/> ram/RASEL_D <= ((NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT cs/Overlay AND
|
|
<br/> NOT ram/RS(1) AND NOT ram/RS(2))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/Overlay AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(2) AND ASrf));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RASEN: FDCPE port map (ram/RASEN,ram/RASEN_D,FCLK,'0','0');
|
|
<br/> ram/RASEN_D <= ((NOT RefReq AND NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND
|
|
<br/> NOT ram/RS(2))
|
|
<br/> OR (NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND
|
|
<br/> BACTr)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/RS(1) AND NOT ram/RS(0) AND
|
|
<br/> NOT ram/RS(2) AND ASrf)
|
|
<br/> OR (nAS_FSB AND NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND
|
|
<br/> NOT ram/RS(2) AND NOT ASrf)
|
|
<br/> OR (NOT RefUrg AND ram/RS(1) AND ram/RS(0))
|
|
<br/> OR (ram/RefDone AND ram/RS(1) AND ram/RS(0))
|
|
<br/> OR (ram/RS(1) AND ram/RS(0) AND ram/RS(2))
|
|
<br/> OR (nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RASrf_D,NOT FCLK,'0','0');
|
|
<br/> ram/RASrf_D <= ((NOT ram/RS(1) AND ram/RS(0))
|
|
<br/> OR (NOT ram/RS(1) AND ram/RS(2)));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RS0: FDCPE port map (ram/RS(0),ram/RS_D(0),FCLK,'0','0');
|
|
<br/> ram/RS_D(0) <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/Overlay AND NOT ram/RS(0) AND
|
|
<br/> ram/RASEN AND ASrf)
|
|
<br/> OR (ram/RS(1) AND NOT ram/RS(0))
|
|
<br/> OR (NOT ram/RS(0) AND ram/RS(2))
|
|
<br/> OR (NOT nAS_FSB AND nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND
|
|
<br/> NOT ram/RS(2))
|
|
<br/> OR (nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2) AND
|
|
<br/> ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT cs/Overlay AND
|
|
<br/> NOT ram/RS(0) AND ram/RASEN));
|
|
</td></tr><tr><td>
|
|
FTCPE_ram/RS1: FTCPE port map (ram/RS(1),ram/RS_T(1),FCLK,'0','0');
|
|
<br/> ram/RS_T(1) <= ((NOT ram/RS(0))
|
|
<br/> OR (NOT nAS_FSB AND nDTACK_FSB AND NOT ram/RS(1) AND NOT ram/RS(2))
|
|
<br/> OR (nDTACK_FSB AND NOT ram/RS(1) AND NOT ram/RS(2) AND ASrf));
|
|
</td></tr><tr><td>
|
|
FTCPE_ram/RS2: FTCPE port map (ram/RS(2),ram/RS_T(2),FCLK,'0','0');
|
|
<br/> ram/RS_T(2) <= ((ram/RS(1) AND ram/RS(0) AND ram/RS(2))
|
|
<br/> OR (RefUrg AND NOT ram/RefDone AND ram/RS(1) AND ram/RS(0))
|
|
<br/> OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
|
<br/> OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
|
<br/> OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (nAS_FSB AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2) AND NOT ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
|
<br/> NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr)
|
|
<br/> OR (A_FSB(22) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
|
<br/> NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefCAS: FDCPE port map (ram/RefCAS,ram/RefCAS_D,FCLK,'0','0');
|
|
<br/> ram/RefCAS_D <= ((A_FSB(23) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
|
<br/> NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr)
|
|
<br/> OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
|
<br/> OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
|
<br/> OR (RefUrg AND NOT ram/RefDone AND ram/RS(1) AND ram/RS(0) AND
|
|
<br/> NOT ram/RS(2))
|
|
<br/> OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2))
|
|
<br/> OR (nAS_FSB AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
|
<br/> NOT ram/RS(0) AND NOT ram/RS(2) AND NOT ASrf)
|
|
<br/> OR (A_FSB(22) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
|
<br/> NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
|
|
<br/> ram/RefDone_D <= ((RefReq AND ram/RefDone)
|
|
<br/> OR (RefReq AND ram/RS(2)));
|
|
</td></tr><tr><td>
|
|
FDCPE_set/SetWRr: FDCPE port map (set/SetWRr,set/SetWRr_D,FCLK,'0','0');
|
|
<br/> set/SetWRr_D <= ((A_FSB(21) AND A_FSB(20) AND NOT A_FSB(19) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(21) AND A_FSB(20) AND NOT A_FSB(19) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND ASrf));
|
|
</td></tr><tr><td>
|
|
Register Legend:
|
|
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
|
|
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
|
|
<br/> LDCP (Q,D,G,CLR,PRE);
|
|
</td></tr><tr><td>
|
|
</td></tr>
|
|
</table>
|
|
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