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Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD.

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Zane Kaminski 2024-10-09 04:15:23 -04:00
parent e44991266c
commit ffad08ffb5
1 changed files with 2 additions and 2 deletions
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4
cpld/IOBS.v
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@ -51,7 +51,7 @@ module IOBS(
// I/O selected, and FIFO secondary level empty // I/O selected, and FIFO secondary level empty
if (BACT && IOPWCS && !ALE1 && !Sent && TS!=0) begin if (BACT && IOPWCS && !ALE1 && !Sent && TS!=0) begin
// Latch R/W now but latch address and LDS/UDS next cycle // Latch R/W now but latch address and LDS/UDS next cycle
IORW1 <= nWE || !IORealCS; IORW1 <= nWE;// || !IORealCS;
Load1 <= 1; Load1 <= 1;
end else Load1 <= 0; end else Load1 <= 0;
end end
@ -87,7 +87,7 @@ module IOBS(
IOL0 <= IOL1; IOL0 <= IOL1;
IOU0 <= IOU1; IOU0 <= IOU1;
end else begin // FSB request end else begin // FSB request
IORW <= nWE || !IORealCS; IORW <= nWE;// || !IORealCS;
IOL0 <= !nLDS; IOL0 <= !nLDS;
IOU0 <= !nUDS; IOU0 <= !nUDS;
end end