mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-28 20:52:22 +00:00
517 lines
20 KiB
Plaintext
517 lines
20 KiB
Plaintext
Release 14.7 - xst P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.80 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.84 secs
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--> Reading design: WarpSE.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "WarpSE.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "WarpSE"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : WarpSE
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../RAM.v" in library work
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Compiling verilog file "../IOBS.v" in library work
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Module <RAM> compiled
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Compiling verilog file "../IOBM.v" in library work
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Module <IOBS> compiled
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Compiling verilog file "../FSB.v" in library work
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Module <IOBM> compiled
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Compiling verilog file "../CS.v" in library work
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Module <FSB> compiled
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Compiling verilog file "../CNT.v" in library work
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Module <CS> compiled
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Compiling verilog file "../CLK.v" in library work
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Module <CNT> compiled
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Compiling verilog file "../WarpSE.v" in library work
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Module <CLK> compiled
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Module <WarpSE> compiled
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No errors in compilation
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Analysis of file <"WarpSE.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <WarpSE> in library <work>.
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Analyzing hierarchy for module <CLK> in library <work>.
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Analyzing hierarchy for module <CS> in library <work>.
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Analyzing hierarchy for module <RAM> in library <work>.
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Analyzing hierarchy for module <IOBS> in library <work>.
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Analyzing hierarchy for module <IOBM> in library <work>.
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Analyzing hierarchy for module <CNT> in library <work>.
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Analyzing hierarchy for module <FSB> in library <work>.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <WarpSE>.
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Module <WarpSE> is correct for synthesis.
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Analyzing module <CLK> in library <work>.
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Module <CLK> is correct for synthesis.
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Analyzing module <CS> in library <work>.
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Module <CS> is correct for synthesis.
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Analyzing module <RAM> in library <work>.
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Module <RAM> is correct for synthesis.
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Analyzing module <IOBS> in library <work>.
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Module <IOBS> is correct for synthesis.
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Analyzing module <IOBM> in library <work>.
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Module <IOBM> is correct for synthesis.
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Analyzing module <CNT> in library <work>.
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Module <CNT> is correct for synthesis.
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Analyzing module <FSB> in library <work>.
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Module <FSB> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2679 - Register <BA<1>> in unit <RAM> has a constant value of 0 during circuit operation. The register is replaced by logic.
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Synthesizing Unit <CLK>.
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Related source file is "../CLK.v".
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WARNING:Xst:1305 - Output <RCLK> is never assigned. Tied to value 0.
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WARNING:Xst:1305 - Output <SS<2>> is never assigned. Tied to value 0.
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Found 2-bit register for signal <SS<1:0>>.
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Found 1-bit register for signal <MCLK>.
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Found 2-bit adder for signal <$add0000> created at line 6.
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Summary:
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inferred 3 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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Unit <CLK> synthesized.
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Synthesizing Unit <CS>.
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Related source file is "../CS.v".
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Found 1-bit register for signal <nOverlay0>.
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Found 1-bit register for signal <nOverlay1>.
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Summary:
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inferred 2 D-type flip-flop(s).
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Unit <CS> synthesized.
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Synthesizing Unit <RAM>.
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Related source file is "../RAM.v".
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WARNING:Xst:647 - Input <BACT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found finite state machine <FSM_0> for signal <RS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 6 |
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| Inputs | 2 |
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| Outputs | 4 |
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| Clock | CLK (rising_edge) |
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| Clock enable | RS$cmp_eq0000 (positive) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <BA<0>>.
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Found 1-bit register for signal <nRAS>.
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Found 1-bit register for signal <nCS>.
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Found 1-bit register for signal <nCAS>.
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Found 12-bit register for signal <RA>.
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Found 1-bit register for signal <nRWE>.
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Found 1-bit register for signal <DQMH>.
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Found 1-bit register for signal <DQML>.
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Found 1-bit register for signal <CKE>.
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Found 1-bit register for signal <Once1>.
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Found 1-bit register for signal <Once3>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 21 D-type flip-flop(s).
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Unit <RAM> synthesized.
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Synthesizing Unit <IOBS>.
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Related source file is "../IOBS.v".
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Found finite state machine <FSM_1> for signal <PS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 10 |
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| Inputs | 5 |
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| Outputs | 5 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <BERR>.
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Found 1-bit register for signal <IOREQ>.
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Found 1-bit register for signal <IORW0>.
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Found 1-bit register for signal <IOL0>.
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Found 1-bit register for signal <IOU0>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <ALE1>.
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Found 1-bit register for signal <Clear1>.
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Found 1-bit register for signal <IOACTr>.
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Found 1-bit register for signal <IOL1>.
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Found 1-bit register for signal <IOReady>.
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Found 1-bit register for signal <IORW1>.
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Found 1-bit register for signal <IOU1>.
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Found 1-bit register for signal <Load1>.
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Found 1-bit register for signal <Once>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 9 D-type flip-flop(s).
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Unit <IOBS> synthesized.
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Synthesizing Unit <IOBM>.
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Related source file is "../IOBM.v".
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Found finite state machine <FSM_2> for signal <IOS>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 16 |
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| Inputs | 7 |
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| Outputs | 8 |
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| Clock | C16M (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <IOBERR>.
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Found 1-bit register for signal <nASout>.
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Found 1-bit register for signal <IOACT>.
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Found 1-bit register for signal <nLDS>.
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Found 1-bit register for signal <nUDS>.
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Found 1-bit register for signal <nDinLE>.
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Found 1-bit register for signal <nDoutOE>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <nVMA>.
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Found 1-bit register for signal <BERRrf>.
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Found 1-bit register for signal <BERRrr>.
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Found 1-bit register for signal <BG>.
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Found 1-bit register for signal <BGr0>.
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Found 1-bit register for signal <BGr1>.
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Found 1-bit register for signal <DTACKrf>.
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Found 1-bit register for signal <DTACKrr>.
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Found 1-bit register for signal <Er>.
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Found 1-bit register for signal <Er2>.
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Found 5-bit up counter for signal <ES>.
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Found 1-bit register for signal <ETACK>.
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Found 1-bit register for signal <IOREQr>.
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Found 1-bit register for signal <RESrf>.
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Found 1-bit register for signal <RESrr>.
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Found 1-bit register for signal <VPArf>.
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Found 1-bit register for signal <VPArr>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 22 D-type flip-flop(s).
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Unit <IOBM> synthesized.
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Synthesizing Unit <CNT>.
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Related source file is "../CNT.v".
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Found 1-bit register for signal <TimeoutA>.
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Found 1-bit register for signal <TimeoutB>.
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Found 8-bit up counter for signal <RefCnt>.
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Found 1-bit register for signal <TimeoutBPre>.
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Summary:
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inferred 1 Counter(s).
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Unit <CNT> synthesized.
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Synthesizing Unit <FSB>.
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Related source file is "../FSB.v".
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WARNING:Xst:647 - Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 1-bit register for signal <nDTACK>.
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Found 1-bit register for signal <BACT>.
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Found 1-bit register for signal <BERR0r>.
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Found 1-bit register for signal <BERR1r>.
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Found 1-bit register for signal <Ready0r>.
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Found 1-bit register for signal <Ready1r>.
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Found 1-bit register for signal <VPA>.
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Summary:
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inferred 1 D-type flip-flop(s).
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Unit <FSB> synthesized.
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Synthesizing Unit <WarpSE>.
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Related source file is "../WarpSE.v".
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WARNING:Xst:647 - Input <SW<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 1-bit tristate buffer for signal <nAS_IOB>.
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Found 1-bit tristate buffer for signal <nLDS_IOB>.
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Found 1-bit tristate buffer for signal <nUDS_IOB>.
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Found 1-bit tristate buffer for signal <nVMA_IOB>.
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Found 1-bit register for signal <Disable>.
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Found 1-bit register for signal <IPL2r0>.
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Found 1-bit register for signal <IPL2r1>.
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Found 1-bit register for signal <RESDone>.
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Found 1-bit register for signal <RESr0>.
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Found 1-bit register for signal <RESr1>.
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Found 1-bit register for signal <RESr2>.
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Summary:
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inferred 7 D-type flip-flop(s).
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inferred 4 Tristate(s).
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Unit <WarpSE> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Counters : 2
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5-bit up counter : 1
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8-bit up counter : 1
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# Registers : 83
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1-bit register : 83
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# Tristates : 4
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1-bit tristate buffer : 4
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_2> for best encoding.
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Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:3]> with gray encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 000
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001 | 001
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010 | 011
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011 | 010
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100 | 110
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101 | 111
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110 | 101
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111 | 100
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-------------------
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Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <iobs/PS/FSM> on signal <PS[1:2]> with johnson encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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11 | 01
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10 | 11
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01 | 10
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-------------------
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <ram/RS/FSM> on signal <RS[1:2]> with compact encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 10
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01 | 00
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11 | 11
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10 | 01
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-------------------
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WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone.
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You should achieve better results by setting this init to 1.
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WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable.
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You should achieve better results by setting this init to 1.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 3
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# Adders/Subtractors : 1
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2-bit adder : 1
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# Counters : 2
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5-bit up counter : 1
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8-bit up counter : 1
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# Registers : 65
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Flip-Flops : 65
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:1426 - The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE.
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You should achieve better results by setting this init to 1.
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WARNING:Xst:1426 - The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE.
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You should achieve better results by setting this init to 1.
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Optimizing unit <WarpSE> ...
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implementation constraint: INIT=r : RESr0
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implementation constraint: INIT=r : RESr1
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implementation constraint: INIT=r : RESr2
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implementation constraint: INIT=r : IPL2r0
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implementation constraint: INIT=r : IPL2r1
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implementation constraint: INIT=r : Disable
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implementation constraint: INIT=r : RESDone
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implementation constraint: INIT=r : ram/Once3
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implementation constraint: INIT=r : ram/Once1
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implementation constraint: INIT=r : iobs/PS_FSM_FFd1
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implementation constraint: INIT=r : iobs/IOACTr
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implementation constraint: INIT=r : iobs/Once
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implementation constraint: INIT=r : cs/nOverlay0
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implementation constraint: INIT=r : cs/nOverlay1
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implementation constraint: INIT=r : iobm/IOREQr
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implementation constraint: INIT=r : iobs/PS_FSM_FFd2
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implementation constraint: INIT=r : iobm/IOS_FSM_FFd2
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implementation constraint: INIT=r : iobm/IOS_FSM_FFd3
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implementation constraint: INIT=r : iobm/ETACK
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implementation constraint: INIT=r : iobm/BGr0
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implementation constraint: INIT=r : iobm/BGr1
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implementation constraint: INIT=r : iobm/BG
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implementation constraint: INIT=s : ram/RS_FSM_FFd1
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implementation constraint: INIT=r : ram/RS_FSM_FFd2
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implementation constraint: INIT=r : cnt/RefCnt_0
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implementation constraint: INIT=r : cnt/RefCnt_1
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implementation constraint: INIT=r : cnt/RefCnt_2
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implementation constraint: INIT=r : cnt/RefCnt_3
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implementation constraint: INIT=r : cnt/RefCnt_4
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implementation constraint: INIT=r : cnt/RefCnt_5
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implementation constraint: INIT=r : cnt/RefCnt_6
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implementation constraint: INIT=r : cnt/RefCnt_7
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implementation constraint: INIT=r : iobm/IOS_FSM_FFd1
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : WarpSE.ngr
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Top Level Output File Name : WarpSE
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Target Technology : XC9500XL CPLDs
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Macro Preserve : YES
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XOR Preserve : YES
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Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 79
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Cell Usage :
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# BELS : 631
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# AND2 : 180
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# AND3 : 29
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# AND4 : 13
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# AND5 : 1
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# AND6 : 1
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# AND7 : 1
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# AND8 : 3
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# GND : 1
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# INV : 266
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# OR2 : 109
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# OR3 : 9
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# OR4 : 3
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# VCC : 1
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# XOR2 : 14
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# FlipFlops/Latches : 103
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# FD : 72
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# FDCE : 31
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# Tri-States : 1
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# BUFE : 1
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# IO Buffers : 78
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# IBUF : 39
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# OBUF : 35
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# OBUFE : 4
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=========================================================================
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Total REAL time to Xst completion: 23.00 secs
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Total CPU time to Xst completion: 22.87 secs
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-->
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Total memory usage is 205652 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 10 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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