115 lines
3.0 KiB
Verilog
115 lines
3.0 KiB
Verilog
module CNT(
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/* FSB clock and E clock inputs */
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input CLK, input C8M, input E,
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/* Refresh request */
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output reg RefReq, output reg RefUrg,
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/* Reset, button */
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output reg nRESout, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output reg nBR_IOB,
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/* Sound QoS */
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input BACT, input WS, input nWE,
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input SndROMCS, input SndRAMCSWR, input RAMCS,
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output reg QoSReady);
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/* E clock synchronization */
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reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
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wire EFall = Er[1] && !Er[0];
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/* C8M clock synchronization */
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reg [1:0] C8Mr; always @(posedge CLK) C8Mr[1:0] <= { C8Mr[0], C8M };
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wire C8MFall = C8Mr[1] && !C8Mr[0];
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/* NMI button synchronization */
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reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
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/* Startup sequence state */
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reg [1:0] IS = 0;
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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* Refresh timer sequence
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* | Timer | RefReq | RefUrg |
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* |---------|--------|-----------|
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* | 0 0000 | 0 | 0 |
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* | 1 0001 | 1 | 0 |
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* | 2 0010 | 1 | 0 |
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* | 3 0011 | 1 | 0 |
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* | 4 0100 | 1 | 0 |
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* | 5 0101 | 1 | 0 |
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* | 6 0110 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 8 1000 | 1 | 0 |
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* | 9 1001 | 1 | 1 |
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* | 10 1010 | 1 | 1 |
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* back to timer==0
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*/
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reg [3:0] Timer = 0;
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reg TimerTC;
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always @(posedge CLK) begin
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if (EFall) begin
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if (TimerTC) Timer <= 0;
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else Timer <= Timer+1;
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RefUrg <= Timer==8 || Timer==9;
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RefReq <= Timer!=10;
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TimerTC <= Timer==9;
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end
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end
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/* During init (IS!=3) long timer counts from 0 to 4095.
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* 4096 states == 57.516 ms
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* During operation (IS==3) long timer counts from 0 to 3
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* starting at first sound RAM access.
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* Period is 28.124 us - 42.240 us */
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reg [11:0] LTimer;
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reg LTimerTC;
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always @(posedge CLK) begin
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if (EFall && TimerTC) begin
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LTimer <= LTimer+1;
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LTimerTC <= LTimer[11:0]==12'hFFE;
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end
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end
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/* Sound QoS trigger */
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reg [1:0] QS;
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wire QoSEN = QS!=0;
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always @(posedge CLK) begin
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if (BACT && SndRAMCSWR) QS[1:0] <= 1;
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else if (QS==0) QS[1:0] <= 0;
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else if (EFall && TimerTC) QS[1:0] <= QS+1;
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end
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/* Sound QoS */
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reg [4:0] Wait = 0;
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always @(posedge CLK) begin
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if (!BACT) Wait <= 0;
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else Wait <= Wait+1;
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if (!BACT || !QoSReady) QoSReady <= !QoSEN || (Wait==16);
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end
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/* Startup sequence state control */
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wire ISTC = EFall && TimerTC && LTimerTC;
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always @(posedge CLK) begin
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case (IS[1:0])
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0: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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if (ISTC) IS <= 1;
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end 1: begin
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AoutOE <= 0;
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nRESout <= 0;
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nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
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if (ISTC && nIPL2r) IS <= 2;
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end 2: begin
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AoutOE <= !nBR_IOB;
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nRESout <= 0;
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if (ISTC) IS <= 3;
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end 3: begin
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nRESout <= 1; // Release reset
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IS <= 3;
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end
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endcase
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end
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endmodule
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