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https://github.com/garrettsworkshop/Warp-SE.git
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51 lines
952 B
Verilog
51 lines
952 B
Verilog
module SET(
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input CLK,
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input nPOR,
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input BACT,
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input [11:1] A,
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input SetCSWR,
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output SlowIACK,
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output SlowVIA,
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output SlowIWM,
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output SlowSCC,
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output SlowSCSI,
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output SlowSnd,
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output SlowClockGate,
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output [3:0] SlowInterval);
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//reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
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assign SlowInterval[3:0] = 4'hF;
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assign SlowIACK = 1;
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assign SlowVIA = 1;
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assign SlowIWM = 1;
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assign SlowSCC = 1;
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assign SlowSCSI = 1;
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assign SlowSnd = 1;
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assign SlowClockGate = 0;
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/*always @(posedge CLK) begin
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if (!nPOR) begin
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SlowInterval[3:0] <= 4'hF;
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SlowIACK <= 1;
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SlowVIA <= 1;
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SlowIWM <= 1;
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SlowSCC <= 1;
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SlowSCSI <= 1;
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SlowSnd <= 1;
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SlowClockGate <= 0;
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end else if (SetWRr) begin
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SlowInterval[3:0] <= A[11:8];
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SlowIACK <= A[7];
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SlowVIA <= A[6];
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SlowIWM <= A[5];
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SlowSCC <= A[4];
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SlowSCSI <= A[3];
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SlowSnd <= A[2];
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SlowClockGate <= A[1];
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end
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end*/
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endmodule
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