Warp-SE/cpld/FSB.v
2023-04-07 02:33:04 -04:00

30 lines
782 B
Verilog

module FSB(
/* MC68HC000 interface */
input FCLK, input nAS, output reg nDTACK, output reg nVPA,
/* AS cycle detection */
output BACT,
/* Ready inputs */
input ROMCS,
input RAMCS, input RAMReady,
input IOPWCS, input IOPWReady, input IONPReady,
/* Interrupt acknowledge select */
input IACS);
/* AS cycle detection */
reg ASrf = 0;
always @(negedge FCLK) begin ASrf <= !nAS; end
assign BACT = !nAS || ASrf; // BACT - bus active
/* DTACK/VPA control */
wire Ready = (RAMCS && RAMReady && !IOPWCS) ||
(RAMCS && RAMReady && IOPWCS && IOPWReady) ||
(ROMCS) || (IONPReady);
always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
always @(posedge FCLK, posedge nAS) begin
if (nAS) nVPA <= 1;
else nVPA <= !(Ready && BACT && IACS);
end
endmodule