mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-24 21:34:16 +00:00
876 lines
63 KiB
HTML
876 lines
63 KiB
HTML
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
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<h3 align='center'>Equations</h3>
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<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
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<tr><td>
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</td></tr><tr><td>
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********** Mapped Logic **********
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</td></tr><tr><td>
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FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
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<br/> ALE0M_D <= ((iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND
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<br/> NOT iobm/IOREQr));
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</td></tr><tr><td>
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FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,FCLK,'0','0');
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<br/> ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
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</td></tr><tr><td>
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</td></tr><tr><td>
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C20MEN <= '1';
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</td></tr><tr><td>
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</td></tr><tr><td>
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C25MEN <= '1';
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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</td></tr><tr><td>
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FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
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<br/> IOACT_D <= ((C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
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<br/> iobm/RESrf AND iobm/RESrr)
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<br/> OR (iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
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<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND
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<br/> NOT iobm/IOREQr)
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<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
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<br/> iobm/ETACK)
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<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
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<br/> iobm/DTACKrf AND iobm/DTACKrr)
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<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
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<br/> iobm/BERRrf AND iobm/BERRrr));
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</td></tr><tr><td>
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FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,C16M,'0','0');
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<br/> IOBERR_T <= ((C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/RESrf AND
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<br/> iobm/RESrr)
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<br/> OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/DTACKrf AND
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<br/> iobm/DTACKrr)
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<br/> OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/BERRrf AND
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<br/> iobm/BERRrr)
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<br/> OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/RESrf AND
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<br/> iobm/RESrr)
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<br/> OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
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<br/> NOT iobm/IOS_FSM_FFd2 AND IOBERR)
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<br/> OR (C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/ETACK)
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<br/> OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/ETACK)
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<br/> OR (C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/DTACKrf AND
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<br/> iobm/DTACKrr)
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<br/> OR (C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
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<br/> iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/BERRrf AND
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<br/> iobm/BERRrr));
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</td></tr><tr><td>
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FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,FCLK,'0','0',IOL0_CE);
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<br/> IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
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<br/> OR (iobs/IOL1 AND NOT nADoutLE1));
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<br/> IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
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</td></tr><tr><td>
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FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,FCLK,'0','0');
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<br/> IOREQ_D <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nAS_FSB AND
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<br/> NOT iobs/PS_FSM_FFd1)
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<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND
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<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
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<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nAS_FSB AND
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<br/> NOT iobs/PS_FSM_FFd1)
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<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND
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<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
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<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
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<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
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<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd1)
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<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
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<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
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<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
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<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
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<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
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<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd1)
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<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
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<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
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<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
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<br/> OR (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
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<br/> OR (iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr)
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<br/> OR (NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
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<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
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<br/> NOT iobs/PS_FSM_FFd1)
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<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd1 AND
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<br/> fsb/ASrf));
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</td></tr><tr><td>
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FDCPE_IORW0: FDCPE port map (IORW0,IORW0_D,FCLK,'0','0');
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<br/> IORW0_D <= ((EXP11_.EXP)
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<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nWE_FSB AND
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<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
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<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nWE_FSB AND
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<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
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<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nWE_FSB AND
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<br/> NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
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<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nWE_FSB AND
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<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
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<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
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<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
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<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
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<br/> nADoutLE1)
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<br/> OR (NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
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<br/> NOT nADoutLE1)
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<br/> OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT IORW0 AND
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<br/> nADoutLE1)
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<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND
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<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
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<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nWE_FSB AND
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<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
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<br/> OR (NOT IORW0 AND iobs/PS_FSM_FFd2)
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<br/> OR (NOT IORW0 AND iobs/PS_FSM_FFd1)
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<br/> OR (iobs/Once AND NOT IORW0 AND nADoutLE1)
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<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT IORW0 AND nADoutLE1)
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<br/> OR (NOT IORW0 AND nAS_FSB AND NOT fsb/ASrf AND nADoutLE1));
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</td></tr><tr><td>
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FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,FCLK,'0','0',IOU0_CE);
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<br/> IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
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<br/> OR (iobs/IOU1 AND NOT nADoutLE1));
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<br/> IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(1)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(1) <= ((A_FSB(11) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(2)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(2) <= ((A_FSB(12) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(3)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(4)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(5)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(6)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
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<br/> OR (ram/RASEL AND A_FSB(7)));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(7) <= ((A_FSB(8) AND ram/RASEL)
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<br/> OR (A_FSB(17) AND NOT ram/RASEL));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(8) <= ((A_FSB(23) AND A_FSB(18))
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<br/> OR (A_FSB(22) AND A_FSB(18))
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<br/> OR (A_FSB(18) AND NOT cs/nOverlay)
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<br/> OR (A_FSB(18) AND NOT ram/RASEL)
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<br/> OR (A_FSB(9) AND NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
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<br/> ram/RASEL));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(9) <= ((A_FSB(20) AND ram/RASEL)
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<br/> OR (A_FSB(19) AND NOT ram/RASEL));
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(10) <= A_FSB(21);
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</td></tr><tr><td>
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</td></tr><tr><td>
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RA(11) <= A_FSB(19);
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</td></tr><tr><td>
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FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
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<br/> RefReq_D <= (NOT RefUrg AND NOT cnt/Timer(1) AND NOT cnt/Timer(2));
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<br/> RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_RefUrg: FTCPE port map (RefUrg,RefUrg_T,FCLK,'0','0',RefUrg_CE);
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<br/> RefUrg_T <= ((RefUrg AND cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1))
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<br/> OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
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<br/> NOT cnt/TimerTC)
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<br/> OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
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<br/> cnt/Er(0))
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<br/> OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
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<br/> NOT cnt/Er(1)));
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<br/> RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
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</td></tr><tr><td>
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FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
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</td></tr><tr><td>
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FTCPE_cnt/INITS_FSM_FFd1: FTCPE port map (cnt/INITS_FSM_FFd1,cnt/INITS_FSM_FFd1_T,FCLK,'0','0');
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<br/> cnt/INITS_FSM_FFd1_T <= (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/INITS_FSM_FFd1 AND
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<br/> cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/nIPL2r AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/INITS_FSM_FFd2: FTCPE port map (cnt/INITS_FSM_FFd2,cnt/INITS_FSM_FFd2_T,FCLK,'0','0');
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<br/> cnt/INITS_FSM_FFd2_T <= ((cnt/TimerTC AND cnt/LTimerTC AND cnt/INITS_FSM_FFd1 AND
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<br/> cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1))
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<br/> OR (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/INITS_FSM_FFd1 AND
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<br/> NOT cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/LTimer_CE(0));
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<br/> cnt/LTimer_CE(0) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/LTimer_CE(1));
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<br/> cnt/LTimer_CE(1) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/LTimer_CE(2));
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<br/> cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1));
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<br/> cnt/LTimer_CE(2) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/LTimer_CE(3));
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<br/> cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
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<br/> cnt/LTimer_CE(3) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/LTimer_CE(4));
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<br/> cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
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<br/> cnt/LTimer(3));
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<br/> cnt/LTimer_CE(4) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/LTimer_CE(5));
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<br/> cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
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<br/> cnt/LTimer(3) AND cnt/LTimer(4));
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<br/> cnt/LTimer_CE(5) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/LTimer_CE(6));
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<br/> cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
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<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
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<br/> cnt/LTimer_CE(6) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
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</td></tr><tr><td>
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FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/LTimer_CE(7));
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<br/> cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
|
|
<br/> cnt/LTimer_CE(7) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/LTimer_CE(8));
|
|
<br/> cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
<br/> cnt/LTimer(7));
|
|
<br/> cnt/LTimer_CE(8) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/LTimer_CE(9));
|
|
<br/> cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
<br/> cnt/LTimer(7) AND cnt/LTimer(8));
|
|
<br/> cnt/LTimer_CE(9) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/LTimer_CE(10));
|
|
<br/> cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
<br/> cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
<br/> cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
|
<br/> cnt/LTimer_CE(10) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/LTimer_CE(11));
|
|
<br/> cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
|
<br/> cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
|
<br/> cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
|
<br/> cnt/LTimer_CE(11) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/LTimer12: FTCPE port map (cnt/LTimer(12),cnt/LTimer_T(12),FCLK,'0','0',cnt/LTimer_CE(12));
|
|
<br/> cnt/LTimer_T(12) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(11) AND
|
|
<br/> cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND
|
|
<br/> cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND
|
|
<br/> cnt/LTimer(9));
|
|
<br/> cnt/LTimer_CE(12) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/LTimerTC: FDCPE port map (cnt/LTimerTC,cnt/LTimerTC_D,FCLK,'0','0',cnt/LTimerTC_CE);
|
|
<br/> cnt/LTimerTC_D <= (NOT cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(11) AND
|
|
<br/> cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND
|
|
<br/> cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND
|
|
<br/> cnt/LTimer(9) AND cnt/LTimer(12));
|
|
<br/> cnt/LTimerTC_CE <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
|
|
<br/> cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/TimerTC AND NOT cnt/Er(0) AND
|
|
<br/> cnt/Er(1));
|
|
<br/> cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/Timer1: FDCPE port map (cnt/Timer(1),cnt/Timer_D(1),FCLK,'0','0',cnt/Timer_CE(1));
|
|
<br/> cnt/Timer_D(1) <= ((cnt/Timer(0) AND cnt/Timer(1))
|
|
<br/> OR (NOT cnt/Timer(0) AND NOT cnt/Timer(1))
|
|
<br/> OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
|
|
<br/> cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/Timer2: FDCPE port map (cnt/Timer(2),cnt/Timer_D(2),FCLK,'0','0',cnt/Timer_CE(2));
|
|
<br/> cnt/Timer_D(2) <= ((NOT cnt/Timer(0) AND NOT cnt/Timer(2))
|
|
<br/> OR (NOT cnt/Timer(1) AND NOT cnt/Timer(2))
|
|
<br/> OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
|
|
<br/> OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
|
|
<br/> cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/TimerTC: FDCPE port map (cnt/TimerTC,cnt/TimerTC_D,FCLK,'0','0',cnt/TimerTC_CE);
|
|
<br/> cnt/TimerTC_D <= (RefUrg AND cnt/Timer(0) AND NOT cnt/Timer(1) AND
|
|
<br/> NOT cnt/Timer(2));
|
|
<br/> cnt/TimerTC_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
</td></tr><tr><td>
|
|
FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FTCPE_cs/nOverlay: FTCPE port map (cs/nOverlay,cs/nOverlay_T,FCLK,NOT nRES.PIN,'0');
|
|
<br/> cs/nOverlay_T <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
|
<br/> NOT cs/nOverlay AND NOT nAS_FSB)
|
|
<br/> OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
|
<br/> NOT cs/nOverlay AND fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,FCLK,'0','0');
|
|
<br/> fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready0r AND NOT ram/RAMReady));
|
|
</td></tr><tr><td>
|
|
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,FCLK,'0','0');
|
|
<br/> fsb/Ready1r_D <= ((A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nADoutLE1)
|
|
<br/> OR (nAS_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND
|
|
<br/> NOT iobs/IOReady)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND
|
|
<br/> NOT iobs/IOReady)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,FCLK,'0','0');
|
|
<br/> fsb/VPA_D <= ((EXP12_.EXP)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND fsb/VPA AND
|
|
<br/> NOT iobs/IOReady AND fsb/ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready0r AND fsb/VPA AND NOT nAS_FSB AND NOT ram/RAMReady)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready0r AND fsb/VPA AND fsb/ASrf AND NOT ram/RAMReady)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nAS_FSB AND
|
|
<br/> NOT nADoutLE1)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nAS_FSB AND
|
|
<br/> NOT nADoutLE1)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND fsb/ASrf AND
|
|
<br/> NOT nADoutLE1)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND fsb/ASrf AND
|
|
<br/> NOT nADoutLE1)
|
|
<br/> OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
|
|
<br/> A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND fsb/Ready1r AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
|
|
<br/> A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND iobs/IOReady AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
|
|
<br/> A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND iobs/IOReady AND fsb/ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
|
|
<br/> NOT iobs/IOReady AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
|
|
<br/> NOT iobs/IOReady AND fsb/ASrf)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND fsb/VPA AND
|
|
<br/> NOT iobs/IOReady AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND fsb/VPA AND
|
|
<br/> NOT iobs/IOReady AND fsb/ASrf)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND fsb/VPA AND
|
|
<br/> NOT iobs/IOReady AND NOT nAS_FSB));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/DoutOE: FDCPE port map (iobm/DoutOE,iobm/DoutOE_D,C16M,'0','0');
|
|
<br/> iobm/DoutOE_D <= ((NOT IORW0 AND iobm/IOS_FSM_FFd3)
|
|
<br/> OR (NOT IORW0 AND iobm/IOS_FSM_FFd2)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd2 AND NOT iobm/IOREQr AND NOT nAoutOE));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),C16M,'0','0');
|
|
<br/> iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
|
|
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
|
|
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),C16M,'0','0');
|
|
<br/> iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
|
<br/> OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
|
<br/> OR (NOT iobm/Er AND iobm/Er2));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),C16M,'0','0');
|
|
<br/> iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
|
|
<br/> OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
|
|
<br/> OR (NOT iobm/Er AND iobm/Er2)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
|
|
<br/> OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),C16M,'0','0');
|
|
<br/> iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),C16M,'0','0');
|
|
<br/> iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
|
<br/> iobm/ES(3) AND iobm/Er)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
|
<br/> iobm/ES(3) AND NOT iobm/Er2)
|
|
<br/> OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND iobm/ES(4)));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,C16M,'0','0');
|
|
<br/> iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND iobm/ES(4));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd1_D <= ((iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1)
|
|
<br/> OR (NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobm/IOS_FSM_FFd2: FTCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_T,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd2_T <= ((iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd2)
|
|
<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
|
|
<br/> iobm/IOS_FSM_FFd2 AND iobm/ETACK)
|
|
<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
|
|
<br/> iobm/IOS_FSM_FFd2 AND iobm/DTACKrf AND iobm/DTACKrr)
|
|
<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
|
|
<br/> iobm/IOS_FSM_FFd2 AND iobm/BERRrf AND iobm/BERRrr)
|
|
<br/> OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
|
|
<br/> iobm/IOS_FSM_FFd2 AND iobm/RESrf AND iobm/RESrr));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
|
|
<br/> iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
|
|
<br/> OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd2)
|
|
<br/> OR (NOT C8M AND NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2 AND
|
|
<br/> iobm/IOREQr AND NOT nAoutOE));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES.PIN,NOT C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES.PIN,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,C16M,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
|
|
<br/> iobs/Clear1_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1);
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
</td></tr><tr><td>
|
|
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
|
|
<br/> iobs/IORW1_T <= ((iobs/Once)
|
|
<br/> OR (NOT nADoutLE1)
|
|
<br/> OR (nDTACK_FSB_OBUF.EXP)
|
|
<br/> OR (nAS_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20))
|
|
<br/> OR (nWE_FSB AND iobs/IORW1)
|
|
<br/> OR (NOT nWE_FSB AND NOT iobs/IORW1)
|
|
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,FCLK,'0','0');
|
|
<br/> iobs/IOReady_T <= ((iobs/Once AND iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
|
|
<br/> NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
|
|
<br/> OR (iobs/Once AND NOT iobs/IOReady AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
|
|
<br/> OR (iobs/Once AND NOT iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
|
|
<br/> NOT iobs/IOACTr AND NOT IOBERR AND fsb/ASrf AND nADoutLE1)
|
|
<br/> OR (iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
|
|
<br/> iobs/Load1_D <= ((iobs/Once)
|
|
<br/> OR (NOT nADoutLE1)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20))
|
|
<br/> OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND NOT A_FSB(22))
|
|
<br/> OR (nAS_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobs/Once: FTCPE port map (iobs/Once,iobs/Once_T,FCLK,'0','0');
|
|
<br/> iobs/Once_T <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(14) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
|
<br/> A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
|
<br/> NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
|
|
<br/> OR (A_FSB(14) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
|
<br/> A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
|
<br/> NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
|
|
<br/> OR (A_FSB(13) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
|
<br/> A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
|
<br/> NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
|
|
<br/> OR (A_FSB(13) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
|
|
<br/> A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
|
|
<br/> NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
|
|
<br/> OR (iobs/Once AND nAS_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
|
|
<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
|
|
</td></tr><tr><td>
|
|
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,FCLK,'0','0');
|
|
<br/> iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
|
|
<br/> OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
|
|
</td></tr><tr><td>
|
|
FTCPE_iobs/PS_FSM_FFd2: FTCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_T,FCLK,'0','0');
|
|
<br/> iobs/PS_FSM_FFd2_T <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
|
|
<br/> NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr)
|
|
<br/> OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
|
|
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
|
|
<br/> OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
|
|
<br/> NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nAS_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
|
</td></tr><tr><td>
|
|
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
|
|
<br/> nADoutLE1_D <= ((iobs/Load1)
|
|
<br/> OR (NOT iobs/Clear1 AND NOT nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
|
|
<br/> nAS_IOB <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2)
|
|
<br/> OR (iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2));
|
|
<br/> nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
|
|
<br/> nAS_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
|
|
<br/> nAoutOE_D <= ((NOT nBR_IOB AND cnt/INITS_FSM_FFd1 AND
|
|
<br/> cnt/INITS_FSM_FFd2)
|
|
<br/> OR (cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2 AND
|
|
<br/> NOT nAoutOE));
|
|
</td></tr><tr><td>
|
|
FTCPE_nBERR_FSB: FTCPE port map (nBERR_FSB,nBERR_FSB_T,FCLK,'0','0');
|
|
<br/> nBERR_FSB_T <= ((nAS_FSB AND NOT nBERR_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (iobs/Once AND NOT nBERR_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
|
<br/> NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
|
|
<br/> OR (iobs/Once AND NOT nAS_FSB AND nBERR_FSB AND
|
|
<br/> NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
|
|
<br/> OR (iobs/Once AND nBERR_FSB AND NOT iobs/PS_FSM_FFd2 AND
|
|
<br/> NOT iobs/IOACTr AND IOBERR AND fsb/ASrf AND nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FTCPE_nBR_IOB: FTCPE port map (nBR_IOB,nBR_IOB_T,FCLK,'0','0');
|
|
<br/> nBR_IOB_T <= ((nBR_IOB AND NOT cnt/INITS_FSM_FFd1 AND
|
|
<br/> NOT cnt/INITS_FSM_FFd2)
|
|
<br/> OR (NOT nBR_IOB AND NOT cnt/INITS_FSM_FFd1 AND
|
|
<br/> cnt/INITS_FSM_FFd2 AND NOT cnt/nIPL2r));
|
|
</td></tr><tr><td>
|
|
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
|
|
<br/> nDTACK_FSB_D <= ((nAS_FSB AND NOT fsb/ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
|
|
<br/> nDTACK_FSB)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND
|
|
<br/> NOT iobs/IOReady AND nDTACK_FSB)
|
|
<br/> OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
|
|
<br/> A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND fsb/Ready1r)
|
|
<br/> OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
|
|
<br/> A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
|
|
<br/> A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
<br/> A_FSB(17) AND A_FSB(16) AND iobs/IOReady)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND
|
|
<br/> NOT iobs/IOReady AND nDTACK_FSB)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
|
|
<br/> OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND nDTACK_FSB AND NOT nADoutLE1)
|
|
<br/> OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
|
|
<br/> A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
|
|
<br/> NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND nDTACK_FSB AND NOT nADoutLE1));
|
|
</td></tr><tr><td>
|
|
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
|
|
<br/> nDinLE_D <= (iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2);
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nDinOE <= NOT (((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(22) AND A_FSB(21) AND nWE_FSB AND NOT nAS_FSB)
|
|
<br/> OR (A_FSB(22) AND A_FSB(20) AND nWE_FSB AND NOT nAS_FSB)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nDoutOE <= NOT ((iobm/DoutOE AND NOT nAoutOE));
|
|
</td></tr><tr><td>
|
|
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
|
|
<br/> nLDS_IOB <= ((IOL0 AND NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2)
|
|
<br/> OR (IOL0 AND iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
|
|
<br/> OR (IORW0 AND IOL0 AND iobm/IOS_FSM_FFd3 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd1));
|
|
<br/> nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
|
|
<br/> nLDS_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nOE <= NOT ((nWE_FSB AND NOT nAS_FSB));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRAMLWE <= NOT ((NOT nLDS_FSB AND NOT nWE_FSB AND NOT nAS_FSB AND ram/RAMEN));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT nAS_FSB AND ram/RAMEN));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRAS <= NOT (((ram/RefRAS)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
|
|
<br/> ram/RAMEN)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nRES_I <= '0';
|
|
<br/> nRES <= nRES_I when nRES_OE = '1' else 'Z';
|
|
<br/> nRES_OE <= NOT nRESout;
|
|
</td></tr><tr><td>
|
|
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
|
|
<br/> nRESout_D <= (cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2);
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nROMCS <= NOT (((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20))
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT cs/nOverlay)));
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
|
|
</td></tr><tr><td>
|
|
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
|
|
<br/> nUDS_IOB <= ((IOU0 AND NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2)
|
|
<br/> OR (IOU0 AND iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
|
|
<br/> OR (IORW0 AND IOU0 AND iobm/IOS_FSM_FFd3 AND
|
|
<br/> NOT iobm/IOS_FSM_FFd1));
|
|
<br/> nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
|
|
<br/> nUDS_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C16M,'0','0');
|
|
<br/> nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4))
|
|
<br/> OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
|
|
<br/> NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
|
|
<br/> nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
|
|
<br/> nVMA_IOB_OE <= NOT nAoutOE;
|
|
</td></tr><tr><td>
|
|
</td></tr><tr><td>
|
|
nVPA_FSB <= NOT ((fsb/VPA AND NOT nAS_FSB));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,FCLK,'0','0');
|
|
<br/> ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0');
|
|
<br/> ram/RAMEN_D <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
|
|
<br/> OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND ram/RAMEN)
|
|
<br/> OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
|
|
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
|
|
<br/> OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RAMEN)
|
|
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
|
|
<br/> ram/BACTr)
|
|
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
|
|
<br/> NOT ram/RefReq)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
|
|
<br/> NOT ram/RS_FSM_FFd1 AND ram/RAMEN)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT ram/RS_FSM_FFd1 AND ram/RAMEN AND fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,FCLK,'0','0');
|
|
<br/> ram/RAMReady_D <= ((A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND ram/BACTr)
|
|
<br/> OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RefReq)
|
|
<br/> OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND ram/BACTr)
|
|
<br/> OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RefReq)
|
|
<br/> OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND ram/BACTr)
|
|
<br/> OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
|
|
<br/> OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RefReq)
|
|
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND
|
|
<br/> NOT ram/RAMEN));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
|
|
<br/> ram/RASEL_D <= ((A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND NOT ram/RefReq)
|
|
<br/> OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND NOT ram/RefReq)
|
|
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND NOT fsb/ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
|
|
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RAMEN)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RAMEN AND fsb/ASrf)
|
|
<br/> OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND ram/BACTr)
|
|
<br/> OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND ram/BACTr)
|
|
<br/> OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND ram/BACTr)
|
|
<br/> OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND NOT ram/RefReq)
|
|
<br/> OR (ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
|
<br/> OR (NOT nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
|
|
<br/> OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RS_FSM_FFd3)
|
|
<br/> OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
|
|
<br/> OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,FCLK,'0','0');
|
|
<br/> ram/RS_FSM_FFd1_T <= ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
|
|
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN AND
|
|
<br/> fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,FCLK,'0','0');
|
|
<br/> ram/RS_FSM_FFd2_T <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
|
|
<br/> OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RefUrg AND NOT fsb/ASrf)
|
|
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND
|
|
<br/> ram/BACTr)
|
|
<br/> OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND
|
|
<br/> NOT ram/RefReq)
|
|
<br/> OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
|
|
<br/> NOT ram/RefUrg AND NOT fsb/ASrf)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
|
|
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
|
|
<br/> OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
|
|
<br/> NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,FCLK,'0','0');
|
|
<br/> ram/RS_FSM_FFd3_T <= ((nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
|
|
<br/> OR (NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RAMEN)
|
|
<br/> OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3)
|
|
<br/> OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3)
|
|
<br/> OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> NOT ram/RS_FSM_FFd3)
|
|
<br/> OR (NOT nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RS_FSM_FFd3 AND ram/RefUrg)
|
|
<br/> OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RS_FSM_FFd3 AND ram/RefUrg AND fsb/ASrf));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
|
|
<br/> ram/RefDone_D <= ((ram/RefDone AND ram/RefReqSync)
|
|
<br/> OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
|
|
<br/> ram/RefReqSync));
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefRAS: FDCPE port map (ram/RefRAS,ram/RefRAS_D,FCLK,'0','0');
|
|
<br/> ram/RefRAS_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefReq: FDCPE port map (ram/RefReq,ram/RefReq_D,FCLK,'0','0');
|
|
<br/> ram/RefReq_D <= (NOT ram/RefDone AND ram/RefReqSync);
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefReqSync: FDCPE port map (ram/RefReqSync,RefReq,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RefUrg: FDCPE port map (ram/RefUrg,ram/RefUrg_D,FCLK,'0','0');
|
|
<br/> ram/RefUrg_D <= (NOT ram/RefDone AND ram/RegUrgSync);
|
|
</td></tr><tr><td>
|
|
FDCPE_ram/RegUrgSync: FDCPE port map (ram/RegUrgSync,RefUrg,FCLK,'0','0');
|
|
</td></tr><tr><td>
|
|
Register Legend:
|
|
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
|
|
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
|
|
<br/> LDCP (Q,D,G,CLR,PRE);
|
|
</td></tr><tr><td>
|
|
</td></tr>
|
|
</table>
|
|
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