Macintosh-HW/Warp-SE
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a1d07e308f
Warp-SE/cpld
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Zane Kaminski a1d07e308f put 0.7a source, .jed, etc back and recompile
2024-10-12 02:20:41 -04:00
..
XC95144XL put 0.7a source, .jed, etc back and recompile 2024-10-12 02:20:41 -04:00
CNT.v Add settings module power-on reset 2024-10-11 17:28:08 -04:00
CS.v Add slowdown settings 2024-10-11 16:41:31 -04:00
FSB.v Add slowdown settings 2024-10-11 16:41:31 -04:00
IOBM.v
IOBS.v Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD. 2024-10-09 04:15:23 -04:00
RAM.v
SET.v put 0.7a source, .jed, etc back and recompile 2024-10-12 02:20:41 -04:00
WarpSE-XC95144XL.ucf
WarpSE.v Add settings module power-on reset 2024-10-11 17:28:08 -04:00