mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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77 lines
2.7 KiB
Verilog
77 lines
2.7 KiB
Verilog
module CS(
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/* MC68HC000 interface */
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input [23:1] A, input CLK, input nRES, input nWE,
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/* AS cycle detection */
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input BACT,
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/* QoS enable input */
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input QoSEN,
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/* Device select outputs */
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output IOCS, output IORealCS, output IOPWCS,
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output ROMCS, output ROMCS4X,
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output RAMCS, output RAMCS0X,
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output IACKCS, output IACK0CS, output IACK1CS,
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output VIACS, output IWMCS,
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output SCCCS, output SCSICS, output SndCSWR,
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output SetCSWR);
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/* Overlay control */
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reg Overlay;
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always @(posedge CLK) begin
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if (!BACT && !nRES) Overlay <= 1;
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else if (BACT && ROMCS4X) Overlay <= 0;
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end
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/* I/O select signals */
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assign IACKCS = A[23:20]==4'hF && A[19];
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assign IACK0CS = IACKCS && A[1];
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assign IACK1CS = IACKCS && A[2];
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assign VIACS = A[23:20]==4'hE;
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assign IWMCS = A[23:20]==4'hD;
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assign SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
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assign SCSICS = A[23:20]==4'h5;
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/* ROM select signals */
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assign ROMCS4X = A[23:20]==4'h4;
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wire ROMCSF0X = A[23:16]==8'hF0;
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assign ROMCS = Overlay || ROMCS4X || ROMCSF0X;
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/* RAM select signals */
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assign RAMCS0X = A[23:22]==2'b00;
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assign RAMCS = RAMCS0X && !Overlay;
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wire VidRAMCSWR64k = A[23:16]==8'h3F && !nWE; // 3F0000-3FFFFF
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wire VidRAMCSWR = VidRAMCSWR64k; //&& (
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//A[15:12]==4'h2 || // 1792 bytes RAM, 2304 bytes video
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//A[15:12]==4'h3 || // 4096 bytes video
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//A[15:12]==4'h4 || // 4096 bytes video
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//A[15:12]==4'h5 || // 4096 bytes video
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//A[15:12]==4'h6 || // 4096 bytes video
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//A[15:12]==4'h7 || // 3200 bytes video, 896 bytes RAM
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//A[15:12]==4'hA || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
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//A[15:12]==4'hB || // 4096 bytes video
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//A[15:12]==4'hC || // 4096 bytes video
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//A[15:12]==4'hD || // 4096 bytes video
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//A[15:12]==4'hE || // 4096 bytes video
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//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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assign SndCSWR = VidRAMCSWR64k && (
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((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign SetCSWR = A[23:20]==4'hF && A[19:16]==4'h0 && !nWE;
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/* Select signals - IOB domain */
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assign IORealCS =
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(A[23:20]==4'hF && A[19]) || // IACK
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hC || // empty / fast ROM
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A[23:20]==4'hB || // SCC write
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A[23:20]==4'hA || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'h8 || // empty
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A[23:20]==4'h7 || // empty (expansion RAM on final rev. A except last 64 kB)
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A[23:20]==4'h6 || // empty (expansion RAM on final rev. A)
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A[23:20]==4'h5; // SCSI
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assign IOCS = IORealCS || VidRAMCSWR || QoSEN;
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assign IOPWCS = IACKCS || (VidRAMCSWR64k && !QoSEN); // Posted write to video RAM only when QoS disabled
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endmodule
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