mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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More PLD toward final version
This commit is contained in:
Zane Kaminski
parent
5721821571
commit
a94a40b13a
30
cpld/CFG_A.v
Normal file
30
cpld/CFG_A.v
Normal file
@ -0,0 +1,30 @@
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module CFG(
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input [23:20] A,
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inout GA23,
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inout GA22,
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inout GA21,
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inout GA20,
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output SlowdownIOWriteGate,
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input DBG0_ROMWS,
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input DBG1_RAMWS,
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input DBG4_IOWS,
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output ROMWS,
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output RAMWS,
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output IOWS);
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assign GA23 = 1'bZ;
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wire GA23Gate =
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(A[23:20]==4'h6) ||
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(A[23:20]==4'h7 && A[19:16]!=4'hF) ||
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(A[23:20]==4'h5 && !A[19]);
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assign GA22 = ) ? 1'b0 : A[23];
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assign GA21 = 1'bZ;
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assign GA20 = 1'bZ;
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assign SlowdownIOWriteGate = 1;
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assign ROMWS = DBG0_ROMWS;
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assign RAMWS = DBG1_RAMWS;
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assign IOWS = DBG4_IOWS;
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endmodule
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26
cpld/CFG_Prototype.v
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26
cpld/CFG_Prototype.v
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@ -0,0 +1,26 @@
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module CFG(
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input [23:20] A,
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inout GA23,
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inout GA22,
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inout GA21,
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inout GA20,
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output SlowdownIOWriteGate,
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input DBG0_ROMWS,
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input DBG1_RAMWS,
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input DBG4_IOWS,
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output ROMWS,
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output RAMWS,
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output IOWS);
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assign GA23 = A_FSB[23];
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assign GA22 = A_FSB[22];
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assign GA21 = 1'bZ;
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assign GA20 = 1'bZ;
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assign SlowdownIOWriteGate = 0;
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assign ROMWS = 0;
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assign RAMWS = 0;
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assign IOWS = 0;
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endmodule
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30
cpld/CS.v
30
cpld/CS.v
@ -6,7 +6,7 @@ module CS(
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/* QoS enable input */
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input QoSEN,
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/* Device select outputs */
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output IOCS, output IORealCS, output IOPWCS, output IACS,
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output IOCS, output IORealCS, output IOPWCS,
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output ROMCS, output ROMCS4X,
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output RAMCS, output RAMCS0X,
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output IACKCS, output IACK0CS, output IACK1CS,
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@ -22,7 +22,7 @@ module CS(
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end
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/* I/O select signals */
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assign IACKCS = A[23:20]==4'hF;
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assign IACKCS = A[23:20]==4'hF && A[19];
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assign IACK0CS = IACKCS && A[1];
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assign IACK1CS = IACKCS && A[2];
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assign VIACS = A[23:20]==4'hE;
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@ -32,7 +32,8 @@ module CS(
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/* ROM select signals */
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assign ROMCS4X = A[23:20]==4'h4;
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assign ROMCS = Overlay || ROMCS4X;
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wire ROMCSF0X = A[23:16]==8'hF0;
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assign ROMCS = Overlay || ROMCS4X || ROMCSF0X;
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/* RAM select signals */
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assign RAMCS0X = A[23:22]==2'b00;
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@ -58,19 +59,18 @@ module CS(
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assign SetCSWR = A[23:20]==4'hF && A[19:16]==4'h0 && !nWE;
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/* Select signals - IOB domain */
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assign IACS = A[23:20]==4'hF; // IACK
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assign IORealCS =
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A[23:20]==4'hF || // IACK
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hC || // empty / fast ROM
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A[23:20]==4'hB || // SCC write
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A[23:20]==4'hA || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'h8 || // empty (expansion RAM)
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A[23:20]==4'h7 || // empty (expansion RAM)
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A[23:20]==4'h6 || // empty (expansion RAM)
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A[23:20]==4'h5; // SCSI
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(A[23:20]==4'hF && A[19]) || // IACK
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hC || // empty / fast ROM
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A[23:20]==4'hB || // SCC write
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A[23:20]==4'hA || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'h8 || // empty
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A[23:20]==4'h7 || // empty (expansion RAM on final rev. A except last 64 kB)
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A[23:20]==4'h6 || // empty (expansion RAM on final rev. A)
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A[23:20]==4'h5; // SCSI
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assign IOCS = IORealCS || VidRAMCSWR || QoSEN;
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assign IOPWCS = IACKCS || (VidRAMCSWR64k && !QoSEN); // Posted write to video RAM only when QoS disabled
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endmodule
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@ -4,7 +4,7 @@ module FSB(
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/* AS cycle detection */
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output reg ASrf, output BACT, output reg BACTr,
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/* Ready inputs */
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input ROMCS,
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input ROMCS, input ROMReady,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input QoSEN,
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@ -17,9 +17,9 @@ module FSB(
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always @(posedge FCLK) BACTr <= BACT;
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/* DTACK/VPA control */
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wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) ||
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(RAMCS && !QoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !QoSEN) || (IONPReady);
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wire Ready = (RAMCS && RAMReady && !QoSEN && !IOPWCS) ||
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(RAMCS && RAMReady && !QoSEN && IOPWCS && IOPWReady) ||
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(ROMCS && ROMReady && !QoSEN) || (IONPReady);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nDTACK <= 1;
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else if (!IACKCS && Ready) nDTACK <= 0;
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16
cpld/IOBS.v
16
cpld/IOBS.v
@ -5,6 +5,10 @@ module IOBS(
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input BACT, input BACTr,
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/* Select signals */
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input IOCS, input IORealCS, input IOPWCS,
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/* I/O wait state input */
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input IOWS,
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/* Slowdown write gate configutation */
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input SlowdownIOWriteGate,
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/* FSB cycle termination outputs */
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output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
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/* Read data OE control */
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@ -20,11 +24,13 @@ module IOBS(
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/* IOACT input synchronization */
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reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
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/* IODTACK input synchronization */
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/* IODONE input synchronization */
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reg IODONErf; always @(negedge CLK) IODONErf <= IODONEin;
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reg IODONErr; always @(posedge CLK) IODONErr <= IODONErf;
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reg [1:0] IODONEr;
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always @(posedge CLK) IODONEr[1:0] <= {IODONEr[0], IODONErf};
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wire IODONE = !IODONEr[1] && IODONEr[0];
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always @(posedge CLK) IODONEr[1:0] <= !IOWS ?
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{ IODONEr[0], IODONErf } : // 0 I/O wait states
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{ IODONEr[0], IODONErr }; // 1 I/O wait state
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/* Read data OE control */
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assign nDinOE = !(!nAS && BACTr && IORealCS && nWE);
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@ -51,7 +57,7 @@ module IOBS(
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// I/O selected, and FIFO secondary level empty
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if (BACT && IOPWCS && !ALE1 && !Sent && TS!=0) begin
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// Latch R/W now but latch address and LDS/UDS next cycle
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IORW1 <= nWE;// || !IORealCS;
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IORW1 <= SlowdownIOWriteGate ? (!IORealCS ? 1 : nWE) : nWE;
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Load1 <= 1;
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end else Load1 <= 0;
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end
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@ -87,7 +93,7 @@ module IOBS(
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else begin // FSB request
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IORW <= nWE;// || !IORealCS;
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IORW <= SlowdownIOWriteGate ? (!IORealCS ? 1 : nWE) : nWE;
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IOL0 <= !nLDS;
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IOU0 <= !nUDS;
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end
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70
cpld/RAM.v
70
cpld/RAM.v
@ -6,8 +6,10 @@ module RAM(
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input BACT, input BACTr,
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/* Select and ready signals */
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input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X,
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/* RAM ready output */
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output RAMReady,
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/* RAM/ROM wait state inputs */
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input RAMWS, input ROMWS,
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/* RAM/ROM ready output */
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output reg RAMReady, output reg ROMReady,
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/* Refresh Counter Interface */
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input RefReqIn, input RefUrgIn,
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/* DRAM interface */
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@ -33,11 +35,6 @@ module RAM(
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wire RefReq = RefReqIn && !RefDone;
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wire RefUrg = RefUrgIn && !RefDone;
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/* RAM ready control */
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//reg RAMReadyReg;
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//assign RAMReady = RAMReadyReg;
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assign RAMReady = !RS[2];
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/* RAM /RAS control */
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrf);
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@ -57,6 +54,13 @@ module RAM(
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assign nROMOE = !(!nAS && ROMCS && nWE);
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assign nROMWE = !(!nAS && ROMCS4X && !nWE);
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/* ROM ready control */
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wire ROMReadyClear = ROMWS && nAS;
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always @(posedge CLK, posedge ROMReadyClear) begin
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if (ROMReadyClear) ROMReady <= 0;
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else ROMReady <= 1;
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end
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/* RAM address mux (and ROM address on RA8) */
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// RA11 doesn't do anything so both should be identical.
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assign RA[11] = !RASEL ? A[19] : A[20]; // ROM address 19
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@ -80,68 +84,88 @@ module RAM(
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(RefUrg && !BACT) ||
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// Urgent refresh during non-RAM access
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(RefUrg && BACT && !RAMCS0X);
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wire RS0toRAM = BACT && RAMCS && RASEN;
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wire RS0toRAM = BACT && RAMCS;
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always @(posedge CLK) begin
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case (RS[2:0])
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0: begin // Idle/ready
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if (RS0toRAM) RS <= 1; // Access RAM
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else if (RS0toRef) RS <= 4; // To refresh
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else RS <= 0; // Stay in idle/ready
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RASEL <= BACT && RAMCS;
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RefCAS <= RS0toRef;
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RASEN <= !RS0toRef;
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//RAMReadyReg <= !RS0toRef;
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if (RAMReady) begin // Continue accessing RAM
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RS <= 1; // Continue accessing RAM
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RAMReady <= 1;
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RASEL <= 1;
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RefCAS <= 0;
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RASEN <= 1;
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end else if (RS0toRAM) begin // Wait state
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RS <= 0;
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RAMReady <= 1;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 1;
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RefCAS <= 0;
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RASEN <= 1;
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end else if (RS0toRef) begin // Refresh
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RS <= 4;
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RAMReady <= 0;
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RASEL <= 0;
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RefCAS <= 1;
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RASEN <= 0;
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end else begin // Stay in idle
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RS <= 0;
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RAMReady <= RAMWS ? 0 : 1;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 1;
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end
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end 1: begin // RAM access
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if (!nDTACK || !BACT) RS <= 2; // Cycle ending
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else RS <= 1; // Cycle not ending yet
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RAMReady <= 1;
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RASEL <= 1;
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RefCAS <= 0;
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RASEN <= nDTACK;
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//RAMReadyReg <= 1;
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end 2: begin // finish RAM access
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RS <= 3;
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RAMReady <= 1;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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//RAMReadyReg <= 1;
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end 3: begin //AS cycle complete
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if (RefUrg) begin // Refresh RAS
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RS <= 4;
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RAMReady <= 0;
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RefCAS <= 1;
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RASEN <= 0;
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//RAMReadyReg <= 0;
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end else begin // Cycle ended so go back to idle/ready
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RS <= 0;
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RAMReady <= RAMWS ? 0 : 1;
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RefCAS <= 0;
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RASEN <= 1;
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//RAMReadyReg <= 1;
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end
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RASEL <= 0;
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end 4: begin // Refresh RAS I
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RS <= 5;
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RAMReady <= 0;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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//RAMReadyReg <= 0;
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end 5: begin // Refresh RAS II
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RS <= 6;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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//RAMReadyReg <= 0;
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RAMReady <= 0;
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end 6: begin // Refresh precharge I
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RS <= 7;
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RAMReady <= 0;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 0;
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//RAMReadyReg <= 0;
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end 7: begin // Reenable RAM and go to idle/ready
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RS <= 0;
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RAMReady <= RAMWS ? 0 : 1;
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RASEL <= 0;
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RefCAS <= 0;
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RASEN <= 1;
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//RAMReadyReg <= 1;
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end
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endcase
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end
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@ -1,6 +1,7 @@
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module WarpSE(
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input [23:1] A_FSB,
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output [23:22] GA,
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inout GA23,
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inout GA22,
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input nAS_FSB,
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input nLDS_FSB,
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input nUDS_FSB,
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@ -39,7 +40,33 @@ module WarpSE(
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output nDinOE,
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output nDinLE,
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output MCKE,
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input [5:0] DBG);
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input DBG0_ROMWS,
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input DBG1_RAMWS,
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inout DBG2_GA20,
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inout DBG3_GA21,
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input DBG4_IOWS,
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input DBG5_GTS,
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input DBG5_GSR);
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wire SlowdownIOWriteGate;
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wire ROMWS, RAMWS, IOWS;
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CFG cfg(
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/* FSB address input */
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.A(A_FSB[23:20]),
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/* Gated address output */
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.GA23(GA23),
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.GA22(GA22),
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.GA21(DBG3_GA21),
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.GA20(DBG2_GA20),
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/* Wait state jumper inputs */
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.DBG0_ROMWS(DBG0_ROMWS),
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.DBG1_RAMWS(DBG1_RAMWS),
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.DBG4_IOWS(DBG4_IOWS),
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/* Wait state jumper outputs */
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.ROMWS(ROMWS),
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.RAMWS(RAMWS),
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.IOWS(IOWS),
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.SlowdownIOWriteGate(SlowdownIOWriteGate));
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/* GA gated (translated) address output */
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assign GA[23:22] = A_FSB[23:22];
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@ -103,7 +130,7 @@ module WarpSE(
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/* Settings register select output */
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.SetCSWR(SetCSWR));
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wire RAMReady;
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wire RAMReady, ROMReady,
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RAM ram(
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/* MC68HC000 interface */
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.CLK(FCLK),
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@ -121,8 +148,12 @@ module WarpSE(
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.RAMCS0X(RAMCS0X),
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.ROMCS(ROMCS),
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.ROMCS4X(ROMCS4X),
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/* RAM ready output */
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.RAMReady(RAMReady),
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/* RAM/ROM wait state inputs */
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.RAMWS(RAMWS),
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.ROMWS(ROMWS),
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/* RAM/ROM ready outputs */
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.RAMReady(DBG1_RAMWS),
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.ROMReady(DBG1_ROMWS),
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/* Refresh Counter Interface */
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.RefReqIn(RefReq),
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.RefUrgIn(RefUrg),
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@ -156,6 +187,8 @@ module WarpSE(
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.IOCS(IOCS),
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.IORealCS(IORealCS),
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.IOPWCS(IOPWCS),
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/* I/O wait state input */
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.IOWS(IOWS),
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/* FSB cycle termination outputs */
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.IONPReady(IONPReady),
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.IOPWReady(IOPWReady),
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@ -272,6 +305,7 @@ module WarpSE(
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.ROMCS(ROMCS4X),
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.RAMCS(RAMCS0X),
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.RAMReady(RAMReady),
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.ROMReady(ROMReady),
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.IOPWCS(IOPWCS),
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.IOPWReady(IOPWReady),
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.IONPReady(IONPReady),
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