mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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148 lines
3.3 KiB
Verilog
148 lines
3.3 KiB
Verilog
module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output reg nAS, output reg RnW, output reg nLDS, output reg nUDS, output reg nVMA,
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input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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input IOREQ, input IORW, input IOLDS, input IOUDS,
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output reg IOACT, output IODONE);
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/* C8M clock registration */
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reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
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/* I/O request input synchronization */
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reg IOREQr; always @(posedge C16M) IOREQr <= IOREQ;
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/* VPA synchronization */
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reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
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/* E clock synchronization */
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reg Er; always @(negedge C8M) begin Er <= E; end
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/* E clock state */
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reg [3:0] ES;
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always @(negedge C8M) begin
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if (!E && Er) ES <= 1;
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else if (ES==0 || ES==9) ES <= 0;
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else ES <= ES+1;
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end
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/* ETACK and VMA generation */
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wire ETACK = (ES==8) && !nVMA;
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always @(negedge C8M) begin
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if ((ES==3) && IOACT && VPAr) nVMA <= 0;
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else if (ES==0) nVMA <= 1;
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end
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/* I/O bus state */
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reg [2:0] IOS = 0;
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reg IOS0;
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/* Cycle termination signal enable */
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reg TermEN;
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always @(posedge C16M) begin
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TermEN <= IOS==2 || IOS==3 || IOS==4 || IOS==5;
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end
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/* DTACK/"ETACK"/BERR/reset falling edge synchronization */
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reg IODONEr;
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always @(negedge C8M, posedge nAS) begin
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if (nAS) IODONEr <= 0;
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else IODONEr <= TermEN && (!nDTACK || ETACK || !nBERR || !nRES);
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end
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/* DTACK/"ETACK"/BERR/reset output */
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assign IODONE = IODONEr && TermEN;
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/* I/O bus control */
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always @(posedge C16M) case (IOS[2:0])
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3'h0: begin
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if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
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IOS <= 2;
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IOS0 <= 0;
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end else begin // "regular" IOS0
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IOS <= 0;
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IOS0 <= 1;
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end
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IOACT <= IOREQr;
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ALE0 <= IOREQr;
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end 3'h2: begin
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IOS <= 3;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h3: begin
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IOS <= 4;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h4: begin
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IOS <= 5;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h5: begin
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if (!C8Mr && IODONEr) begin
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IOS <= 6;
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IOACT <= 0;
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end else begin
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IOS <= 5;
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IOACT <= 1;
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end
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IOS0 <= 0;
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ALE0 <= 1;
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end 3'h6: begin
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IOS <= 7;
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IOS0 <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end 3'h7: begin
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IOS <= 0;
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IOS0 <= 1;
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IOACT <= 0;
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ALE0 <= 0;
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end
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endcase
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/* PDS address and data latch control */
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always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
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reg DoutOE = 0;
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always @(posedge C16M) begin
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DoutOE <= (IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
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end
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assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
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/* AS, DS, RW control */
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always @(negedge C16M) begin
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nAS <= !(
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(IOS==0 && IOREQr && !C8Mr) ||
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(IOS==2) ||
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(IOS==3) ||
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(IOS==4) ||
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(IOS==5));
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RnW <= !(
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(IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(!IORW && IOS==2) ||
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(!IORW && IOS==3) ||
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(!IORW && IOS==4) ||
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(!IORW && IOS==5) ||
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(!IORW && IOS==6));
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nLDS <= !(
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(IOS==0 && IOREQr && IORW && IOLDS && !C8Mr) ||
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(IOS==2 && IOLDS) ||
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(IOS==3 && IOLDS) ||
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(IOS==4 && IOLDS) ||
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(IOS==5 && IOLDS));
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nUDS <= !(
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(IOS==0 && IOREQr && IORW && IOUDS && !C8Mr) ||
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(IOS==2 && IOUDS) ||
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(IOS==3 && IOUDS) ||
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(IOS==4 && IOUDS) ||
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(IOS==5 && IOUDS));
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end
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endmodule
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