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More /VMA setup time matching MC68k timing

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This commit is contained in:
Zane Kaminski 2024-10-07 06:09:02 -04:00
parent d1cce84963
commit b240a054f2
6 changed files with 98 additions and 81 deletions
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4
cpld/IOBM.v
View File

@ -31,8 +31,8 @@ module IOBM(
/* ETACK and VMA generation */
wire ETACK = (ES==8) && !nVMA;
always @(posedge C8M) begin
if ((ES==4) && IOACT && VPAr) nVMA <= 0;
always @(negedge C8M) begin
if ((ES==3) && IOACT && VPAr) nVMA <= 0;
else if (ES==0) nVMA <= 1;
end

4
cpld/XC95144XL/WarpSE.pad
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
10- 6-2024 11:04PM
10- 7-2024 4:59AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
@ -116,7 +116,7 @@ P95|A_FSB<2>|I|I/O|INPUT|||||||||
P96|A_FSB<3>|I|I/O|INPUT|||||||||
P97|A_FSB<4>|I|I/O|INPUT|||||||||
P98|VCC||VCCINT||||||||||
P99|RnW_IOB|O|I/O/GSR|OUTPUT|||||||||
P99|TIE||I/O/GSR||||||||||
P100|GND||GND||||||||||
To preserve the pinout above for future design iterations in

118
cpld/XC95144XL/WarpSE.syr
View File

@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: WarpSE.prj
@ -141,6 +141,7 @@ Module <FSB> is correct for synthesis.
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <QoSEN> in unit <CNT> has a constant value of 1 during circuit operation. The register is replaced by logic.
Synthesizing Unit <CS>.
Related source file is "../CS.v".
@ -152,8 +153,8 @@ Synthesizing Unit <RAM>.
Related source file is "../RAM.v".
Found 8x3-bit ROM for signal <RS$rom0000>.
Found 1-bit register for signal <nCAS>.
Found 1-bit register for signal <RAMReady>.
Found 1-bit register for signal <CASEndEN>.
Found 1-bit register for signal <RAMReadyReg>.
Found 1-bit register for signal <RASEL>.
Found 1-bit register for signal <RASEN>.
Found 1-bit register for signal <RASrf>.
@ -189,7 +190,8 @@ Synthesizing Unit <IOBS>.
Found 1-bit register for signal <nBERR_FSB>.
Found 1-bit register for signal <Clear1>.
Found 1-bit register for signal <IOACTr>.
Found 1-bit register for signal <IODONEr>.
Found 2-bit register for signal <IODONEr>.
Found 1-bit register for signal <IODONErf>.
Found 1-bit register for signal <IOL1>.
Found 1-bit register for signal <IORW1>.
Found 1-bit register for signal <IOU1>.
@ -206,19 +208,17 @@ Synthesizing Unit <IOBM>.
Found finite state machine <FSM_1> for signal <IOS>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 13 |
| Inputs | 5 |
| Transitions | 12 |
| Inputs | 4 |
| Outputs | 7 |
| Clock | C16M (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <IOBERR>.
Found 1-bit register for signal <RnW>.
Found 1-bit register for signal <IOACT>.
Found 1-bit register for signal <nAS>.
Found 1-bit register for signal <IODONE>.
Found 1-bit register for signal <nLDS>.
Found 1-bit register for signal <nUDS>.
Found 1-bit register for signal <nDinLE>.
@ -228,13 +228,14 @@ Synthesizing Unit <IOBM>.
Found 1-bit register for signal <DoutOE>.
Found 1-bit register for signal <Er>.
Found 4-bit up counter for signal <ES>.
Found 1-bit register for signal <IODONEr>.
Found 1-bit register for signal <IOREQr>.
Found 1-bit register for signal <IOS0>.
Found 1-bit register for signal <VPAr>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 15 D-type flip-flop(s).
inferred 14 D-type flip-flop(s).
Unit <IOBM> synthesized.
@ -243,7 +244,6 @@ Synthesizing Unit <CNT>.
Found 1-bit register for signal <RefUrg>.
Found 1-bit register for signal <RefReq>.
Found 1-bit register for signal <nBR_IOB>.
Found 1-bit register for signal <QoSEN>.
Found 1-bit register for signal <nRESout>.
Found 1-bit register for signal <AoutOE>.
Found 1-bit register for signal <SndQoSReady>.
@ -262,7 +262,7 @@ Synthesizing Unit <CNT>.
Found 4-bit up counter for signal <Wait>.
Summary:
inferred 5 Counter(s).
inferred 11 D-type flip-flop(s).
inferred 10 D-type flip-flop(s).
Unit <CNT> synthesized.
@ -281,14 +281,14 @@ Synthesizing Unit <WarpSE>.
Related source file is "../WarpSE.v".
WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DBG> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit tristate buffer for signal <RnW_IOB>.
WARNING:Xst:646 - Signal <RnW_IOBout> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit tristate buffer for signal <nAS_IOB>.
Found 1-bit tristate buffer for signal <nLDS_IOB>.
Found 1-bit tristate buffer for signal <nRES>.
Found 1-bit tristate buffer for signal <nUDS_IOB>.
Found 1-bit tristate buffer for signal <nVMA_IOB>.
Summary:
inferred 6 Tristate(s).
inferred 5 Tristate(s).
Unit <WarpSE> synthesized.
@ -303,13 +303,13 @@ Macro Statistics
2-bit down counter : 1
4-bit down counter : 1
4-bit up counter : 3
# Registers : 62
1-bit register : 59
2-bit register : 1
# Registers : 61
1-bit register : 57
2-bit register : 2
3-bit register : 1
4-bit register : 1
# Tristates : 6
1-bit tristate buffer : 6
# Tristates : 5
1-bit tristate buffer : 5
=========================================================================
@ -340,6 +340,13 @@ Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
10 | 11
01 | 10
-------------------
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <IORW1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <IOL1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <IOU1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <0> is unconnected in block <0>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <0> is unconnected in block <RAMReadyReg>.
=========================================================================
Advanced HDL Synthesis Report
@ -353,48 +360,60 @@ Macro Statistics
2-bit down counter : 1
4-bit down counter : 1
4-bit up counter : 3
# Registers : 47
Flip-Flops : 47
# Registers : 45
Flip-Flops : 45
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <QS_3> of sequential type is unconnected in block <CNT>.
WARNING:Xst:2677 - Node <QS_2> of sequential type is unconnected in block <CNT>.
WARNING:Xst:2677 - Node <QS_1> of sequential type is unconnected in block <CNT>.
WARNING:Xst:2677 - Node <QS_0> of sequential type is unconnected in block <CNT>.
Optimizing unit <WarpSE> ...
Optimizing unit <CS> ...
Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : TS_FSM_FFd1
Optimizing unit <FSB> ...
implementation constraint: INIT=r : ASrf
Optimizing unit <RAM> ...
Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd1
Optimizing unit <IOBM> ...
implementation constraint: INIT=s : IOS_FSM_FFd7
implementation constraint: INIT=r : IOS_FSM_FFd6
implementation constraint: INIT=r : DoutOE
implementation constraint: INIT=r : IOS_FSM_FFd5
implementation constraint: INIT=r : IOS_FSM_FFd6
implementation constraint: INIT=r : IOS_FSM_FFd1
implementation constraint: INIT=r : IOS_FSM_FFd2
implementation constraint: INIT=r : IOS_FSM_FFd3
implementation constraint: INIT=r : IOS_FSM_FFd4
implementation constraint: INIT=r : IOS_FSM_FFd5
Optimizing unit <CNT> ...
implementation constraint: INIT=r : IS_0
implementation constraint: INIT=r : IS_1
implementation constraint: INIT=r : nPOR
implementation constraint: INIT=r : Timer_2
implementation constraint: INIT=r : Timer_3
implementation constraint: INIT=r : Timer_0
implementation constraint: INIT=r : Timer_1
implementation constraint: INIT=r : Timer_3
implementation constraint: INIT=r : Timer_2
WARNING:Xst:1710 - FF/Latch <Load1> (without init value) has a constant value of 0 in block <iobs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <IORW1> (without init value) has a constant value of 0 in block <iobs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ALE1> (without init value) has a constant value of 0 in block <iobs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IOU1> (without init value) has a constant value of 0 in block <iobs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IOL1> (without init value) has a constant value of 0 in block <iobs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <RnW> of sequential type is unconnected in block <iobm>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <Clear1> is unconnected in block <iobs>.
WARNING:Xst:2677 - Node <RAMReadyReg> of sequential type is unconnected in block <ram>.
=========================================================================
* Partition Report *
@ -423,45 +442,44 @@ Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 80
# IOs : 79
Cell Usage :
# BELS : 690
# AND2 : 203
# AND3 : 34
# AND4 : 11
# BELS : 569
# AND2 : 173
# AND3 : 25
# AND4 : 10
# AND5 : 3
# AND7 : 1
# AND8 : 2
# GND : 6
# INV : 278
# OR2 : 112
# OR3 : 10
# INV : 226
# OR2 : 87
# OR3 : 9
# OR4 : 4
# VCC : 1
# XOR2 : 25
# FlipFlops/Latches : 107
# FD : 65
# FDC : 2
# FDCE : 38
# XOR2 : 22
# FlipFlops/Latches : 95
# FD : 62
# FDCE : 30
# FDCP : 1
# FDP : 1
# IO Buffers : 73
# FDP : 2
# IO Buffers : 72
# IBUF : 35
# IOBUFE : 1
# OBUF : 32
# OBUFE : 5
# OBUFE : 4
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.07 secs
Total CPU time to Xst completion: 4.90 secs
-->
Total memory usage is 262624 kilobytes
Total memory usage is 262496 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Number of warnings : 22 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

2
cpld/XC95144XL/WarpSE_build.xml
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@ -5,7 +5,7 @@
<design name='WarpSE'/>
<rptdir name='WarpSE'/>
<xilinx path='C:/Xilinx/14.7/ISE_DS/ISE;'/>
<projDir path='C:\Users\GWolf\Documents\GitHub\WarpSE-0.6c\cpld\XC95144XL'/>
<projDir path='C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL'/>
<xslDir path='chipviewer/data/xsl'/>
<fileDir path='/chipviewer/data/html'/>
<dataFile file='index.htm'/>

4
cpld/XC95144XL/WarpSE_pad.csv
View File

@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
10- 6-2024 11:04PM
10- 7-2024 4:59AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
@ -116,7 +116,7 @@ P95,A_FSB<2>,I,I/O,INPUT,,,,,,,,,
P96,A_FSB<3>,I,I/O,INPUT,,,,,,,,,
P97,A_FSB<4>,I,I/O,INPUT,,,,,,,,,
P98,VCC,,VCCINT,,,,,,,,,,
P99,RnW_IOB,O,I/O/GSR,OUTPUT,,,,,,,,,
P99,TIE,,I/O/GSR,,,,,,,,,,
P100,GND,,GND,,,,,,,,,,
To preserve the pinout above for future design iterations in

1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 10- 6-2024 11:04PM 10- 7-2024 4:59AM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
116 To preserve the pinout above for future design iterations in
117 Project Navigator simply execute the (Lock Pins) process
118 located under the (Implement Design) process in a toolbox named
119 (Optional Implementation Tools) or invoke PIN2UCF from the
120 command line. The location constraints will be written into your
121 specified UCF file
122

47
cpld/XC95144XL/WarpSE_xst.xrpt
View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sun Oct 06 23:04:26 2024">
<application stringID="Xst" timeStamp="Mon Oct 07 04:59:09 2024">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -81,14 +81,14 @@
<item dataType="int" stringID="XST_4BIT_DOWN_COUNTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="62">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="59"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_REGISTERS" value="61">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="57"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="6">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="6"/>
<item dataType="int" stringID="XST_TRISTATES" value="5">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="5"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
@ -99,8 +99,8 @@
<item dataType="int" stringID="XST_4BIT_DOWN_COUNTER" value="1"/>
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="47">
<item dataType="int" stringID="XST_FLIPFLOPS" value="47"/>
<item dataType="int" stringID="XST_REGISTERS" value="45">
<item dataType="int" stringID="XST_FLIPFLOPS" value="45"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
@ -117,26 +117,25 @@
<item stringID="XST_KEEP_HIERARCHY" value="Yes"/>
</section>
<section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="80"/>
<item stringID="XST_IOS" value="79"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="690">
<item dataType="int" stringID="XST_AND2" value="203"/>
<item dataType="int" stringID="XST_AND3" value="34"/>
<item dataType="int" stringID="XST_AND4" value="11"/>
<item dataType="int" stringID="XST_BELS" value="569">
<item dataType="int" stringID="XST_AND2" value="173"/>
<item dataType="int" stringID="XST_AND3" value="25"/>
<item dataType="int" stringID="XST_AND4" value="10"/>
<item dataType="int" stringID="XST_GND" value="6"/>
<item dataType="int" stringID="XST_INV" value="278"/>
<item dataType="int" stringID="XST_OR2" value="112"/>
<item dataType="int" stringID="XST_INV" value="226"/>
<item dataType="int" stringID="XST_OR2" value="87"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="25"/>
<item dataType="int" stringID="XST_XOR2" value="22"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="107">
<item dataType="int" stringID="XST_FD" value="65"/>
<item dataType="int" stringID="XST_FDC" value="2"/>
<item dataType="int" stringID="XST_FDCE" value="38"/>
<item dataType="int" stringID="XST_FDP" value="1"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="95">
<item dataType="int" stringID="XST_FD" value="62"/>
<item dataType="int" stringID="XST_FDCE" value="30"/>
<item dataType="int" stringID="XST_FDP" value="2"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="73">
<item dataType="int" stringID="XST_IO_BUFFERS" value="72">
<item dataType="int" stringID="XST_IBUF" value="35"/>
<item dataType="int" stringID="XST_OBUF" value="32"/>
</item>
@ -144,8 +143,8 @@
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="2"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="22"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
</section>
</application>