mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-26 06:49:15 +00:00
221 lines
8.1 KiB
Modula-2
221 lines
8.1 KiB
Modula-2
MODEL
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MODEL_VERSION "v1998.8";
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DESIGN "WarpSE";
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/* port names and type */
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INPUT S:PIN24 = A_FSB<23>;
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INPUT S:PIN20 = A_FSB<22>;
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INPUT S:PIN19 = A_FSB<21>;
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INPUT S:PIN18 = A_FSB<20>;
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INPUT S:PIN17 = A_FSB<19>;
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INPUT S:PIN16 = A_FSB<18>;
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INPUT S:PIN15 = A_FSB<17>;
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INPUT S:PIN14 = A_FSB<16>;
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INPUT S:PIN13 = A_FSB<15>;
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INPUT S:PIN11 = A_FSB<13>;
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INPUT S:PIN10 = A_FSB<12>;
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INPUT S:PIN23 = C8M;
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INPUT S:PIN22 = C16M;
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INPUT S:PIN12 = A_FSB<14>;
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INPUT S:PIN9 = A_FSB<11>;
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INPUT S:PIN8 = A_FSB<10>;
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INPUT S:PIN27 = FCLK;
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INPUT S:PIN29 = nWE_FSB;
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INPUT S:PIN32 = nAS_FSB;
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INPUT S:PIN6 = A_FSB<8>;
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INPUT S:PIN7 = A_FSB<9>;
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INPUT S:PIN76 = nBERR_IOB;
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INPUT S:PIN78 = nDTACK_IOB;
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INPUT S:PIN30 = nLDS_FSB;
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INPUT S:PIN33 = nUDS_FSB;
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INPUT S:PIN25 = E;
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INPUT S:PIN92 = nIPL2;
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INPUT S:PIN77 = nVPA_IOB;
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INPUT S:PIN94 = A_FSB<1>;
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INPUT S:PIN4 = A_FSB<7>;
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INPUT S:PIN95 = A_FSB<2>;
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INPUT S:PIN96 = A_FSB<3>;
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INPUT S:PIN97 = A_FSB<4>;
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INPUT S:PIN2 = A_FSB<5>;
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INPUT S:PIN3 = A_FSB<6>;
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TRIOUT S:PIN91 = nRES;
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TRIOUT S:PIN74 = nVMA_IOB;
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TRIOUT S:PIN81 = nAS_IOB;
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TRIOUT S:PIN79 = nLDS_IOB;
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TRIOUT S:PIN80 = nUDS_IOB;
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OUTPUT S:PIN70 = nBERR_FSB;
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OUTPUT S:PIN93 = nVPA_FSB;
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OUTPUT S:PIN64 = nRAS;
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OUTPUT S:PIN72 = nBR_IOB;
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OUTPUT S:PIN41 = RA<3>;
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OUTPUT S:PIN28 = nDTACK_FSB;
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OUTPUT S:PIN53 = RA<0>;
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OUTPUT S:PIN55 = RA<10>;
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OUTPUT S:PIN50 = RA<1>;
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OUTPUT S:PIN43 = RA<2>;
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OUTPUT S:PIN40 = RA<4>;
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OUTPUT S:PIN42 = RA<5>;
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OUTPUT S:PIN46 = RA<6>;
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OUTPUT S:PIN52 = RA<7>;
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OUTPUT S:PIN54 = RA<8>;
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OUTPUT S:PIN56 = RA<9>;
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OUTPUT S:PIN34 = nROMWE;
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OUTPUT S:PIN85 = nADoutLE0;
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OUTPUT S:PIN36 = nCAS;
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OUTPUT S:PIN86 = nDinLE;
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OUTPUT S:PIN37 = nOE;
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OUTPUT S:PIN63 = RA<11>;
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OUTPUT S:PIN82 = nADoutLE1;
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OUTPUT S:PIN87 = nAoutOE;
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OUTPUT S:PIN90 = nDinOE;
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OUTPUT S:PIN89 = nDoutOE;
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OUTPUT S:PIN65 = nRAMLWE;
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OUTPUT S:PIN66 = nRAMUWE;
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OUTPUT S:PIN35 = nROMCS;
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OUTPUT S:PIN58 = C25MEN;
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/* timing arc definitions */
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A_FSB<9>_RA<0>_delay: DELAY A_FSB<9> RA<0>;
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A_FSB<1>_RA<0>_delay: DELAY A_FSB<1> RA<0>;
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A_FSB<17>_RA<10>_delay: DELAY A_FSB<17> RA<10>;
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A_FSB<7>_RA<10>_delay: DELAY A_FSB<7> RA<10>;
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A_FSB<20>_RA<11>_delay: DELAY A_FSB<20> RA<11>;
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A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
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A_FSB<2>_RA<1>_delay: DELAY A_FSB<2> RA<1>;
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A_FSB<10>_RA<1>_delay: DELAY A_FSB<10> RA<1>;
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A_FSB<16>_RA<2>_delay: DELAY A_FSB<16> RA<2>;
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A_FSB<7>_RA<2>_delay: DELAY A_FSB<7> RA<2>;
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A_FSB<20>_RA<3>_delay: DELAY A_FSB<20> RA<3>;
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A_FSB<19>_RA<3>_delay: DELAY A_FSB<19> RA<3>;
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A_FSB<3>_RA<4>_delay: DELAY A_FSB<3> RA<4>;
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A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
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A_FSB<4>_RA<5>_delay: DELAY A_FSB<4> RA<5>;
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A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
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A_FSB<5>_RA<6>_delay: DELAY A_FSB<5> RA<6>;
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A_FSB<13>_RA<6>_delay: DELAY A_FSB<13> RA<6>;
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A_FSB<6>_RA<7>_delay: DELAY A_FSB<6> RA<7>;
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A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
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A_FSB<21>_RA<8>_delay: DELAY A_FSB<21> RA<8>;
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A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
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A_FSB<8>_RA<9>_delay: DELAY A_FSB<8> RA<9>;
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A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
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nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
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A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
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A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
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nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
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A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
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A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
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nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
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nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
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nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
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nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
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nAS_FSB_nRAS_delay: DELAY nAS_FSB nRAS;
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A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
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A_FSB<23>_nRAS_delay: DELAY A_FSB<23> nRAS;
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A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
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A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
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A_FSB<23>_nROMCS_delay: DELAY A_FSB<23> nROMCS;
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A_FSB<21>_nROMCS_delay: DELAY A_FSB<21> nROMCS;
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nWE_FSB_nROMWE_delay: DELAY nWE_FSB nROMWE;
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nAS_FSB_nROMWE_delay: DELAY nAS_FSB nROMWE;
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FCLK_nRES_delay: DELAY (ENABLE_HIGH) FCLK nRES;
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FCLK_nVMA_IOB_delay: DELAY (ENABLE_HIGH) FCLK nVMA_IOB;
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FCLK_nAS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nAS_IOB;
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FCLK_nLDS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nLDS_IOB;
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FCLK_nUDS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nUDS_IOB;
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FCLK_nBERR_FSB_delay: DELAY FCLK nBERR_FSB;
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FCLK_nVPA_FSB_delay: DELAY FCLK nVPA_FSB;
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FCLK_nRAS_delay: DELAY FCLK nRAS;
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FCLK_nBR_IOB_delay: DELAY FCLK nBR_IOB;
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FCLK_RA<3>_delay: DELAY FCLK RA<3>;
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FCLK_nDTACK_FSB_delay: DELAY FCLK nDTACK_FSB;
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FCLK_RA<0>_delay: DELAY FCLK RA<0>;
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FCLK_RA<10>_delay: DELAY FCLK RA<10>;
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FCLK_RA<1>_delay: DELAY FCLK RA<1>;
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FCLK_RA<2>_delay: DELAY FCLK RA<2>;
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FCLK_RA<4>_delay: DELAY FCLK RA<4>;
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FCLK_RA<5>_delay: DELAY FCLK RA<5>;
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FCLK_RA<6>_delay: DELAY FCLK RA<6>;
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FCLK_RA<7>_delay: DELAY FCLK RA<7>;
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FCLK_RA<8>_delay: DELAY FCLK RA<8>;
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FCLK_RA<9>_delay: DELAY FCLK RA<9>;
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FCLK_nADoutLE0_delay: DELAY FCLK nADoutLE0;
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FCLK_nCAS_delay: DELAY FCLK nCAS;
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FCLK_nOE_delay: DELAY FCLK nOE;
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FCLK_RA<11>_delay: DELAY FCLK RA<11>;
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FCLK_nADoutLE1_delay: DELAY FCLK nADoutLE1;
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FCLK_nAoutOE_delay: DELAY FCLK nAoutOE;
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FCLK_nDoutOE_delay: DELAY FCLK nDoutOE;
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FCLK_nRAMLWE_delay: DELAY FCLK nRAMLWE;
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FCLK_nRAMUWE_delay: DELAY FCLK nRAMUWE;
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FCLK_nROMCS_delay: DELAY FCLK nROMCS;
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C16M_nAS_IOB_delay: DELAY (ENABLE_HIGH) C16M nAS_IOB;
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C16M_nLDS_IOB_delay: DELAY (ENABLE_HIGH) C16M nLDS_IOB;
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C16M_nUDS_IOB_delay: DELAY (ENABLE_HIGH) C16M nUDS_IOB;
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C16M_nADoutLE0_delay: DELAY C16M nADoutLE0;
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C16M_nDinLE_delay: DELAY C16M nDinLE;
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C16M_nDoutOE_delay: DELAY C16M nDoutOE;
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C8M_nVMA_IOB_delay: DELAY (ENABLE_HIGH) C8M nVMA_IOB;
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/* timing check arc definitions */
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A_FSB<10>_FCLK_setup: SETUP(POSEDGE) A_FSB<10> FCLK;
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A_FSB<11>_FCLK_setup: SETUP(POSEDGE) A_FSB<11> FCLK;
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A_FSB<12>_FCLK_setup: SETUP(POSEDGE) A_FSB<12> FCLK;
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A_FSB<13>_FCLK_setup: SETUP(POSEDGE) A_FSB<13> FCLK;
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A_FSB<14>_FCLK_setup: SETUP(POSEDGE) A_FSB<14> FCLK;
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A_FSB<15>_FCLK_setup: SETUP(POSEDGE) A_FSB<15> FCLK;
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A_FSB<16>_FCLK_setup: SETUP(POSEDGE) A_FSB<16> FCLK;
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A_FSB<17>_FCLK_setup: SETUP(POSEDGE) A_FSB<17> FCLK;
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A_FSB<18>_FCLK_setup: SETUP(POSEDGE) A_FSB<18> FCLK;
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A_FSB<19>_FCLK_setup: SETUP(POSEDGE) A_FSB<19> FCLK;
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A_FSB<20>_FCLK_setup: SETUP(POSEDGE) A_FSB<20> FCLK;
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A_FSB<21>_FCLK_setup: SETUP(POSEDGE) A_FSB<21> FCLK;
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A_FSB<22>_FCLK_setup: SETUP(POSEDGE) A_FSB<22> FCLK;
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A_FSB<23>_FCLK_setup: SETUP(POSEDGE) A_FSB<23> FCLK;
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A_FSB<8>_FCLK_setup: SETUP(POSEDGE) A_FSB<8> FCLK;
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A_FSB<9>_FCLK_setup: SETUP(POSEDGE) A_FSB<9> FCLK;
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E_FCLK_setup: SETUP(POSEDGE) E FCLK;
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nAS_FSB_FCLK_setup: SETUP(POSEDGE) nAS_FSB FCLK;
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nIPL2_FCLK_setup: SETUP(POSEDGE) nIPL2 FCLK;
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nLDS_FSB_FCLK_setup: SETUP(POSEDGE) nLDS_FSB FCLK;
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nRES_FCLK_setup: SETUP(POSEDGE) nRES FCLK;
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nUDS_FSB_FCLK_setup: SETUP(POSEDGE) nUDS_FSB FCLK;
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nWE_FSB_FCLK_setup: SETUP(POSEDGE) nWE_FSB FCLK;
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A_FSB<10>_FCLK_hold: HOLD(POSEDGE) A_FSB<10> FCLK;
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A_FSB<11>_FCLK_hold: HOLD(POSEDGE) A_FSB<11> FCLK;
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A_FSB<12>_FCLK_hold: HOLD(POSEDGE) A_FSB<12> FCLK;
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A_FSB<13>_FCLK_hold: HOLD(POSEDGE) A_FSB<13> FCLK;
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A_FSB<14>_FCLK_hold: HOLD(POSEDGE) A_FSB<14> FCLK;
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A_FSB<15>_FCLK_hold: HOLD(POSEDGE) A_FSB<15> FCLK;
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A_FSB<16>_FCLK_hold: HOLD(POSEDGE) A_FSB<16> FCLK;
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A_FSB<17>_FCLK_hold: HOLD(POSEDGE) A_FSB<17> FCLK;
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A_FSB<18>_FCLK_hold: HOLD(POSEDGE) A_FSB<18> FCLK;
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A_FSB<19>_FCLK_hold: HOLD(POSEDGE) A_FSB<19> FCLK;
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A_FSB<20>_FCLK_hold: HOLD(POSEDGE) A_FSB<20> FCLK;
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A_FSB<21>_FCLK_hold: HOLD(POSEDGE) A_FSB<21> FCLK;
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A_FSB<22>_FCLK_hold: HOLD(POSEDGE) A_FSB<22> FCLK;
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A_FSB<23>_FCLK_hold: HOLD(POSEDGE) A_FSB<23> FCLK;
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A_FSB<8>_FCLK_hold: HOLD(POSEDGE) A_FSB<8> FCLK;
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A_FSB<9>_FCLK_hold: HOLD(POSEDGE) A_FSB<9> FCLK;
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E_FCLK_hold: HOLD(POSEDGE) E FCLK;
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nAS_FSB_FCLK_hold: HOLD(POSEDGE) nAS_FSB FCLK;
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nIPL2_FCLK_hold: HOLD(POSEDGE) nIPL2 FCLK;
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nLDS_FSB_FCLK_hold: HOLD(POSEDGE) nLDS_FSB FCLK;
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nRES_FCLK_hold: HOLD(POSEDGE) nRES FCLK;
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nUDS_FSB_FCLK_hold: HOLD(POSEDGE) nUDS_FSB FCLK;
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nWE_FSB_FCLK_hold: HOLD(POSEDGE) nWE_FSB FCLK;
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C8M_C16M_setup: SETUP(POSEDGE) C8M C16M;
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C8M_C16M_hold: HOLD(POSEDGE) C8M C16M;
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E_C8M_setup: SETUP(POSEDGE) E C8M;
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nBERR_IOB_C8M_setup: SETUP(POSEDGE) nBERR_IOB C8M;
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nDTACK_IOB_C8M_setup: SETUP(POSEDGE) nDTACK_IOB C8M;
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nRES_C8M_setup: SETUP(POSEDGE) nRES C8M;
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nVPA_IOB_C8M_setup: SETUP(POSEDGE) nVPA_IOB C8M;
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E_C8M_hold: HOLD(POSEDGE) E C8M;
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nBERR_IOB_C8M_hold: HOLD(POSEDGE) nBERR_IOB C8M;
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nDTACK_IOB_C8M_hold: HOLD(POSEDGE) nDTACK_IOB C8M;
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nRES_C8M_hold: HOLD(POSEDGE) nRES C8M;
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nVPA_IOB_C8M_hold: HOLD(POSEDGE) nVPA_IOB C8M;
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ENDMODEL
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