ASG on mac128pal.v, documentation links.
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Andrew Makousky
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@ -321,12 +321,29 @@ Peripheral device signals, input or output?
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----------
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Digital copy of _Guide to the Macintosh family hardware_ on the
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Internet Archive:
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20200905/https://archive.org/details/apple-guide-macintosh-family-hardware
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Please note: Information on how the older compact Macintosh PAL gates
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worked, which provide nearly identical functionality of the BBU.
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20201116/http://www.retro.co.za/ccc/mac/ReverseEngineering/PALs.html
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20201116/https://web.archive.org/web/20170726142931/http://www.mactech.com/articles/mactech/Vol.01/01.11/PAL/index.html
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Here are scans of one of the drafts of the Unitron's reverse
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engineering efforts for the PAL. The Unitron is the first Macintosh
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clone. Despite minor errors in some of the more difficult to reverse
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engineer equations, these equations are far more accurate than most
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third-party equation sources.
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20201120/http://www.merlintec.com/download/unitron1.pdf
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20201120/http://www.merlintec.com/download/unitron2.pdf
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Please note that I have corrected some of the errors in my simulatable
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transcribed copy of the equations into Verilog, see `mac128pal.v`.
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There is still more to learn/investigate relating to unspecified
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signals.
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@ -151,17 +151,28 @@ module lag(simclk, n_res,
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// to get at least partial behavior for analysis.
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// TODO FIXME: We trigger hsync a bit too soon at the end of the
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// scanline. And, we release it too soon at the beginning.
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// HACKED ~vclk inserted
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hsync <=
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~(viapb6 /* & ~p0q2 & s1 */ & ~vclk & va1 & va2 & va3 & va4 /* FIXME & ~va1 & ~va2 & ~va3 & ~va4 */
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~(viapb6 & ~vclk & va1 & va2 & va3 & va4 /* FIXME & va4 & ~va3 & ~va2 & va1 */
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| ~hsync & ~va4
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| ~hsync & ~va3
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| ~hsync & va2
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| ~hsync & va1);
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// TODO TEST NEATER REWRITES:
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// viapb6 <=
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// ~(~hsync & ~va4 & ~va3 & va2 & va1
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// | ~viapb6 & snddma
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// | ~viapb6 & vclk);
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// hsync <=
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// ~(~viapb6 & ~va4 & ~va3 & va2 & ~va1
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// | ~hsync & ~viapb6
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// | ~hsync & ~va4);
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s1 <=
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~(~p0q2 // 0 for processor and 1 for video
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| ~vclk
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| ~vsync & hsync
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| ~vsync & viapb6 // vertical retrace only has sound cycles
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// Next line HACKED, was: ~viapb6 & hsync & ~va4 & ~va3 & ~va2
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| ~vsync & ~viapb6 & ~hsync & va4 & va3 & va2 & va1
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| ~viapb6 & ~hsync & ~va4
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| ~viapb6 & ~hsync & va4 & ~va3 & ~va2
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@ -196,16 +207,14 @@ module lag(simclk, n_res,
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| ~viapb6 & ~va2
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| ~viapb6 & ~va3
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| ~viapb6 & ~va4);
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// TODO FIXME HACK: Previously viapb6 but negated for testing.
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snddma <=
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~(~viapb6 & va4 & ~va3 & va2 & va1 & p0q2 & vclk & ~hsync // 0 in this output
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| ~snddma & vclk); // ... indicates sound cycle
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// TODO FIXME HACK: Previously ~viapb6 but negated for testing.
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reslin <= // try to generate line 370
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~(l28
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| ~vsync
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| ~hsync // HACKED previously hsync, but negated for testing.
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| viapb6
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| viapb6 // HACKED previously ~viapb6 but negated for testing.
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| ~vclk);
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// N.B. Primary conceptual equation:
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// resnyb <=
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@ -224,6 +233,16 @@ module lag(simclk, n_res,
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| ~hsync & ~va3
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| ~va4 & va3
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| va4 & ~va3);
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// TODO TEST NEATER REWRITES:
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// ??? = /SOM . /VCLK + HS . P6 . /4 . /3 . /2 . /1
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// /RN = P2 . P6 . /4 . /3 . /2 . /1 + /RN . P2 + /RN . SOM . 4 + /RN . SOM . 3 + /RN . SOM . 2 + /RN . SOM . 1 + /RN . /P6 . HS + VCLK
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// ??? = P6 . /VCLK . /P2 . /HS . 4 . 3 . /2 . /1 + /VCLK . /P2 . /P6 . <CHOPPED OFF?>/4 . /3 . /2 . /1
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// N.B. P2 maybe shorthand for P0Q2?
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// POSSIBLY SIMPLIFIED EQUATIONS?
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// ??? = HS . 4 + HS . 3 + /HS . /4 + /4 . 3 + /HS . /3 + 4 . /3
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// ??? = [/P6 VCLK P2 2 1] + (HS + /4 + /3)(/HS + 4 . <CHOPPED OFF>
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// ??? = /VA4 * /VA3 * /HSYNC * /V <CHOPPED OFF>
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// ...<CONTINUE> VA4 * VA3 * /HSYNC * V <CHOPPED OFF>
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end
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end
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endmodule
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@ -421,6 +440,57 @@ module tsg(simclk, n_res,
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end
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endmodule
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// U11E-16R8: Analog Signal Generator
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// N.B.: ASG as a "sound generator" is largely a misnomer, it is
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// primarily a PWM disk speed generator. Therefore, the Unitron
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// didn't need an ASG because it didn't clone Apple disk drives.
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// TODO FIXME: ASG not fully implemented.
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module asg(simclk, n_res,
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sysclk, rdq0, rdq1, rdq2, rdq3, rdq4, rdq5, n_snddma, vclk, gnd,
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tsen2, n_dmald, pwm, r5, r4, r3, r2, r1, r0, vcc);
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input `virtwire simclk, n_res;
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input wire sysclk;
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input wire rdq0, rdq1, rdq2, rdq3, rdq4, rdq5, n_snddma, vclk;
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`power wire gnd;
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input wire tsen2;
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output reg n_dmald, pwm, r5, r4, r3, r2, r1, r0;
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`power wire vcc;
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// We must implement RESET for simulation or else this will never
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// stabilize.
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always @(negedge n_res) begin
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n_dmald <= 1;
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r5 <= 1; r4 <= 1; r3 <= 1; r2 <= 1; r1 <= 1; r0 <= 1;
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end
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// Simulate registered logic.
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always @(posedge sysclk) begin
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if (n_res) begin
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n_dmald <=
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~(~vclk & ~n_snddma);
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// (a ^ b) == (a | b) & ~(a & b)
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// ~~(a ^ b) == ~(~(a | b) | (a & b))
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// ~~(a ^ b) == ~((~a & ~b) | (a & b))
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// ~~(a ^ b) == ~((~a & ~(f & g & h)) | (a & (f & g & h)))
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// ~~(a ^ b) == ~((~a & (~f | ~g | ~h)) | (a & (f & g & h)))
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// ~~(a ^ b) == ~(~a & ~f | ~a & ~g | ~a & ~h | (a & (f & g & h)))
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// N.B.: This expansion almost exceeds the term limit of the
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// PAL.
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// TODO FIXME: Not in PAL equation format.
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r0 <= n_dmald & (r0 ^ ~pwm);
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r1 <= n_dmald & (r1 ^ (r0 & ~pwm));
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r2 <= n_dmald & (r2 ^ (r1 & r0 & ~pwm));
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r3 <= n_dmald & (r3 ^ (r2 & r1 & r0 & ~pwm));
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r4 <= n_dmald & (r4 ^ (r3 & r2 & r1 & r0 & ~pwm));
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r5 <= n_dmald & (r5 ^ (r4 & r3 & r2 & r1 & r0 & ~pwm));
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pwm <= n_dmald & r5 & r4 & r3 & r2 & r1 & r0;
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end
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end
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endmodule
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/* Now in order to fully implement the Macintosh's custom board
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capabilities, we must as a baseline have an implementation of some
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standard logic chips that are found on the Macintosh Main Logic
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@ -430,6 +500,9 @@ endmodule
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// Wire that PAL cluster together, along with supporting standard
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// logic chips. Here, we try to better indicate active high and
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// active low because we also need to stick in a hex inverter chip.
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//
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// Important! This is actually a board-level description of a
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// Macintosh Plus.
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module palcl(simclk, vcc, gnd, n_res, n_sysclk,
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sysclk, pclk, p0q1, clkscc, p0q2, vclk, q3, q4,
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e, keyclk,
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@ -522,8 +595,6 @@ module palcl(simclk, vcc, gnd, n_res, n_sysclk,
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// *DMALD is generated by ASG. It's very similar to how *LDPS is
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// generated.
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// n_dmald <=
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// ~(s1 & ~vclk & ~n_snddma);
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wire n_dmald;
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// u12f_tc is the carry propagation signal for the dual PWM sound
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@ -534,6 +605,8 @@ module palcl(simclk, vcc, gnd, n_res, n_sysclk,
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// This is just a pull-up resistor, possibly connected to a RESET
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// circuit.
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wire s5;
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wire tsen2; // Pull-down resistor
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wire pwm;
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// L12 => va13
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// L13 => va14
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@ -567,6 +640,8 @@ module palcl(simclk, vcc, gnd, n_res, n_sysclk,
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// S5: Pull-up resistor. TODO FIXME: Should this be controlled by
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// another thing too?
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assign s5 = vcc;
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// TSEN2: Pull-down resistorr.
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assign tsen2 = gnd;
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// TODO FIXME: A1 - A13 are connected to a pull-up resistors bank
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// RP1.
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@ -636,13 +711,9 @@ module palcl(simclk, vcc, gnd, n_res, n_sysclk,
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sysclk, n_vpa, a19, vclk, p0q1, e, keyclk, n_intscc,
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n_intvia, gnd, tsg_oe3, d0, q6, clkscc, q4, q3, viacb1,
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pclk, n_ipl0, vcc);
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// N.B.: ASG as a "sound generator" is largely a misnomer, it is
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// primarily a PWM disk speed generator.
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// TODO FIXME: ASG not implemented.
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// asg u11e(c16mf, rdq0, rdq1, rdq2, rdq3, rdq4, rdq5, n_dma, vclk, gnd,
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// tsen2, n_dmald, pwm, , , , , , , vcc);
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asg u11e(simclk, n_res,
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c16mf, rdq0, rdq1, rdq2, rdq3, rdq4, rdq5, n_snddma, vclk, gnd,
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tsen2, n_dmald, pwm, , , , , , , vcc);
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endmodule
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`endif // not MAC128PAL_V
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@ -127,7 +127,7 @@ module f32(s1a, s1b, s1y, s2a, s2b, s2y, gnd,
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endmodule
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// LS161: 4-bit binary counter.
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// Used to generate sequential video and sound RAM addresses.
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// Used to generate PWM sound signal.
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module ls161(n_clr, clk, a, b, c, d, enp, gnd,
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n_load, ent, q_d, q_c, q_b, q_a, rco, vcc);
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input wire n_clr, clk, a, b, c, d, enp;
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@ -109,10 +109,10 @@ module test_mac128pal();
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// Set simulation time limit.
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initial begin
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#1920000 $finish;
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// #1920000 $finish;
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// PLEASE NOTE: We must simulate LOTS of cycles in order to see
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// what the oscilloscope trace for one video frame looks like.
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// #30720000 $finish;
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#30720000 $finish;
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end
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// We can use `$display()` for printf-style messages and implement
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