Better BBU README documentation.
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@ -248,27 +248,41 @@ only simple, single-pin interfaces.
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Note that the BBU needs a RESET input pin for its own sake since it
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includes sequential logic to scan the CRT and sound buffers.
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* I'm assuming `*PMCYC` is an output signal? It only connects to the
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* `C2M` is an output signal, it primarily controls the address
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multiplexers to select either the row address (zero) or column
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address (one). Connecting directly to a simple 2 MHz clock could be
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adequate, or a more tailored method may be used for higher
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performance and lower memory access time.
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* `*PMCYC` is an output signal. Its primary conceptual purpose is to
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define "whose turn" it is to access DRAM, the CPU or the BBU? This
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could be as simple as a 1 MHz clock, since the CPU always takes a
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multiple of 4 clock cycles at 8 MHz to access DRAM. The symbol is
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probably short for Processor Memory CYCle. It only connects to the
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PDS slot and the F257 chips.
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----------
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Peripheral device signals, input or output?
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* `*EXT.DTK` is very likely an input signal, for PDS use. Why? The
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Macintosh Classic is essentially a stripped-down Macintosh SE that
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uses the same BBU. In that schematic, pin 11 is indicated as
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connected to a pull-up resistor. So, clearly this must be an input
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since it cannot be connected.
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Actually, the full purpose is documented right here. If this pin is
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pulled low, then the system expansion card is responsible for
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generating the `*DTACK` signal to indicate to the CPU that the data
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transfer is complete. The BBU puts the signal in a high-impedance
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state.
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* `*EXT.DTK` is an input signal, for PDS use. If this pin is pulled
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low, then the system expansion card is responsible for generating
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the `*DTACK` signal to indicate to the CPU that the data transfer is
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complete. The BBU puts the signal in a high-impedance state.
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20200808/https://web.archive.org/web/20190909060927/http://www.ccadams.org/se/pinouts.html
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However, please note that the BBU can still access DRAM on its
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regular turn to do so. The primary purpose of a PDS card driving
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`*DTACK`, of course, is for I/O-mapped I/O where the memory in
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question is hosted on the PDS card, not in the system's main DRAM.
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If the BBU were to start the process of accessing DRAM on behalf of
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the CPU, it will cancel it upon detection of this signal.
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In the Macintosh Classic schematic, this pin is connected to a
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pull-up resistor since the Classic doesn't support PDS expansion
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cards.
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* `*EAREN` is very likely an output signal (also for PDS use), for the
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reason it is not indicated in the Bomarc Macintosh Classic
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schematics, i.e. it could be disconnected entirely. Also, note that
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@ -296,5 +310,24 @@ signals.
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wired together, this probably requires circuit board changes to
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function successfully.
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* Allow the use of even faster DRAM by speeding up the BBU's internal
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timing. The internal clock would be driven by an internal
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oscillator as a phase-locked-loop on the 16 MHz external clock. The
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CPU could then be able to always access DRAM with zero wait states.
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* Add Memory Manager Unit (MMU) functionality to implement virtual
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memory.
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memory. In order to be compatible with the original MC68000, all
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the logic to handle page faults would need to be built into the BBU
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itself and the CPU is simply instructed to wait additional cycles by
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holding the `*DTACK` signal deasserted.
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* Implement bank switching to allow access to more than 4 MB of RAM
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without requiring a CPU that is capable of virtual memory. The
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original MC68000 CPU in particular does not allow for
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exception-handling that repeats execution of a faulted instruction,
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hence it is not capable of a straightforward implementation of
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virtual memory that uses page faults.
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* It could be possible to choose a FPGA with a sufficient quantity of
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SRAM (or even DRAM) stacked within it such that the physical DRAM
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sticks are not needed.
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