Fix some of the mac128pal problems.
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92edcf0931
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@ -152,7 +152,7 @@ module lag(simclk, n_res,
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// TODO FIXME: We trigger hsync a bit too soon at the end of the
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// TODO FIXME: We trigger hsync a bit too soon at the end of the
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// scanline. And, we release it too soon at the beginning.
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// scanline. And, we release it too soon at the beginning.
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hsync <=
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hsync <=
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~(viapb6 & ~p0q2 & s1 & ~va1 & ~va2 & ~va3 & ~va4
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~(viapb6 /* & ~p0q2 & s1 */ & ~vclk & va1 & va2 & va3 & va4 /* FIXME & ~va1 & ~va2 & ~va3 & ~va4 */
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| ~hsync & ~va4
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| ~hsync & ~va4
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| ~hsync & ~va3
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| ~hsync & ~va3
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| ~hsync & va2
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| ~hsync & va2
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@ -160,6 +160,10 @@ module lag(simclk, n_res,
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// TODO FIXME: This is not a synthesizable PAL equation.
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// TODO FIXME: This is not a synthesizable PAL equation.
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// TODO FIXME: This isn't generating sound buffer accesses
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// TODO FIXME: This isn't generating sound buffer accesses
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// during vertical blanking but it should be.
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// during vertical blanking but it should be.
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// This is the correct conceptual equation:
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// s1 <= ~(~p0q2 | ~vclk)
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s1 <=
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s1 <=
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~(~p0q2 // 0 for processor and 1 for video
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~(~p0q2 // 0 for processor and 1 for video
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| ~vclk
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| ~vclk
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@ -185,14 +189,21 @@ module lag(simclk, n_res,
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// to get at least partial behavior for analysis.
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// to get at least partial behavior for analysis.
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// TODO FIXME: Why this latches up and is broken, we should not
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// TODO FIXME: Why this latches up and is broken, we should not
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// use memory access to clock this to one sensitivity cycle.
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// use memory access to clock this to one sensitivity cycle.
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// TODO FIXME: Okay, this is how to do it. The trick is within
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// "self-latching" logic equations. When another clock period
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// remains the same, we use self-latching logic equations, but
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// they loose effect... okay, I don't know what I'm talking
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// about.
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viapb6 <=
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viapb6 <=
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~(~hsync // 1 indicates horizontal retrace (pseudo VA6)
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~(~hsync // 1 indicates horizontal retrace (pseudo VA6)
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| ~viapb6 & p0q2
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/* | ~viapb6 & p0q2
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| ~viapb6 & ~s1
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| ~viapb6 & ~s1 */
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| ~viapb6 & va1
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| ~viapb6 & ~vclk
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| ~viapb6 & va2
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| ~viapb6 & ~va1 // TODO FIXME wrong phase
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| ~viapb6 & va3
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| ~viapb6 & ~va2
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| ~viapb6 & va4);
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| ~viapb6 & ~va3
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| ~viapb6 & ~va4);
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// TODO FIXME HACK: Previously viapb6 but negated for testing.
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// TODO FIXME HACK: Previously viapb6 but negated for testing.
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snddma <=
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snddma <=
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~(~viapb6 & va4 & ~va3 & va2 & va1 & p0q2 & vclk & ~hsync // 0 in this output
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~(~viapb6 & va4 & ~va3 & va2 & va1 & p0q2 & vclk & ~hsync // 0 in this output
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@ -305,7 +316,12 @@ module bmu1(simclk, n_res,
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= ~(~a23 & ~a22 & ~a21 & ~as & ~ovlay // 000000
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= ~(~a23 & ~a22 & ~a21 & ~as & ~ovlay // 000000
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| ~a23 & a22 & a21 & ~as & ovlay); // (600000 with `ovlay`)
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| ~a23 & a22 & a21 & ~as & ovlay); // (600000 with `ovlay`)
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assign io1
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assign io1
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= ~(0); // TODO this indicates we're >= line 28
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= ~(~l15 & ~va9 & va8 & ~va7 // reached 368 or we don't pass line 26
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| ~l28 & ~l15
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| ~l28 & ~va9
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| ~l28 & va8
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| ~l28 & ~va7
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| ~n_res); // SIMULATION ONLY: Else we never settle.
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assign l28
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assign l28
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= ~(~l15 & ~va9 & ~va8 & va7 // reached 370 or we don't pass line 28
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= ~(~l15 & ~va9 & ~va8 & va7 // reached 370 or we don't pass line 28
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| ~l28 & ~l15
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| ~l28 & ~l15
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