mirror of
https://github.com/quorten/macsehw.git
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62d2e920e7
Much better BBU pinout chart, lots of notes learned from Guide to the Macintosh family hardware.
86 lines
4.8 KiB
Plaintext
86 lines
4.8 KiB
Plaintext
Verilog,Signal,Pin,Description,Direction,Device Connection,Device Pin,Device Signal
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ra0,RA0,79,RAM Address bit 0,inout,DRAM SIMMs
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ra1,RA1,78,RAM Address bit 1,inout,DRAM SIMMs
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ra2,RA2,76,RAM Address bit 2,inout,DRAM SIMMs
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ra3,RA3,73,RAM Address bit 3,inout,DRAM SIMMs
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ra4,RA4,71,RAM Address bit 4,inout,DRAM SIMMs
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ra5,RA5,70,RAM Address bit 5,inout,DRAM SIMMs
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ra6,RA6,68,RAM Address bit 6,inout,DRAM SIMMs
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ra8,RA8,67,RAM Address bit 8,inout,DRAM SIMMs
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ra7,RA7,66,RAM Address bit 7,output,DRAM SIMMs
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ra9,RA9,65,RAM Address bit 9,output,DRAM SIMMs
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n_cas1l,*CAS1L,16,DRAM Column Access Strobe row #2 low-byte SIMM,output,DRAM SIMMs
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n_cas0l,*CAS0L,15,DRAM Column Access Strobe row #1 low-byte SIMM,output,DRAM SIMMs
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ram_r_n_w,RAM R/*W,14,DRAM read/write,output,DRAM SIMMs
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n_ras,*RAS,20,DRAM Row Access Strobe,output,DRAM SIMMs
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n_cas1h,*CAS1H,19,DRAM Column Access Strobe row #2 high-byte SIMM,output,DRAM SIMMs
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n_cas0h,*CAS0H,18,DRAM Column Access Strobe row #1 high-byte SIMM,output,DRAM SIMMs
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rdq0,RDQ0,69,RAM Data Value bit 0,inout,DRAM SIMMs
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rdq1,RDQ1,72,RAM Data Value bit 1,inout,DRAM SIMMs
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rdq2,RDQ2,74,RAM Data Value bit 2,inout,DRAM SIMMs
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rdq3,RDQ3,75,RAM Data Value bit 3,inout,DRAM SIMMs
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rdq4,RDQ4,77,RAM Data Value bit 4,inout,DRAM SIMMs
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rdq5,RDQ5,80,RAM Data Value bit 5,inout,DRAM SIMMs
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rdq6,RDQ6,83,RAM Data Value bit 6,inout,DRAM SIMMs
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rdq7,RDQ7,2,RAM Data Value bit 7,inout,DRAM SIMMs
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rdq8,RDQ8,3,RAM Data Value bit 8,inout,DRAM SIMMs
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rdq9,RDQ9,4,RAM Data Value bit 9,inout,DRAM SIMMs
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rdq10,RDQ10,5,RAM Data Value bit 10,inout,DRAM SIMMs
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rdq11,RDQ11,6,RAM Data Value bit 11,inout,DRAM SIMMs
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rdq12,RDQ12,7,RAM Data Value bit 12,inout,DRAM SIMMs
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rdq13,RDQ13,8,RAM Data Value bit 13,inout,DRAM SIMMs
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rdq14,RDQ14,9,RAM Data Value bit 14,inout,DRAM SIMMs
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rdq15,RDQ15,10,RAM Data Value bit 15,inout,DRAM SIMMs
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n_en245,*EN245,12,Enable LS245 DRAM to CPU data bus switch,output,LS245,19,*EO
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n_dtack,*DTACK,38,CPU Data Transfer Acknowledge,inout,68000,10,*DTACK
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r_n_w,R/*W,47,CPU memory read/write,input,68000,9,R/*W
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n_ipl1,*IPL1,30,CPU Interrupt Priority Level bit 1,input,68000,24,*IPL1
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n_lds,*LDS,33,CPU Lower Data Strobe,input,68000,8,*LDS
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n_vpa,*VPA,36,CPU Valid Peripheral Address,output,68000,21,*VPA
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c8m,C8M,37,8MHz clock,output,68000,15,CLK
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null,VCC,22,+5V power,power
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null,VCC,64,+5V power,power
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null,VCC,42,+5V power,power
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null,VCC,84,+5V power,power
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mbram,MBRAM,17,1MB RAM SIMMs jumper,input,Jumper J16
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null,GND,1,Ground,power
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s64kram,64KRAM,21,UNOFFICIAL 64K RAM SIMMs jumper,input
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null,GND,43,Ground,power
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null,GND,63,Ground,power
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row2,ROW2,13,2 rows of RAM SIMMs jumper,input,Jumper J16
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n_extdtk,*EXTDTK,11,External PDS will drive *DTACK,input,PDS slot J13,B28,*EXT.DTACK
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a23,A23,23,CPU Address bit 23,input,68000,52,A23
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a22,A22,24,CPU Address bit 22,input,68000,51,A22
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a21,A21,25,CPU Address bit 21,input,68000,50,A21
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a20,A20,26,CPU Address bit 20,input,68000,48,A20
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a19,A19,27,CPU Address bit 19,input,68000,47,A19
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a17,A17,28,CPU Address bit 17,input,68000,45,A17
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a9,A9,29,CPU Address bit 9,input,68000,37,A9
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n_pmcyc,*PMCYC,81,Processor Memory CYCle,output,F257,15,*OE
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c2m,C2M,82,~2MHz DRAM row/column address selector clock,output,F257,1,S
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n_res,*RES,59,RESet,input,68000,18,*RES
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c16m,C16MRSF2,44,Filtered 16MHz clock input,input,GLU,19,FCLK
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c3_7m,C3.7M,40,~3.7MHz clock,output,"8530, ADB, GLU","20 & 28 on 8530, 16 on ADB, 9 on GLU",RTXCB
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n_romen,*ROMEN,39,ROM ENable,output,ROM,20,*CE
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n_sccrd,*SCCRD,46,Serial Communications Controller ReaD,output,8530,36,*RD
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pwm,PWM,49,Pulse Width Modulation floppy disk drive motor speed control,output,External Floppy,10,PWM
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scsidrq,SCSIDRQ,55,SCSI DMA ReQuest,input,5380,22,DRQ
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n_iwm,*IWM,48,Integrated Wozniak Machine floppy disk controller chip enable,output,IWM,7,*DEV
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n_sccen,*SCCEN,45,Serial Communications Controller chip ENable,output,8530,33,*CE
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n_scsi,*SCSI,57,SCSI chip select,output,5380,21,*CS
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n_dack,*DACK,56,SCSI DMA ACKnowledge,output,5380,26,*DACK
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sndres,SNDRES,50,SouND RESet,input,6522,17,PB7 vSndEnb
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via_cs1,VIA.CS1,58,VIA Chip Select 1,output,6522,24,CS1
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vidpg2,VIDPG2,53,VIDeo framebuffer PaGe 2,input,6522,8,PA6 vPage2
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n_earen,*EAREN,52,Unknown reserved PDS input signal,output,PDS slot J13,B11,Reserved
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n_as,*AS,41,CPU Address Strobe,input,68000,6,*AS
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n_berr,*BERR,34,CPU Bus ERRor,output,68000,22,*BERR
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snd,SND,51,PWM SouND output,output,Sound filter circuit
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n_vsync,*VSYNC,61,Video Vertical Synchronization control,output,Analog board J12,11 on J12 and 40 on 6522,CA1
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n_iow,*IOW,54,SCSI and Serial Communications Controller I/O Write,output,5380 and 8530,29 on 5380 and 35 on 8530,*IOW on 5380 and *WR on 8530
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n_hsync,*HSYNC,60,Video Horizontal Synchronization control,output,Analog board J12,10 on J12
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n_viairq,*VIAIRQ,32,VIA Interrupt ReQuest,input,6522,21,*IRQ
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vidout,VIDOUT,62,VIDeo OUTput,output,Analog board J12,9 on J12
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n_ipl0,*IPL0,31,CPU Interrupt Priority Level bit 0,output,68000,25,*IPL0
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n_uds,*UDS,35,CPU Upper Data Strobe,input,68000,7,*UDS
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