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62d2e920e7
Much better BBU pinout chart, lots of notes learned from Guide to the Macintosh family hardware.
4.8 KiB
4.8 KiB
1 | Verilog | Signal | Pin | Description | Direction | Device Connection | Device Pin | Device Signal |
---|---|---|---|---|---|---|---|---|
2 | n_en245 | *EN245 | 12 | Enable LS245 DRAM to CPU data bus switch | output | LS245 | 19 | *EO |
3 | n_dtack | *DTACK | 38 | CPU Data Transfer Acknowledge | inout | 68000 | 10 | *DTACK |
4 | r_n_w | R/*W | 47 | CPU memory read/write | input | 68000 | 9 | R/*W |
5 | n_ipl1 | *IPL1 | 30 | CPU Interrupt Priority Level bit 1 | input | 68000 | 24 | *IPL1 |
6 | n_lds | *LDS | 33 | CPU Lower Data Strobe | input | 68000 | 8 | *LDS |
7 | n_vpa | *VPA | 36 | CPU Valid Peripheral Address | output | 68000 | 21 | *VPA |
8 | c8m | C8M | 37 | 8MHz clock | output | 68000 | 15 | CLK |
9 | n_extdtk | *EXTDTK | 11 | External PDS will drive *DTACK | input | PDS slot J13 | B28 | *EXT.DTACK |
10 | a23 | A23 | 23 | CPU Address bit 23 | input | 68000 | 52 | A23 |
11 | a22 | A22 | 24 | CPU Address bit 22 | input | 68000 | 51 | A22 |
12 | a21 | A21 | 25 | CPU Address bit 21 | input | 68000 | 50 | A21 |
13 | a20 | A20 | 26 | CPU Address bit 20 | input | 68000 | 48 | A20 |
14 | a19 | A19 | 27 | CPU Address bit 19 | input | 68000 | 47 | A19 |
15 | a17 | A17 | 28 | CPU Address bit 17 | input | 68000 | 45 | A17 |
16 | a9 | A9 | 29 | CPU Address bit 9 | input | 68000 | 37 | A9 |
17 | n_pmcyc | *PMCYC | 81 | Processor Memory CYCle | output | F257 | 15 | *OE |
18 | c2m | C2M | 82 | ~2MHz DRAM row/column address selector clock | output | F257 | 1 | S |
19 | n_res | *RES | 59 | RESet | input | 68000 | 18 | *RES |
20 | c16m | C16MRSF2 | 44 | Filtered 16MHz clock input | input | GLU | 19 | FCLK |
21 | c3_7m | C3.7M | 40 | ~3.7MHz clock | output | 8530, ADB, GLU | 20 & 28 on 8530, 16 on ADB, 9 on GLU | RTXCB |
22 | n_romen | *ROMEN | 39 | ROM ENable | output | ROM | 20 | *CE |
23 | n_sccrd | *SCCRD | 46 | Serial Communications Controller ReaD | output | 8530 | 36 | *RD |
24 | pwm | PWM | 49 | Pulse Width Modulation floppy disk drive motor speed control | output | External Floppy | 10 | PWM |
25 | scsidrq | SCSIDRQ | 55 | SCSI DMA ReQuest | input | 5380 | 22 | DRQ |
26 | n_iwm | *IWM | 48 | Integrated Wozniak Machine floppy disk controller chip enable | output | IWM | 7 | *DEV |
27 | n_sccen | *SCCEN | 45 | Serial Communications Controller chip ENable | output | 8530 | 33 | *CE |
28 | n_scsi | *SCSI | 57 | SCSI chip select | output | 5380 | 21 | *CS |
29 | n_dack | *DACK | 56 | SCSI DMA ACKnowledge | output | 5380 | 26 | *DACK |
30 | sndres | SNDRES | 50 | SouND RESet | input | 6522 | 17 | PB7 vSndEnb |
31 | via_cs1 | VIA.CS1 | 58 | VIA Chip Select 1 | output | 6522 | 24 | CS1 |
32 | vidpg2 | VIDPG2 | 53 | VIDeo framebuffer PaGe 2 | input | 6522 | 8 | PA6 vPage2 |
33 | n_earen | *EAREN | 52 | Unknown reserved PDS input signal | output | PDS slot J13 | B11 | Reserved |
34 | n_as | *AS | 41 | CPU Address Strobe | input | 68000 | 6 | *AS |
35 | n_berr | *BERR | 34 | CPU Bus ERRor | output | 68000 | 22 | *BERR |
36 | n_vsync | *VSYNC | 61 | Video Vertical Synchronization control | output | Analog board J12 | 11 on J12 and 40 on 6522 | CA1 |
37 | n_iow | *IOW | 54 | SCSI and Serial Communications Controller I/O Write | output | 5380 and 8530 | 29 on 5380 and 35 on 8530 | *IOW on 5380 and *WR on 8530 |
38 | n_viairq | *VIAIRQ | 32 | VIA Interrupt ReQuest | input | 6522 | 21 | *IRQ |
39 | n_ipl0 | *IPL0 | 31 | CPU Interrupt Priority Level bit 0 | output | 68000 | 25 | *IPL0 |
40 | n_uds | *UDS | 35 | CPU Upper Data Strobe | input | 68000 | 7 | *UDS |