mirror of
https://github.com/elliotnunn/boot3.git
synced 2024-07-04 18:29:29 +00:00
323 lines
13 KiB
Plaintext
323 lines
13 KiB
Plaintext
|
;
|
|||
|
|
; File: SCSIEqu96.a
|
|||
|
|
;
|
|||
|
|
; Contains: Equates for dealing with the SCSI 53c96 chip
|
|||
|
|
;
|
|||
|
|
; Written by: Jonathan Abilay
|
|||
|
|
;
|
|||
|
|
; Copyright: <09> 1990-1993 by Apple Computer, Inc., all rights reserved.
|
|||
|
|
;
|
|||
|
|
; Change History (most recent first):
|
|||
|
|
;
|
|||
|
|
; <SM6> 2/5/93 CSS Rollin from Horror:
|
|||
|
|
; <H4> 10/17/92 jab Added some definitions required for supporting Messaging
|
|||
|
|
; correctly in Wombat.
|
|||
|
|
; <H3> 9/6/92 jab Updated from CubeE and SkyNet for BIOS SCSI.
|
|||
|
|
; <H2> 6/10/92 BG (Actually JAB) Modification of DREQ equates for SCSI access
|
|||
|
|
; through BIOS and renamed SCSIx_DAFB to SCSIx_DREQ to reflect
|
|||
|
|
; that it references the location of the DREQ bit.
|
|||
|
|
; <SM5> 10/18/92 CCH Added equates for location of SCSI DREQ bit on PDM.
|
|||
|
|
; <SM2> 7/7/92 CSS Update from Reality:
|
|||
|
|
; <2> 5/22/92 DTY #1029009 <jab>: Modification of DREQ equates for SCSI access
|
|||
|
|
; through BIOS and renamed SCSIx_DAFB to SCSIx_DREQ to reflect
|
|||
|
|
; that it references the location of the DREQ bit.
|
|||
|
|
; <SM1> 5/22/92 CSS Cyclone roll in.
|
|||
|
|
; <1> 10/24/91 SAM Rolled in Regatta file.
|
|||
|
|
;
|
|||
|
|
; Terror Change History:
|
|||
|
|
;
|
|||
|
|
; <7> 6/27/91 BG (actually PDW) Changed various clock conversion factor and
|
|||
|
|
; Selection Timeout constants to reflect real world values.
|
|||
|
|
; <6> 6/27/91 djw (actually PDW) Removed non-96 specific stuff and some
|
|||
|
|
; SCSIBusy/FreeHook stuff. Corrected values for Select timeout.
|
|||
|
|
; Added Select sequence bits in G_State96 (was G_53c80bits).
|
|||
|
|
; <5> 6/8/91 BG (actually PDW) Added tsc_cf_stg_XX equates for DAFB state
|
|||
|
|
; machine initialization.
|
|||
|
|
; <4> 3/30/91 BG (actually JMA) Added FreeHookPend bit & new values to support
|
|||
|
|
; various SCSI clks.
|
|||
|
|
; <3> 2/17/91 BG (actually JMA) Settled on final clkCnvVal & slctTimeout values,
|
|||
|
|
; also added new selector values and new max value.
|
|||
|
|
; <2> 1/5/91 BG (actually JMA) More EQUs.
|
|||
|
|
; <1> 12/7/90 JMA Added to TERROR for the first time.
|
|||
|
|
;==========================================================================
|
|||
|
|
|
|||
|
|
mgrVersion2 EQU 2 ; SCSI96 based Manager
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; SCSI 53C96 (ASC) Register Defs, Offsets
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
;EVT2/Final
|
|||
|
|
;SCSI539x1 EQU $50F0F000 ; channel 1--internal
|
|||
|
|
;SCSI539x2 EQU $50F0F402 ; channel 2--external
|
|||
|
|
|
|||
|
|
nonSerlzdDisp EQU $040000 ; disp. between serlzd and non-serlzd I/O images <T6> pdw
|
|||
|
|
|
|||
|
|
; EVT1
|
|||
|
|
;SCSI539x1 EQU $F9900000 ; channel 1--internal
|
|||
|
|
;SCSI539x2 EQU $F9900000 ; channel 2--external
|
|||
|
|
|
|||
|
|
; Turbo SCSI IIci card
|
|||
|
|
;SCSI539x0 EQU $50F30000 ; channel 1--internal
|
|||
|
|
;SCSI539x1 EQU $50F31000 ; channel 2--external
|
|||
|
|
|
|||
|
|
rXCL EQU $00 ; Transfer counter LSB (r/w)
|
|||
|
|
rXCM EQU $10 ; Transfer counter MSB (r/w)
|
|||
|
|
rFFO EQU $20 ; FIFO (r/w)
|
|||
|
|
rCMD EQU $30 ; Command (r/w)
|
|||
|
|
rCF1 EQU $80 ; Configuration 1 (r/w)
|
|||
|
|
rCF2 EQU $B0 ; Configuration 2 (r/w)
|
|||
|
|
rCF3 EQU $C0 ; Configuration 3 (r/w)
|
|||
|
|
|
|||
|
|
rSTA EQU $40 ; Status (r)
|
|||
|
|
rINT EQU $50 ; Interrupt (r)
|
|||
|
|
rSQS EQU $60 ; Sequence Step (r)
|
|||
|
|
rFOS EQU $70 ; FIFO Flags/Sequence Step (r)
|
|||
|
|
|
|||
|
|
rDID EQU $40 ; Destination Bus ID (w)
|
|||
|
|
rSTO EQU $50 ; Select/Reselect Timeout (w)
|
|||
|
|
rSYP EQU $60 ; Synchronous Period (w)
|
|||
|
|
rSYO EQU $70 ; Synchronous Offset (w)
|
|||
|
|
rCKF EQU $90 ; Clock Conversion Factor (w)
|
|||
|
|
rTST EQU $A0 ; Test (w)
|
|||
|
|
rRFO EQU $F0 ; Reserve FIFO Byte (w)
|
|||
|
|
|
|||
|
|
rDMA EQU $100 ; Pseudo-DMA regr (r/w)
|
|||
|
|
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; SCSI 53C96 (ASC) Command Set
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
;Note:
|
|||
|
|
; for NON-DMA mode, bit7=0. DMA mode command bytes have bit7=1.
|
|||
|
|
|
|||
|
|
cNOP EQU $00 ; NOP command
|
|||
|
|
cFlshFFO EQU $01 ; flush FIFO command
|
|||
|
|
cRstSChp EQU $02 ; reset SCSI chip
|
|||
|
|
cRstSBus EQU $03 ; reset SCSI bus
|
|||
|
|
|
|||
|
|
cIOXfer EQU $10 ; non-DMA Transfer command
|
|||
|
|
cCmdComp EQU $11 ; Initiator Command Complete Sequence
|
|||
|
|
cMsgAcep EQU $12 ; Message Accepted
|
|||
|
|
cSlctNoAtn EQU $41 ; Select Without ATN Sequence
|
|||
|
|
cSlctAtn EQU $42 ; Select With ATN Sequence
|
|||
|
|
cSlctAtnStp EQU $43 ; Select With ATN and Stop Sequence
|
|||
|
|
|
|||
|
|
cSetAtn EQU $1A ; Set ATN command
|
|||
|
|
cRstAtn EQU $1B ; Reset ATN command
|
|||
|
|
|
|||
|
|
cDMAXfer EQU $90 ; DMA Transfer command
|
|||
|
|
cDMASlctNoAtn EQU $C1 ; Select Without ATN Sequence, use DMA
|
|||
|
|
cDMASelWOAtn EQU $C1 ; Select Without ATN Sequence, use DMA <H3>
|
|||
|
|
cDMASelWAtn EQU $C2 ; Select With ATN Sequence, use DMA <H3>
|
|||
|
|
cDMASelWAtnStp EQU $C3 ; Select With ATN and Stop Sequence, use DMA <H4>
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; SCSI 53C96 (ASC) Bit Defs
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
; rINT bits
|
|||
|
|
bFNC EQU 3 ; function complete bit (intrp regr)
|
|||
|
|
bBSS EQU 4 ; bus service bit (intrp regr)
|
|||
|
|
bDSC EQU 5 ; disconnected bit (intrp regr)
|
|||
|
|
|
|||
|
|
dbFNC EQU bFNC+16 ; shifted 16 bits
|
|||
|
|
dbBSS EQU bBSS+16 ; shifted 16 bits
|
|||
|
|
dbDSC EQU bDSC+16 ; shifted 16 bits
|
|||
|
|
|
|||
|
|
; rSTA bits
|
|||
|
|
bTRC EQU 4 ; terminal count bit (status regr)
|
|||
|
|
bINT EQU 7 ; interrupt bit (status regr)
|
|||
|
|
|
|||
|
|
dbTRC EQU bTRC+16 ; shifted 16 bits
|
|||
|
|
dbINT EQU bINT+16 ; shifted 16 bits
|
|||
|
|
|
|||
|
|
; rINT bits
|
|||
|
|
bINTMode EQU 4 ; SCSI c9x is in initiator mode (rCMD)
|
|||
|
|
bTRGMode EQU 5 ; SCSI c9x is in target mode (rCMD)
|
|||
|
|
bDSCMode EQU 6 ; SCSI c9x is in disconnected mode (rCMD)
|
|||
|
|
|
|||
|
|
bIDENT EQU 7 ; Identify <H4>
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; SCSI 53C96 (ASC) Constants
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
iSQSMsk EQU $07 ; sequence bits mask value (rSQS) <T3>
|
|||
|
|
iSQSMsk2 EQU $E0 ; sequence bits mask value (rFOS) <T3>
|
|||
|
|
iFOFMsk EQU $1F ; FIFO count mask value (rFOS)
|
|||
|
|
iCOM EQU $80 ; completion sequence (rFOS)
|
|||
|
|
|
|||
|
|
iDcBsMsk EQU $30 ; Disconnect & Bus Service mask bits(rINT)
|
|||
|
|
iDcBsFcMsk EQU iDcBsMsk+$08 ; Disconnect, Bus Service
|
|||
|
|
; & Function complete mask bits (rINT)
|
|||
|
|
iDcBsOK EQU $10 ; not discnct + bs
|
|||
|
|
iBsFcOK EQU iDcBsOk+$08 ; not discnct + bs + fc bits (rINT)
|
|||
|
|
|
|||
|
|
|
|||
|
|
iFifoSize EQU $10 ; FIFO size in bytes
|
|||
|
|
|
|||
|
|
iPhaseMsk EQU $07 ; MASK value for phase bits
|
|||
|
|
iDataOut EQU $00 ; Data-Out SCSI Phase value
|
|||
|
|
iDataIn EQU $01 ; Data-In SCSI Phase value
|
|||
|
|
iCommand EQU $02 ; Command Phase value
|
|||
|
|
iStatus EQU $03 ; Status Phase value
|
|||
|
|
iMsgOut EQU $06 ; Msg-Out SCSI Phase value
|
|||
|
|
iMsgIn EQU $07 ; Msg-In SCSI Phase value
|
|||
|
|
|
|||
|
|
cBDR EQU $0C ; Bus Device Reset Message <H4>
|
|||
|
|
cABRT EQU $06 ; Abort Command Message <H4>
|
|||
|
|
cTERM EQU $11 ; Terminate I/O Process Message <H4>
|
|||
|
|
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; For SCSIStat result word
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
aPM EQU iPM<<8 ; assert Phase Match
|
|||
|
|
aATN EQU iATN<<8 ; assert ATN
|
|||
|
|
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; G_State96 Bit defs (bits 0-7 available)
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
HandleBusErrs EQU $7 ; Supposed to handle bus errors flag
|
|||
|
|
SelMsgOut EQU $6 ; We did the Select with ATN thing <H4>
|
|||
|
|
PendBusFree EQU $5 ; Bus Free should be expected <H4>
|
|||
|
|
FldFakeSel EQU $6 ; <SM1> CSS we failed select in cmd <P1> pdw
|
|||
|
|
OurBus EQU $5 ; <SM1> CSS we are initiator on bus <P1> pdw
|
|||
|
|
FCIntPend EQU $4 ; Functional Complete Intrp pending bit <T6> pdw
|
|||
|
|
SelInProg EQU $3 ; Select (or Select w/ATN) cmd is executing bit <T6> pdw
|
|||
|
|
NeedMsgOut EQU $2 ; we expect a msg_out phase that we need to complete the select <T6> pdw
|
|||
|
|
NeedCmdSent EQU $1 ; we expect a command phase that we need to complete the select <T6> pdw
|
|||
|
|
|
|||
|
|
FreeHookPend EQU $0 ; Free Hook pending bit %%% old vm stuff %%% <T4>
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; SCSICfg96 defs (bits 31-0 available)
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
bQuadraSCSI EQU 0 ; Quadra 700/900/950 SCSI DAFB setup <H3>
|
|||
|
|
bHasBIOS EQU 1 ; Wombat 20/25/33/40 BIOS SCSI setup <H3>
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; Miscellaneous Constants
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
SCSI0_DREQ_BIOS EQU $50F03A00 ; address to access SCSI1 DREQ bit for BIOS access <H1>
|
|||
|
|
bDREQ_BIOS EQU 0 ; SCSI DREQ status bit for BIOS access <H1>
|
|||
|
|
|
|||
|
|
SCSI0_DREQ_PDM EQU $50F26003 ; address to access SCSI1 DREQ bit for PDM <SM3>
|
|||
|
|
bDREQ_PDM EQU 0 ; SCSI DREQ status bit for PDM access <SM3>
|
|||
|
|
|
|||
|
|
SCSI0_DAFB EQU $F9800024 ; DAFB address to access SCSI1 DREQ bit <T2>
|
|||
|
|
SCSI1_DAFB EQU $F9800028 ; DAFB address to access SCSI2 DREQ bit <T2>
|
|||
|
|
bDREQ EQU 9 ; SCSI DREQ status bit <T2>
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; SCSI DAFB Regr Values <T5>
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
tsc_cf_stg_25 EQU $1EC ; DAFB state maching config value for 25 MHz CPU <T5>
|
|||
|
|
tsc_cf_stg_33 EQU $041 ; DAFB state maching config value for 33 MHz CPU <T5>
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; Debug Defs
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
overFlow EQU $0 ;
|
|||
|
|
|
|||
|
|
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
; 53C96 Regr Values
|
|||
|
|
;---------------------------------------------------
|
|||
|
|
|
|||
|
|
;Clock Conversion Values (based on SCSI chip clock - not CPU clock)
|
|||
|
|
ccf10MHz EQU $02 ; CLK conv factor 10.0Mhz
|
|||
|
|
ccf10to15MHz EQU $03 ; CLK conv factor 10.01 to 15.0Mhz
|
|||
|
|
ccf15to20MHz EQU $04 ; CLK conv factor 15.01 to 20.0Mhz
|
|||
|
|
ccf20to25MHz EQU $05 ; CLK conv factor 20.01 to 25.0Mhz
|
|||
|
|
ccf25to30MHz EQU $06 ; CLK conv factor 25.01 to 30.0Mhz
|
|||
|
|
ccf30to35MHz EQU $07 ; CLK conv factor 30.01 to 35.0Mhz <T4>
|
|||
|
|
ccf35to40MHz EQU $00 ; CLK conv factor 35.01 to 40.0Mhz (0 <- 8) <T4>
|
|||
|
|
|
|||
|
|
SelTO16Mhz EQU 126 ; ($7e) using the formula: RV (regr value) <T7>
|
|||
|
|
; 126 = (16MHz * 250mS)/ (7682 * 4) <T7>
|
|||
|
|
; 250mS is ANSI standard.
|
|||
|
|
|
|||
|
|
SelTO25Mhz EQU 167 ; ($a7) using the formula: RV (regr value)
|
|||
|
|
; 163 = (25MHz * 250mS)/ (7682 * 5)
|
|||
|
|
; 250mS is ANSI standard.
|
|||
|
|
|
|||
|
|
SelTO33Mhz EQU 167 ; ($a7) using the formula: RV (regr value) <T4> thru next <T4>
|
|||
|
|
; 153 = (33MHz * 250mS)/ (7682 * 7)
|
|||
|
|
; 250mS is ANSI standard.
|
|||
|
|
|
|||
|
|
SelTO40Mhz EQU 167 ; ($a7) using the formula: RV (regr value)
|
|||
|
|
; 163 = (40MHz * 250mS)/ (7682 * 8)
|
|||
|
|
; 250mS is ANSI standard. <T4>
|
|||
|
|
|
|||
|
|
|
|||
|
|
;Configuration 1 Regr bit defs
|
|||
|
|
SlowCableMode EQU $80 ; Slow Cable Mode enabled bit
|
|||
|
|
SCSIRstRptIntDis EQU $40 ; SCSI Reset Reporting Intrp Disabled bit
|
|||
|
|
ParityTestMode EQU $20 ; Parity Test Mode bit
|
|||
|
|
EnableParity EQU $10 ; Enable Parity Checking bit
|
|||
|
|
EnableChpTstMd EQU $08 ; Enable Chip Test Mode bit
|
|||
|
|
|
|||
|
|
myBusID EQU $07 ; My SCSI Bus ID Mask
|
|||
|
|
;myBusID EQU scDefaultID ; My SCSI Bus ID Mask
|
|||
|
|
|
|||
|
|
;Configuration 2 Regr bit defs
|
|||
|
|
RsrvFIFOByte EQU $80 ; Reserve FIFO Byte
|
|||
|
|
EnablePhsLtch EQU $40 ; Enable Phase Latch
|
|||
|
|
EnableByteCntl EQU $20 ; Enable Byte Control
|
|||
|
|
DREQHiZ EQU $10 ; DREQ High Impedance
|
|||
|
|
|
|||
|
|
SCSI2 EQU $08 ; SCSI-2 Mode
|
|||
|
|
TrgtBadPrtyAbrt EQU $04 ; Target Bad Parity Abort
|
|||
|
|
RegrPrtyEn EQU $02 ; Regr Parity Enable
|
|||
|
|
DMAPrtyEn EQU $01 ; DMA Parity Enable
|
|||
|
|
|
|||
|
|
;Configuration 3 Regr bit defs
|
|||
|
|
; bit8-3 are reserved
|
|||
|
|
SaveRsdlByte EQU $04 ; Save Residual Byte
|
|||
|
|
AltDMAMode EQU $02 ; Alternate DMA Mode
|
|||
|
|
Threshold8 EQU $01 ; Threshold 8
|
|||
|
|
|
|||
|
|
|
|||
|
|
initCF1 EQU SCSIRstRptIntDis + myBusID ; Initial CF1 value: <T6> pdw
|
|||
|
|
; 1 - slow cable mode enabled
|
|||
|
|
; 1 - disable intrp to host on bus reset
|
|||
|
|
; 0 - parity test mode disabled
|
|||
|
|
; 0 - parity checking disable
|
|||
|
|
; (ie. do not check parity on incoming data)
|
|||
|
|
; 0 - chip mode test disabled
|
|||
|
|
; 0 - use 0 as default myBusID
|
|||
|
|
|
|||
|
|
initCF2 EQU $00 ; Initial CF2 value:
|
|||
|
|
; 0 - do not reserve FIFO byte during sync xfer
|
|||
|
|
; 0 - disable phase latch
|
|||
|
|
; (Ie. status regr is a live state indicator
|
|||
|
|
; of SCSI phase lines)
|
|||
|
|
; 0 - ignore byte control inputs
|
|||
|
|
; 0 - DACK* is enabled decr the xfer counter
|
|||
|
|
; 0 - do not use SCSI-2 features
|
|||
|
|
; 0 - do not abort is parity error is detected
|
|||
|
|
; 0 - do not flag outgoing parity errs (IO-xfer)
|
|||
|
|
; 0 - do not flag outgoing parity errs (DMA-xfer)
|
|||
|
|
|
|||
|
|
initCF3 EQU SaveRsdlByte ; Initial CF3 value: <T6> pdw
|
|||
|
|
; 1 - do not assert DREQ on residual byte at end of xfer
|
|||
|
|
; 0 - disable alterante DMA mode
|
|||
|
|
; 0 - disable threshold 8 mode
|
|||
|
|
|
|||
|
|
asyncXfer EQU $0 ; Asynchronous Data Transfer = 0 Synch Offset value
|
|||
|
|
; a non-zero value indicates Synch data xfer
|
|||
|
|
|
|||
|
|
initOp EQU asyncXfer ; use this operation
|
|||
|
|
|
|||
|
|
clkCnvVal EQU ccf20to25MHz ; use this clock conversion factor <T3>
|
|||
|
|
slctTimeout EQU SelTO25Mhz ; use this Select timeout value <T3>
|
|||
|
|
|
|||
|
|
|