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Resource forks are included only for .rsrc files. These are DeRezzed into their data fork. 'ckid' resources, from the Projector VCS, are not included. The Tools directory, containing mostly junk, is also excluded.
221 lines
7.5 KiB
Plaintext
221 lines
7.5 KiB
Plaintext
;EASE$$$ READ ONLY COPY of file ÒIOPDefs.aiiÓ
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; 1.2 CCH 07/08/1989 Added EASE comments to file.
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;¥1.1 GGD 06/15/1989 Updated to use equates for the latest rev of the IOP chip,
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; re-formated tab stops in source.
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; 1.0 CCH 11/ 9/1988 Adding to EASE.
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; END EASE MODIFICATION HISTORY
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macro
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assert &boolExpr
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if not(&Eval(&boolExpr)) then
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aerror &concat('Assertion Failed - ',&boolExpr)
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endif
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endm
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; 65C02 definitions
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pswC equ %00000001 ; carry bit
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pswZ equ %00000010 ; zero bit
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pswI equ %00000100 ; interrupt bit
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pswD equ %00001000 ; decimal bit
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pswB equ %00010000 ; break bit
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psw5 equ %00100000 ; bit 5 unused
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pswV equ %01000000 ; overflow bit
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pswN equ %10000000 ; negative bit
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StackPage equ $0100 ; page 1 is the stack
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vNMI equ $FFFA ; non-maskable interrupt
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vRESET equ $FFFC ; reset vector
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vINT equ $FFFE ; interrupt vector
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; IOP Hardware offsets
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IOBase equ $F000 ; base of I/O space
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; TIMER Hardware Control
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TimerCounterL equ IOBase+$10 ; (RW) Timer low counter (latch on write)
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TimerCounterH equ IOBase+$11 ; (RW) Timer high counter (load on write)
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TimerLatchL equ IOBase+$12 ; (RW) Timer low latch
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TimerLatchH equ IOBase+$13 ; (RW) Timer high latch
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; DMA Hardware Control
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DMA1Control equ IOBase+$20 ; (RW) DMA channel 1 control
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DMAEN1 equ %00000001 ; enable DMA channel 1
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DREQ1 equ %00000010 ; DMA request 1 active
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DMADIR1 equ %00000100 ; transfer I/O to RAM
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DEN1ON2 equ %00001000 ; start DMA 1 after DMA 2 complete
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IOA1 equ %00010000 ; DMA I/O address
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DMA1RAMAddressL equ IOBase+$21 ; (RW) DMA channel 1 RAM address low byte
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DMA1RAMAddressH equ IOBase+$22 ; (RW) DMA channel 1 RAM address high byte
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DMA1XferCountL equ IOBase+$23 ; (RW) DMA channel 1 transfer count low byte
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DMA1XferCountH equ IOBase+$24 ; (RW) DMA channel 1 transfer count high byte
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DMA2Control equ IOBase+$28 ; (RW) DMA channel 2 control
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DMAEN2 equ %00000001 ; enable DMA channel 2
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DREQ2 equ %00000010 ; DMA request 2 active
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DMADIR2 equ %00000100 ; transfer I/O to RAM
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DEN2ON1 equ %00001000 ; start DMA 2 after DMA 1 complete
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IOA2 equ %00010000 ; DMA I/O address
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DMA2RAMAddressL equ IOBase+$29 ; (RW) DMA channel 2 RAM address low byte
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DMA2RAMAddressH equ IOBase+$2A ; (RW) DMA channel 2 RAM address high byte
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DMA2XferCountL equ IOBase+$2B ; (RW) DMA channel 2 transfer count low byte
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DMA2XferCountH equ IOBase+$2C ; (RW) DMA channel 2 transfer count high byte
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; Miscelaneous Hardware Control
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SCCControlReg equ IOBase+$30 ; (RW) SCC control register
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BYPASS equ %00000001 ; Host processor controls SCC/ISM
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SCCISM equ %00000010 ; ISM port
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* equ %00000100 ; unused
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RTXCA equ %00001000 ; selects SCC channel A clock source
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RTXCB equ %00100000 ; selects SCC channel B clock source
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GPOUT1 equ %10000000 ; general purpose output 1
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RTXC3MHz equ %00 ; 3.6864MHz
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RTXCDPCLK equ %01 ; DPCLK/10
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RTXCDPLLOut equ %10 ; Digital phase locked loop output
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RTXCGPI equ %11 ; GPIA or GPIB
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IOControlReg equ IOBase+$31 ; (RW) I/O Control register
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IODurationCount equ %00000001 ; I/O duration count
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IODelayCount equ %00010000 ; I/O delay count
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TimerDPLLctl equ IOBase+$32 ; (RW) Timer/DPLL control
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CONT equ %00000001 ; timer continuous mode
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GPOUT0 equ %00000010 ; general purpose output 0
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GPIN0 equ %00000100 ; general purpose input 0
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GPIN1 equ %00001000 ; general purpose input 1
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DPLL1EN equ %00010000 ; DPLL 1 enabled
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CRSNS1 equ %00100000 ; carrier present on RXDA
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DPLL2EN equ %01000000 ; DPLL 2 enabled
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CRSNS2 equ %10000000 ; carrier present on RXDB
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InterruptMask equ IOBase+$33 ; (RW) Interrupt Mask Register
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DMA1ENI equ %00000010 ; enable DMA channel 1 interrupts
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DMA2ENI equ %00000100 ; enable DMA channel 2 interrupts
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SCCENI equ %00001000 ; enable SCC interrupts
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HSTENI equ %00010000 ; enable interrupts from the host processor
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TMRENI equ %00100000 ; enable timer interrupts
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InterruptReg equ IOBase+$34 ; (RW) Interrupt Register
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DMA1INT equ %00000010 ; DMA channel 1 interrupt
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DMA2INT equ %00000100 ; DMA channel 2 interrupt
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SCCINT equ %00001000 ; SCC interrupt
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HSTINT equ %00010000 ; interrupt from the host processor
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TMRINT equ %00100000 ; timer interrupt
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HostControl equ IOBase+$35 ; (RW) Host Register
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INTHST0 equ %00000100 ; host interrupt 0 active
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INTHST1 equ %00001000 ; host interrupt 1 active
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MsgCompletedINT equ INTHST0 ; indicates message in MessageCompleted state
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NewMsgSentINT equ INTHST1 ; indicates message in NewMessageSent state
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; IOP Shared Memory Addresses
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RCVMsgBase equ $0200 ; receive message page
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RCVMsgMax equ RCVMsgBase+$00 ; Highest receive message number
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RCVMsg1State equ RCVMsgBase+$01 ; receive message 1 state
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RCVMsg2State equ RCVMsgBase+$02 ; receive message 2 state
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RCVMsg3State equ RCVMsgBase+$03 ; receive message 3 state
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RCVMsg4State equ RCVMsgBase+$04 ; receive message 4 state
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RCVMsg5State equ RCVMsgBase+$05 ; receive message 5 state
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RCVMsg6State equ RCVMsgBase+$06 ; receive message 6 state
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RCVMsg7State equ RCVMsgBase+$07 ; receive message 7 state
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PatchReq equ RCVMsgBase+$1F ; Host wants to patch IOP code
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RCVMsg1Data equ RCVMsgBase+$20 ; receive message 1 data
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RCVMsg2Data equ RCVMsgBase+$40 ; receive message 2 data
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RCVMsg3Data equ RCVMsgBase+$60 ; receive message 3 data
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RCVMsg4Data equ RCVMsgBase+$80 ; receive message 4 data
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RCVMsg5Data equ RCVMsgBase+$A0 ; receive message 5 data
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RCVMsg6Data equ RCVMsgBase+$C0 ; receive message 6 data
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RCVMsg7Data equ RCVMsgBase+$E0 ; receive message 7 data
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XMTMsgBase equ $0300 ; transmit message page
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XMTMsgMax equ XMTMsgBase+$00 ; Highest transmit message number
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XMTMsg1State equ XMTMsgBase+$01 ; transmit message 1 state
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XMTMsg2State equ XMTMsgBase+$02 ; transmit message 2 state
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XMTMsg3State equ XMTMsgBase+$03 ; transmit message 3 state
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XMTMsg4State equ XMTMsgBase+$04 ; transmit message 4 state
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XMTMsg5State equ XMTMsgBase+$05 ; transmit message 5 state
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XMTMsg6State equ XMTMsgBase+$06 ; transmit message 6 state
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XMTMsg7State equ XMTMsgBase+$07 ; transmit message 7 state
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Alive equ XMTMsgBase+$1F ; IOP is alive flag
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XMTMsg1Data equ XMTMsgBase+$20 ; transmit message 1 data
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XMTMsg2Data equ XMTMsgBase+$40 ; transmit message 2 data
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XMTMsg3Data equ XMTMsgBase+$60 ; transmit message 3 data
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XMTMsg4Data equ XMTMsgBase+$80 ; transmit message 4 data
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XMTMsg5Data equ XMTMsgBase+$A0 ; transmit message 5 data
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XMTMsg6Data equ XMTMsgBase+$C0 ; transmit message 6 data
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XMTMsg7Data equ XMTMsgBase+$E0 ; transmit message 7 data
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; IOP Message States
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Idle equ 0 ; message buffer idle
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NewMessageSent equ 1 ; new message arrived
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MessageReceived equ 2 ; message being processed
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MessageCompleted equ 3 ; request completed
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; Block Copy Message Assignments
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BCxmtState equ XMTMsg1State
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BCxmtData equ XMTMsg1Data
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; Block Copy Driver request format
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bcIOPtoHOST equ $00
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bcHOSTtoIOP equ $01
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bcCompare equ $02
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bcReqCmd equ BCxmtData+$00 ; (byte) Request Kind
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bcReqByteCount equ BCxmtData+$02 ; (word) transfer byte count
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bcReqHostAddr equ BCxmtData+$04 ; (long) host RAM address
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bcReqIopAddr equ BCxmtData+$08 ; (word) IOP RAM address
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bcReqCompRel equ BCxmtData+$0A ; (byte) Compare Relation (output)
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; TMPB Time constants (1 tick = 256 clocks @1.9584MHz = 130.71895 uSec)
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TMPB1second equ 7650 ; 1 second
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TMPB100ms equ TMPB1second/10 ; 100 milliseconds
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TMPB10ms equ TMPB1second/100 ; 10 milliseconds
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TMPB1ms equ TMPB1second/1000 ; 1 millisecond
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