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232 lines
6.9 KiB
Plaintext
232 lines
6.9 KiB
Plaintext
;
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; File: XOvfl.a
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;
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; Contains: Routines to handle the FP Overflow exception
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;
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; Originally Written by: Motorola Inc.
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; Adapted to Apple/MPW: Jon Okada
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;
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; Copyright: © 1990, 1991 by Apple Computer, Inc., all rights reserved.
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;
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; This file is used in these builds: Mac32
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;
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; Change History (most recent first):
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;
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; <2+> 6/24/91 BG Force vectoring to user INEX handler for OVFL if
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; OVFL is not enabled but INEX2 is enabled (per
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; Motorola release 2.0).
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; <2> 3/30/91 BG Rolling in Jon Okada's latest changes.
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; <1> 12/14/90 BG First checked into TERROR/BBS.
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; xovfl.a
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; Based upon Motorola file 'x_ovfl.sa'.
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; CHANGE LOG:
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; 08 Jan 91 JPO Inserted label "ovfl" at top of code. Deleted
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; label "take_inex" (not referenced). Renamed
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; labels "no_e3_1", "ck_inex", "no_e3_2", "e1_set",
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; and "not_opc011" to "ofno_e3_1", "ofck_inex",
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; "ofno_e3_2", "ofe1_set", and "ofnot_opc011",
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; respectively. Modified code to branch to user
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; handlers for OVFL and INEX. Changed "bra fpsp_done"
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; to "rte".
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; 04 Mar 91 JPO Changed source of destination registers from CMDREG1B
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; to CMDREG3B for E3 exceptions.
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; 10 Jun 91 JPO Force vectoring to user INEX handler for OVFL if
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; OVFL is not enabled but INEX2 is enabled (per
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; Motorola release 2.0).
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;
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*
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* x_ovfl.sa 3.1 12/10/90
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*
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* fpsp_ovfl --- FPSP handler for overflow exception
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*
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* Overflow occurs when a floating-point intermediate result is
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* too large to be represented in a floating-point data register,
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* or when storing to memory, the contents of a floating-point
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* data register are too large to be represented in the
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* destination format.
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*
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* Trap disabled results
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*
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* If the instruction is move_out, then garbage is stored in the
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* destination. If the instruction is not move_out, then the
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* destination is not affected. For 68881 compatibility, the
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* following values should be stored at the destination, based
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* on the current rounding mode:
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*
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* RN Infinity with the sign of the intermediate result.
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* RZ Largest magnitude number, with the sign of the
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* intermediate result.
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* RM For pos overflow, the largest pos number. For neg overflow,
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* -infinity
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* RP For pos overflow, +infinity. For neg overflow, the largest
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* neg number
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*
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* Trap enabled results
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* All trap disabled code applies. In addition the exceptional
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* operand needs to be made available to the users exception handler
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* with a bias of $6000 subtracted from the exponent.
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*
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*
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* Copyright (C) Motorola, Inc. 1990
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* All Rights Reserved
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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* The copyright notice above does not evidence any
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* actual or intended publication of such source code.
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* X_OVFL IDNT 2,1 Motorola 040 Floating Point Software Package
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ovfl: ; <1/8/91, JPO>
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fpsp_ovfl:
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link a6,#-LOCAL_SIZE
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fsave -(a7)
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movem.l d0-d1/a0-a1,USER_DA(a6)
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fmovem.x fp0-fp3,USER_FP0(a6)
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fmovem.l fpcr/fpsr/fpiar,USER_FPCR(a6)
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*
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* The 040 doesn't set the AINEX bit in the FPSR, the following
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* line temporarily rectifies this error.
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*
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bset.b #ainex_bit,FPSR_AEXCEPT(a6)
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*
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bsr ovf_adj ;denormalize, round & store interm op
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*
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* if overflow traps not enabled check for inexact exception
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*
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btst.b #ovfl_bit,FPCR_ENABLE(a6)
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beq.b ofck_inex ; label renamed <1/8/91, JPO>
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*
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btst.b #E3,E_BYTE(a6)
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beq.b ofno_e3_1 ; label renamed <1/8/91, JPO>
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; bfextu CMDREG1B(a6){6:3},d0 ;get dest reg no - DELETED <3/4/91, JPO>
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bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no <3/4/91, JPO>
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bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
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bsr b1238_fix
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move.l USER_FPSR(a6),FPSR_SHADOW(a6)
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or.l #sx_mask,E_BYTE(a6)
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ofno_e3_1: ; label renamed <1/8/91, JPO>
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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frestore (a7)+
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unlk a6
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; bra.l real_ovfl ; deleted <1/8/91, JPO>
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move.l (FPOVFL_VEC040).W,-(sp) ; push vector to user OVFL handler <1/8/91, JPO>
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rts ; execute user handler <1/8/91, JPO>
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*
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* It is possible to have either inex2 or inex1 exceptions with the
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* ovfl. If the inex enable bit is set in the FPCR, and either
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* inex2 or inex1 occured, we must clean up and branch to the
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* real inex handler.
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*
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;
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; Enabled INEX2 trap must occur for overflow if ovfl is not enabled <6/10/91, JPO>
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;
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ofck_inex: ; label renamed <1/8/91, JPO>
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; move.b FPCR_ENABLE(a6),d0 ; DELETED <6/10/91, JPO> <T3>
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; and.b FPSR_EXCEPT(a6),d0 ; DELETED <6/10/91, JPO> <T3>
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; andi.b #$3,d0 ; DELETED <6/10/91, JPO> <T3>
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btst.b #inex2_bit,FPCR_ENABLE(a6); added <6/10/91, JPO> <T3>
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beq.b ovfl_exit
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*
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* Inexact enabled and reported, and we must take an inexact exception.
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*
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;take_inex: ; label deleted <1/8/91, JPO>
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btst.b #E3,E_BYTE(a6)
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beq.b ofno_e3_2 ; label renamed <1/8/91, JPO>
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; bfextu CMDREG1B(a6){6:3},d0 ;get dest reg no - DELETED <3/4/91, JPO>
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bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no <3/4/91, JPO>
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bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
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bsr b1238_fix
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move.l USER_FPSR(a6),FPSR_SHADOW(a6)
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or.l #sx_mask,E_BYTE(a6)
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ofno_e3_2: ; label renamed <1/8/91, JPO>
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move.b #INEX_VEC,EXC_VEC+1(a6)
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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frestore (a7)+
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unlk a6
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; bra.l real_inex ; deleted <1/8/91, JPO>
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move.l ($00C4).W,-(sp) ; push vector to user INEX handler <1/8/91, JPO>
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rts ; execute user handler <1/8/91, JPO>
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ovfl_exit:
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bclr.b #E3,E_BYTE(a6) ;test and clear E3 bit
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beq.b ofe1_set ; label renamed <1/8/91, JPO>
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*
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* Clear dirty bit on dest register in the frame before branching
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* to b1238_fix.
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*
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; bfextu CMDREG1B(a6){6:3},d0 ;get dest reg no - DELETED <3/4/91, JPO>
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bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no <3/4/91, JPO>
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bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
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bsr b1238_fix ;test for bug1238 case
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move.l USER_FPSR(a6),FPSR_SHADOW(a6)
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or.l #sx_mask,E_BYTE(a6)
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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frestore (a7)+
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unlk a6
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; bra.l fpsp_done ; deleted <1/8/91, JPO>
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rte ; <1/8/91, JPO>
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ofe1_set: ; label renamed <1/8/91, JPO>
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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unlk a6
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; bra.l fpsp_done ; deleted <1/8/91, JPO>
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rte ; <1/8/91, JPO>
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*
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* ovf_adj
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*
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ovf_adj:
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*
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* Have a0 point to the correct operand.
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*
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btst.b #E3,E_BYTE(a6) ;test E3 bit
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beq.b ovf_e1
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lea WBTEMP(a6),a0
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bra.b ovf_com
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ovf_e1:
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lea ETEMP(a6),a0
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ovf_com:
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bclr.b #sign_bit,LOCAL_EX(a0)
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sne LOCAL_SGN(a0)
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bsr g_opcls ;returns opclass in d0
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cmpi.w #3,d0 ;check for opclass3
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bne.b ofnot_opc011 ; label renamed <1/8/91, JPO>
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*
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* FPSR_CC is saved and restored because ovf_r_x3 affects it. The
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* CCs are defined to be 'not affected' for the opclass3 instruction.
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*
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move.b FPSR_CC(a6),L_SCR1(a6)
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bsr ovf_r_x3 ;returns a0 pointing to result
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move.b L_SCR1(a6),FPSR_CC(a6)
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bra store ;stores to memory or register
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ofnot_opc011: ; label renamed <1/8/91, JPO>
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bsr ovf_r_x2 ;returns a0 pointing to result
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bra store ;stores to memory or register
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