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542 lines
16 KiB
Plaintext
542 lines
16 KiB
Plaintext
;
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; File: HALc96Init.a
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;
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; Contains: initialization routines
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;
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; Written by: Paul Wolf
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;
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; Copyright: © 1992-1994 by Apple Computer, Inc., All rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM30> 1/25/94 DCB Initialize our null deferred task which we use to make sure that
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; jDisptch gets called in order to run our own DT Manager
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; <SM29> 12/19/93 DCB Clear our deferred task flags field before using it.
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; <SM28> 11/22/93 pdw Rolling in from <MCxx>.
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; <MC10> 11/8/93 pdw Fixed the bug that Craig reported but I didn't understand until
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; now.
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; <MC8> 10/29/93 pdw Added initialization of dmaAlignMask from dmaAlignmentSize.
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; <SM27> 11/19/93 chp Beautify some conditional code that sometimes needs to branch
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; around TNT code.
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; <SM26> 11/17/93 KW changed forSTP601 to forSTP601v1
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; <SMG3> 9/29/93 chp Add Grand Central DMA sub-transfer routine initialization.
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; <SM24> 11/9/93 KW for the CygnusX1 ROM, use SlowRead96 instead of FastRead_96_BIOS
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; until we get our new BTU chip
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; <SM23> 10/29/93 DCB Initializing our Deferred Task queue element which is used in
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; the pseudo-DMA data transfer routines to lower the interrupt
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; level.
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; <MC7> 10/28/93 pdw Rearranged some vectors, fixed up the forPDMProto stuff again.
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; <SM22> 10/14/93 pdw <MC> roll-in.
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; <MC6> 10/12/93 pdw Changed a .s to a .w to fix another build problem.
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; <MC5> 10/12/93 pdw Added support for Synchronous data transfers, rewrote State
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; Machine, message handling etc.
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; <MC4> 10/6/93 pdw Fixed forPDMProto stuff.
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; <MC3> 10/4/93 RC Put forPDMProto around AMIC3/2 special code
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; <MC2> 9/17/93 pdw Removed exception for Cold Fusion in PRAM check for disabling
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; DMA read.
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; <SM21> 9/12/93 pdw Got rid of vector for HALtransfer since the routine is gone.
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; <SM20> 9/9/93 pdw Lots of little changes. Name changes, temporary cache_bug
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; stuff.
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; <SM19> 7/20/93 pdw Changed DMA-disabling/enabling PRAM interpretation. Now it
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; defaults to (in zero case) the fastest, safe means. For EVT3s
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; this means DMA for all others (including Cold Fusion), this
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; means pseudo-DMA.
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; <SM18> 7/17/93 pdw Lots of little things.
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; <SM17> 7/8/93 pdw Replaced slow DMA routines with SlowRead96 until I fix the
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; residual length problems with the DMA routines.
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; <SM16> 6/29/93 pdw Massive checkins: Change asynchronicity mechanism to CallMachine
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; stack switching mechanism. Adding support for Cold Fusion.
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; Rearranging HW/SW Init code. Some code optimizations.
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; <SM15> 5/25/93 DCB Rollin from Ludwig. (The next item below)
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; <LW10> 5/21/93 PW Adding PRAM selectable Initiator ID stuff.
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; <SM14> 5/5/93 PW Converted names to meanies-friendly names. Updated with latest
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; from Ludwig stuff.
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; <SM13> 4/8/93 DCB Added Initialization code for Wombat class machines.
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; <LW9> 5/1/93 PW Put IF RECORD_ON around the initial RecordEvent call.
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; <LW8> 4/30/93 DCB Getting rid of Info HalAction vector. It is getting its own
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; entry point into the HAL to prevent deadlocks.
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; <LW7> 4/30/93 PW Added some extra fields in jump table for future use.
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; <LW5> 4/14/93 DCB Added jump table vector for SetParity
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; <SM12> 3/29/93 PW Added PDM test code to turn on real DMA reads and/or real DMA
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; writes if certain PRAM bits are set.
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; <LW4> 3/26/93 PW Added code to initialize new DMA vectors.
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; <SM10> 3/23/93 DCB Removed a reference to the old SCSI Globals which aren't
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; supported anymore.
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; <SM9> 3/23/93 PW Removing RejectMsg stuff.
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; <SM8> 3/20/93 PW Unknown changes.
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; <LW3> 2/17/93 PW For PDM: replaces Fast with Slow routines since they have
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; trouble with DREQ.
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; <SM7> 1/31/93 PW Update from the latest of Ludwig. Also changes required for PDM
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; (will update Ludwig with these as needed myself).
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; <LW2> 1/27/93 PW Added dispatch tables for InitDataPointer and DoData routines.
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; <SM6> 10/30/92 DCB Added Setup and Teardown routines to support Direct DMA into a
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; user buffer
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; <SM5> 10/8/92 PW Got rid of unused third Read and Write transfer routine vectors.
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; <SM4> 8/30/92 PW Added kAssertATN to dispatch list.
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; <SM3> 8/20/92 DCB Fixed SCSI Bus Reset
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; <SM2> 7/27/92 PW Virtually initial check-in.
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;
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;==========================================================================
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BLANKS ON ; assembler accepts spaces & tabs in operand field
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PRINT OFF ; do not send subsequent lines to the listing file
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; don't print includes
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CACHEBUG EQU 0 ;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥
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LOAD 'StandardEqu.d'
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INCLUDE 'HardwarePrivateEqu.a'
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INCLUDE 'UniversalEqu.a' ; for TestFor
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INCLUDE 'DeferredTaskEqu.a'
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INCLUDE 'Debug.a' ; for NAME macro
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INCLUDE 'SCSI.a'
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INCLUDE 'SCSIEqu53c96.a'
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INCLUDE 'HALc96equ.a'
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INCLUDE 'ACAM.a'
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INCLUDE 'XPTEqu.a'
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PRINT ON ; do send subsequent lines to the listing files
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CASE OBJECT
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HALc96Init PROC EXPORT ;
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EXPORT Initc96Asm
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; From SCSIMgr96.a ---
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IMPORT CyclePhase ;
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IMPORT DoSCSIMsgIn
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; From SCSIMgrHW96.a ---
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IMPORT BusErrHandler96, Install_ISR
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IMPORT DoInitiate
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IMPORT DoBitBucket
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IMPORT DoDataIn
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IMPORT DoDataOut
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IMPORT DoAcceptMsg
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IMPORT DoMsgOut
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IMPORT DoStatus
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IMPORT DoComplete
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IMPORT DoSaveDataPointer
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IMPORT DoModifyDataPointer
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IMPORT DoRestorePointers
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IMPORT GetReconnectInfo
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IMPORT GetSelectInfo
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IMPORT DoSelect
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IMPORT DoCommand
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IMPORT DoHalInfo
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IMPORT DoReset
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IMPORT DoAssertATN
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IMPORT SlowRead96
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IMPORT SlowWrite96
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IMPORT FastRead96
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IMPORT FastWrite96
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IMPORT TeardownIO ; <SM6> DCB
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IMPORT SetParity ; <LW5> DCB
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IMPORT InitDataTIB
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IMPORT InitDataBuffer
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IMPORT InitDataSG
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IMPORT DoDataTIB
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IMPORT DoDataBuffer
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IMPORT DoDataSG
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IMPORT StartPSC, StopPSCRead, StopPSCWrite, Wt4PSCComplete
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IMPORT StartAMIC, StopAMICRead, StopAMICWrite, Wt4AMICComplete
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IMPORT StartGC, StopGCRead, StopGCWrite, Wt4GCComplete
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IMPORT FastRead_96_BIOS,FastWrite_96_BIOS
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IMPORT DataIn_DMA, DataIn_DMA1x1, DataOut_DMA
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IMPORT SetupIOPSC, TeardownIOPSC
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IMPORT SetupIOAMIC, TeardownIOAMIC
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IMPORT SetupIOGC, TeardownIOGC
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IMPORT SetupIONoDMA, TeardownIONoDMA
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IMPORT AutoMsgIn, HandleSelected
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IMPORT Wt4SelectComplete
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IMPORT HandleBusInt
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IMPORT RecordEvent
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IMPORT DataDTask,ci_jDisptch_Vers,ci_jDisptch
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IMPORT oldjDisptch
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WITH HALc96GlobalRecord
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;-------------------------------------------------------------
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;
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Macro
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DispatchVector &ROMAddress
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IF forC96Init OR forROM THEN ;
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dc.l &ROMAddress-Initc96Asm
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ELSE
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dcImportResident &ROMAddress
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ENDIF
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EndM
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OffsetTbl96
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;ÑÑÑ Externals (Entry points)
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DispatchVector DoInitiate
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DispatchVector DoBitBucket
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DispatchVector DoDataIn
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DispatchVector DoDataOut
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DispatchVector DoAcceptMsg
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DispatchVector unusedVector
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DispatchVector unusedVector
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DispatchVector DoMsgOut
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DispatchVector DoStatus
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DispatchVector DoComplete
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DispatchVector DoSaveDataPointer
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DispatchVector DoModifyDataPointer
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DispatchVector DoRestorePointers
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DispatchVector GetReconnectInfo
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DispatchVector GetSelectInfo
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DispatchVector DoSelect
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DispatchVector unusedVector
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DispatchVector DoCommand
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DispatchVector SetParity ; <LW5> DCB
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DispatchVector HandleSelected
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DispatchVector SetupIONoDMA
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DispatchVector DoReset
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DispatchVector DoAssertATN ; <SM4> pdw
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DispatchVector TeardownIONoDMA
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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DispatchVector unusedVector ; unused for now
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;ÑÑÑ Internals (Non-entry points)
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; Init Data Pointer routines
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DispatchVector InitDataBuffer
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DispatchVector InitDataTIB
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DispatchVector InitDataSG
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DispatchVector unusedVector
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; Data routines
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DispatchVector DoDataBuffer
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DispatchVector DoDataTIB
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DispatchVector DoDataSG
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DispatchVector unusedVector
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; Xfer routines
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DispatchVector DataIn_DMA
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DispatchVector DataIn_DMA
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DispatchVector DataOut_DMA ; <SM5> pdw
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DispatchVector DataOut_DMA ; <SM5> pdw
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DispatchVector unusedVector
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DispatchVector CyclePhase
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DispatchVector BusErrHandler96
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DispatchVector unusedVector
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DispatchVector unusedVector ; jvStartDMA - fill it in below
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DispatchVector unusedVector ; jvStopReadDMA - fill it in below
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DispatchVector unusedVector ; jvStopWriteDMA - fill it in below
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DispatchVector unusedVector ; jvWt4DMAComplete - fill it in below
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DispatchVector AutoMsgIn ;
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DispatchVector Wt4SelectComplete ;
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DispatchVector HandleBusInt ;
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DispatchVector unusedVector ; unused
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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DispatchVector unusedVector ;
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tblEntries equ (*-OffsetTbl96)/4
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;==========================================================================
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unusedVector
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DebugStr 'HAL unusedVector'
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rts
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;-------------------------------------------------------------
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;
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; Initialization code for the SCSI Manager 5394/5396
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Initc96Asm
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link a6, #0
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movem.l intrRegs, -(sp) ; save all registers, for convenience
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movea.l 8(a6), A5 ; get ptr to HAL globals
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move.l baseRegAddr(A5), A3 ; load A3 with base addr of 53c96
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;ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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; Set up jump table - go through DispatchVectors above and copy them into the HALglobals
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;
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IF (numSelectors<>tblEntries) THEN
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xxx TABLES DO NOT MATCH
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ENDIF
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moveq.l #numSelectors-1, d1 ; loop count
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IF forC96Init OR forROM THEN ; if not a linked patch, make addrs relative
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lea.l Initc96Asm, a1 ; get start of SCSI Mgr code
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move.l a1, d0 ; remember base address
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ELSE
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moveq.l #0, D0 ; if linked patch, make addrs absolute
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ENDIF
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lea OffsetTbl96, a1 ; address of offset table
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lea G_JmpTbl(A5), a0 ; point to base of jump table
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@MakeJmpTbl
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move.l (a1)+, d2 ; get the next offset
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beq.s @skipEntry ; if zero, skip this entry
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add.l d0, d2 ; compute the address
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move.l d2, (a0) ; install it in the jump table
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@skipEntry
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adda.l #4, a0
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dbra d1, @MakeJmpTbl ; loop for all vectors
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;ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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; Replace standard vectors (just loaded) with those for specific hardware
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;
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IF forPDMProto THEN
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bset #doRealDMARead, dmaFlags(A5)
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bset #doRealDMAWrite, dmaFlags(A5)
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ENDIF
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tst.b HBAhasDMA(A5) ; does HBA have real DMA?
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beq.w @hasNoDMA ; no-> install psuedo-DMA routines
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@hasDMA
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move.b dmaAlignmentSize(A5), D0 ; 8 or 16 (or whatever)
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ext.w D0
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ext.l D0
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subq.l #1, D0
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move.l D0, dmaAlignMask(A5)
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cmp.b #dmaTypePSC, dmaType(A5) ; is it a PSC-type DMA?
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beq.s @hasPSC ; -> yes
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cmp.b #dmaTypeAMIC, dmaType(A5) ; is it an AMIC-type DMA?
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beq.s @hasAMIC ; -> yes
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cmp.b #dmaTypeGC, dmaType(A5) ; is it a Grand Central-type DMA?
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beq.w @hasGC
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DebugStr 'Bad hwDesc - dmaType unknown'
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;
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; CYCLONE ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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@hasPSC
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lea StartPSC, A0
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move.l A0, jvStartDMA(A5)
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lea StopPSCRead, A0
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move.l A0, jvStopReadDMA(A5)
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lea StopPSCWrite, A0
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move.l A0, jvStopWriteDMA(A5)
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lea Wt4PSCComplete, A0
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move.l A0, jvWt4DMAComplete(A5)
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lea SetupIOPSC, A0
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move.l A0, jvSetupIO(A5)
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lea TeardownIOPSC, A0
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move.l A0, jvTeardownIO(A5)
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bra.w @endDMAstuff
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;
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; PDM ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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@hasAMIC ; first do DMA sub-transfer routines
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lea StartAMIC, A0
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move.l A0, jvStartDMA(A5)
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lea StopAMICRead, A0
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move.l A0, jvStopReadDMA(A5)
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lea StopAMICWrite, A0
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move.l A0, jvStopWriteDMA(A5)
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lea Wt4AMICComplete, A0
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move.l A0, jvWt4DMAComplete(A5)
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lea SetupIOAMIC, A0
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move.l A0, jvSetupIO(A5)
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lea TeardownIOAMIC, A0
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move.l A0, jvTeardownIO(A5)
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lea SlowRead96, A0 ; LET'S FIGURE OUT WHAT'S WRONG WITH LITTLE DMAs!!!
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move.l A0, jvReadSlow(A5)
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IF forPDMProto THEN
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IMPORT DoWeHaveAMIC3B
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bsr DoWeHaveAMIC3B ; If we donÕt have AMIC3B then
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beq.s @hasNoDMA ; use pseudo-DMA routines.
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ENDIF
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bra.w @endDMAstuff
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;
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; TNT ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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@hasGC
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lea StartGC, A0
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move.l A0, jvStartDMA(A5)
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lea StopGCRead, A0
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move.l A0, jvStopReadDMA(A5)
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lea StopGCWrite, A0
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move.l A0, jvStopWriteDMA(A5)
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lea Wt4GCComplete, A0
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move.l A0, jvWt4DMAComplete(A5)
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lea SetupIOGC, A0
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move.l A0, jvSetupIO(A5)
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lea TeardownIOGC, A0
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move.l A0, jvTeardownIO(A5)
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bra.s @endDMAstuff
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;
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; QUADRAs and CENTRISes ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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@hasNoDMA
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lea FastRead96, A0 ; assume FastRead96
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move.l A0, jvReadFast(A5) ; put this into transfer routine vector
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lea FastWrite96, A0 ; assume FastWrite96
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move.l A0, jvWriteFast(A5) ; put this into transfer routine vector
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lea SlowRead96, A0 ; always SlowRead96
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move.l A0, jvReadSlow(A5)
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lea SlowWrite96, A0 ; always SlowWrite96
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move.l A0, jvWriteSlow(A5)
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cmp.b #pdmaTypeBIOS, dmaType(a5) ; Is this a BIOS equipped Machine?
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bne.s @endDMAstuff ; if not -> assumptions correct
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IF forSTP601v1 THEN
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lea SlowRead96, A0 ; ¥¥¥¥ if so, replace routines with BIOS versions
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ELSE
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lea FastRead_96_BIOS, A0 ; if so, replace routines with BIOS versions
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ENDIF
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move.l A0, jvReadFast(A5)
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lea FastWrite_96_BIOS, A0
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move.l A0, jvWriteFast(A5)
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@endDMAstuff
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;ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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; Configure rCF3NormalVal and rCF3DMAVal according to our hardware
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;
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move.b #mCF3_SaveResidual, rCF3NormalVal(A5) ; assume NOT T8
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move.b #mCF3_SaveResidual, rCF3DMAVal(A5) ; assume NOT T8
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tst.b usesThreshold8(A5) ; is T8 used for DMA?
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beq.s @endThresholdStuff ; no -> skip this all
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move.b #mCF3_SaveResidual + mCF3_Threshold8 + mCF3_AltDMAMode, rCF3DMAVal(A5)
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; do not assert DREQ on residual byte at end of xfer
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; enable alternate DMA mode
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; enable threshold 8 mode
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tst.b HBAhasPseudoDMA(A5) ; does HBA have pseudo DMA?
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bne.s @endThresholdStuff ; -> if so, switch back and forth
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move.b rCF3DMAVal(A5), rCF3NormalVal(A5) ; if not, always use T8
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@endThresholdStuff
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move.b rCF3NormalVal(A5), rCF3(A3) ; configure for normal operation
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;ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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;
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; Assorted stuff
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;
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bsr Install_ISR
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WITH DeferredTask
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WITH SCSIGlobalsRec
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; Setup the real deferred task
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lea dataDT(a5),a0 ; our deferred task record
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lea DataDTask,a1 ; the deferred task
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clr.l qLink(a0) ; reserved on entry
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move.w #dtQType, qType(a0) ; The queue type
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move.l a1, dtAddr(a0) ; fill in PB
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move.l a5, dtParm(a0) ; Save globals do DT can restore a5
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clr.l dtReserved(a0) ; reserved
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clr.w dtFlags(a0) ; reserved
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; Setup the dummy deferred task
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lea dataDT_Null(a5),a0 ; our deferred task record
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lea @bogusDefer,a1 ; the deferred task (!)
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clr.l qLink(a0) ; reserved on entry
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move.w #dtQType, qType(a0) ; The queue type
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move.l a1, dtAddr(a0) ; fill in PB
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move.l a5, dtParm(a0) ; parameter is our globals
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clr.l dtReserved(a0) ; reserved
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clr.w dtFlags(a0) ; reserved
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move.l SCSIGlobals, A0 ;
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move.l ci_jDisptch_Vers, D0 ; our version number
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cmp.l ci_jDisptchVers(A0), D0 ; already installed?
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beq.b @alreadyInstalled ; yep
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move.l D0, ci_jDisptchVers(A0) ; remember our version number
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move.l jDisptch, oldjDisptch(A0) ; remember the old routine
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clr.w privDTQFlags(A0) ; clear out the qFlags field
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clr.l privDTQHead(A0) ; and the qHead
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clr.l privDTQTail(A0) ; and the qTail
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lea ci_jDisptch, A1 ; get our patch
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move.l A1, jDisptch ; and install it in the jVector
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@alreadyInstalled
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clr.b dataDTFlags(a5) ; clear our flags field
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move.b #SCSIPhase.kBusFreePhase, currentPhase(A5)
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IF RECORD_ON THEN
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pea $00000000
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pea '===='
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bsr RecordEvent
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addq.l #8, sp
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ENDIF
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movem.l (sp)+, intrRegs ; restore registers
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unlk A6
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rts
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@bogusDefer
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rts
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NAME 'Initc96Asm'
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ENDWITH
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ENDWITH
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ENDWITH
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ENDP
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END
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