mirror of
https://github.com/elliotnunn/boot3.git
synced 2025-01-04 02:30:45 +00:00
5b0f0cc134
Resource forks are included only for .rsrc files. These are DeRezzed into their data fork. 'ckid' resources, from the Projector VCS, are not included. The Tools directory, containing mostly junk, is also excluded.
337 lines
12 KiB
Plaintext
337 lines
12 KiB
Plaintext
;
|
|
; File: MaceEqu.a
|
|
;
|
|
; Contains: Equates for accessing the Ethernet Media Access
|
|
; Controller (MACE)
|
|
;
|
|
; Written by: Mark A. Law
|
|
;
|
|
; Copyright: © 1991-1993 by Apple Computer, Inc. All rights reserved.
|
|
;
|
|
; This file is used in these builds: Mac32
|
|
;
|
|
; Change History (most recent first):
|
|
;
|
|
; <SM6> 6/14/93 kc Roll in Ludwig.
|
|
; <LW4> 5/1/93 mal #1082434 Added records for new GetMem & FreeMem rtns.
|
|
; <LW3> 3/21/93 mal Versioned record for MACE 'ecfg' rsrc.
|
|
; <LW2> 1/27/93 mal Added MACEecfg rsrc support.
|
|
; <SM5> 12/4/92 mal Removed OFLO bit from recv pkt status.
|
|
; <SM4> 11/19/92 mal Added equ for yet another bit AMD didn't tell us about.
|
|
; <SM3> 10/30/92 mal MaceInitParms record change.
|
|
; <SM2> 10/13/92 mal -changed status thats passed to RecvRtn to lw
|
|
; <1> 10/6/92 GDW New location for ROMLink tool.
|
|
; <SM2> 6/22/92 mal Changes to support PSC2's (EVT2) Ethernet DMA receive model.
|
|
; <P4> 4/30/92 mal Expanded MaceInitParms record.
|
|
; <P3> 4/27/92 mal Added MaceInit parameters record.
|
|
; <P2> 3/23/92 mal Added MACE MAC config reg bit defines
|
|
;
|
|
|
|
; ---------------------------------------------------------
|
|
; MACE Registers
|
|
; ---------------------------------------------------------
|
|
MACERegBase EQU $50F1C000 ; Mace Reg Base on Cyclone
|
|
|
|
MACERegs RECORD 0
|
|
MACE_RX_FIFO DS.W 1 ;RD RXData -Read Status first
|
|
ORG *+$e
|
|
MACE_XMIT_FIFO DS.W 1 ;TX TXData
|
|
ORG *+$e
|
|
MACE_TX_FRM_CNTRL DS.B 1 ;RD/WR 01=Retry,XMTFCS,AUTOPAD
|
|
ORG *+$f
|
|
MACE_TX_FRM_STAT DS.B 1 ;RD
|
|
ORG *+$f
|
|
MACE_TX_RETRY_CNT DS.B 1 ;RD
|
|
ORG *+$f
|
|
MACE_RX_FRM_CNTRL DS.B 1 ;RD/WR 00 = Not_AutoStripPad
|
|
ORG *+$f
|
|
MACE_RX_FRM_STAT DS.B 1 ;RD Read 4x to get RX Status of packet
|
|
ORG *+$f
|
|
MACE_FIFO_FRM_CNT DS.B 1 ;RD Number of frames in FIFO
|
|
ORG *+$f
|
|
MACE_INT DS.B 1 ;RD_1 Interupt Source bits
|
|
ORG *+$f
|
|
MACE_INT_MSK DS.B 1 ;RD/WR Interupt Enables
|
|
ORG *+$f
|
|
MACE_POLL DS.B 1 ;RD Yet another status location
|
|
ORG *+$f
|
|
MACE_BIU_CNFG DS.B 1 ;RD/WR 20 = normal mode 01 = Soft Reset
|
|
ORG *+$f
|
|
MACE_FIFO_CNFG DS.B 1
|
|
ORG *+$f
|
|
MACE_MAC_CNFG DS.B 1 ;Enables
|
|
ORG *+$f
|
|
MACE_PLS_CNFG DS.B 1 ;RD/WR 0=Normal Mode
|
|
ORG *+$f
|
|
MACE_PHY_CNFG DS.B 1 ;RD/WR Reserved,Dude.
|
|
ORG *+$f
|
|
MACE_CHIP_ID_LOW DS.B 1 ;RD Just Reads ID
|
|
ORG *+$f
|
|
MACE_CHIP_ID_HIGH DS.B 1 ;RD Just Reads ID
|
|
ORG *+$f
|
|
MACE_ADDR_CNFG DS.B 1 ;RD/WR 04=Phy_Addr, 02=Log_Addr
|
|
ORG *+$1f
|
|
MACE_LOG_ADDR DS.B 1 ;Load with 6 Zeros
|
|
ORG *+$f
|
|
MACE_PHY_ADDR DS.B 1 ;Load with Address
|
|
ORG *+$2f
|
|
MACE_MISSED_PKT_CNT DS.B 1 ;RD
|
|
ORG *+$4f
|
|
MACE_USER_TEST_REG DS.B 1 ;
|
|
ENDR
|
|
;
|
|
; MACE Interrupt Reg. & Int. Reg. Mask Bit defines
|
|
; MACE Int. Reg - Read/Clear; MACE Int. Mask Reg. - Read/Write
|
|
;
|
|
BABL EQU 6 ; Babble, Xmit timeout error
|
|
CERR EQU 5 ; Signal Quality Error (SQE), xmit
|
|
RCVCO EQU 4 ; Receive Collision Cnt Overflow
|
|
MPCO EQU 2 ; Missed Pkt Cnt Overflow
|
|
RCVINT EQU 1 ; Rcv int
|
|
XMTINT EQU 0 ; Xmit int
|
|
; mask to disable all MACE ints
|
|
MaceIntMask EQU (1<<BABL)+(1<<CERR)+(1<<RCVCO)+(1<<MPCO)+(1<<RCVINT)+(1<<XMTINT)
|
|
OurIntsMask EQU (1<<RCVINT) ; ignore recv ints
|
|
|
|
;
|
|
; MACE Transmit Frame Status Reg. Bit defines
|
|
; Note: ONE and MORE are swapped prior to CURIO B0 MACE
|
|
;
|
|
XMTSV EQU 7 ; transmit status field valid when 1
|
|
UFLO EQU 6 ; underflow - xmit fifo
|
|
LCOL EQU 5 ; late collision
|
|
MORE EQU 4 ; more than 1 retry needed to xmit
|
|
ONE EQU 3 ; exactly 1 retry needed to xmit
|
|
DEFER EQU 2 ; transmission defered at least once
|
|
LCAR EQU 1 ; loss of carrier
|
|
RTRY EQU 0 ; retry
|
|
|
|
;
|
|
; MACE Transmit Frame Control Reg. Bit defines (byte)
|
|
;
|
|
DRTRY EQU 7 ; disable retry
|
|
DXMTFCS EQU 3 ; disable xmit fcs
|
|
APADXMT EQU 0 ; enable xmt autopad
|
|
; -forces generation of fcs
|
|
|
|
;
|
|
; MACE Receive Frame Control Reg. Bit defines (byte)
|
|
;
|
|
ASTRIPRCV EQU 0 ; enable rcv autopad stripping
|
|
; -forces stripping of fcs
|
|
|
|
;
|
|
; MACE Receive Status Reg. Bit defines (long)
|
|
;
|
|
; Receive Message Byte Count (byte0)
|
|
; Bits 7-0 : Recv Message Byte Count bits 7-0
|
|
; Receive Status (byte1)
|
|
; Bits 3-0 : Recv Message Byte Count bits 11-8
|
|
; Bits 7-4 : Recv Message Status bits
|
|
RcvOFLO EQU 7 ; receive fifo overflow
|
|
RcvCLSN EQU 6 ; late collision during recv
|
|
RcvFRAM EQU 5 ; frame error, non-integer # of bytes
|
|
RcvFCS EQU 4 ; frame check sequence error
|
|
; Receive Runt Packet Count (byte2)
|
|
; -number of runts recv'd since last successfully recv'd pkt
|
|
; -maxs at 255
|
|
; Receive Collision Count (byte3)
|
|
; -number of collisions since last successfully recv'd pkt
|
|
; -maxs at 255
|
|
|
|
;
|
|
; MACE Bus Interface Unit Reg. Bit defines (byte)
|
|
;
|
|
BSWAP EQU 7 ; byte swap mode, 0-Intel, 1-Motorola
|
|
; Transmit start point Bits 5-4
|
|
XMSTP EQU 4 ; bit shift offset
|
|
MACERESET EQU 0 ; software reset
|
|
; Transmit start point equates
|
|
; -controls when preamble xmit starts
|
|
XMTS4 EQU $00 ; start when 4 bytes in FIFO
|
|
XMTS16 EQU $10 ; start when 16 bytes in FIFO
|
|
XMTS64 EQU $20 ; start when 64 bytes in FIFO
|
|
XMTS112 EQU $30 ; start when 112 bytes in FIFO
|
|
|
|
;
|
|
; MACE FIFO Configuration Reg. Bit defines (byte)
|
|
; -fifo water mark changes ignored until fw reset bit set
|
|
; Transmit FIFO water mark Bits 7-6
|
|
XMTFW EQU 6 ; bit shift offset
|
|
; Receive FIFO water mark Bits 5-4
|
|
RCVFW EQU 4 ; bit shift offset
|
|
XMTFWR EQU 3 ; xmit fifo water mark reset
|
|
RCVFWR EQU 2 ; recv fifo water mark reset
|
|
XMTBRST EQU 1 ; xmit burst
|
|
RCVBRST EQU 0 ; recv burst
|
|
; FIFO watermark equates
|
|
RFW16 EQU $00 ; 16 byte recv FIFO watermark
|
|
RFW32 EQU $10 ; 32 byte recv FIFO watermark
|
|
RFW64 EQU $20 ; 64 byte recv FIFO watermark
|
|
TFW16 EQU $00 ; 16 byte xmit FIFO watermark
|
|
TFW32 EQU $40 ; 32 byte xmit FIFO watermark
|
|
TFW64 EQU $80 ; 64 byte xmit FIFO watermark
|
|
|
|
|
|
;
|
|
; MACE MAC Configuration Reg. Bit defines (byte)
|
|
;
|
|
PROMISC EQU 7 ; promiscuous mode, recv all valid frames
|
|
DXMT2PD EQU 6 ; disable xmit 2-part deferral algorithm
|
|
EMBA EQU 5 ; enable modified back-off algorithm
|
|
ENXMT EQU 1 ; enable xmit
|
|
ENRCV EQU 0 ; enable recv
|
|
|
|
;
|
|
; MACE Physical Layer Signaling Reg. Bit defines (byte)
|
|
;
|
|
XMTSEL EQU 3 ; xmit mode select
|
|
; Port Select Bits 2-1
|
|
PORTSEL EQU 1 ; bit shift offset
|
|
ENSTS EQU 0 ; enable optional I/O function status
|
|
|
|
;
|
|
; MACE Internal Address Configuration Reg. Bit defines (byte)
|
|
;
|
|
ADDRCHG EQU 7 ; address change enable
|
|
PHYADDR EQU 2 ; physical address select
|
|
LOGADDR EQU 1 ; logical address select
|
|
|
|
;
|
|
; MACE User Test Reg. Bit defines (byte)
|
|
;
|
|
;¥¥¥¥¥ WARNING: DO NOT EVER SET BIT 7 or you'll fry the MACE!!!! ¥¥¥¥¥
|
|
; Bit 6 (disable) is set during MACE init to disallow an erroneous and/or
|
|
; malicious setting of RTRE.
|
|
RTRE EQU 7 ; reserved test register enable
|
|
RTRD EQU 6 ; reserved test register disable
|
|
;¥¥¥¥¥
|
|
RPA EQU 5 ; runt packet accept
|
|
FCOLL EQU 4 ; force a collision, use with loopback
|
|
RCVFCSE EQU 3 ; receive fcs enable, use with loopback
|
|
; Loopback control Bits 2-1, %XX0 ¥¥¥ NOT FOR BIT SHIFTS!
|
|
NOLPB EQU %000 ; disable loopback mode
|
|
EXTLPB EQU %010 ; external loopback mode
|
|
INTLPB EQU %100 ; internal loopback, no MENDEC
|
|
MENDECLPB EQU %110 ; internal loopback, with MENDEC
|
|
|
|
|
|
;
|
|
; Misc. equates
|
|
;
|
|
MondoPkt EQU 2000 ; Value > max pkt, used for Recv DMA cnt
|
|
|
|
CntRegMask EQU $0001ffff ; Ignore upper 15 bits
|
|
|
|
nobuff EQU -2 ; no xmit buffer available
|
|
|
|
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Network Statistics
|
|
NetStats RECORD 0 ; network management stats.
|
|
TxOK DS.L 1 ; frames transmitted OK
|
|
sCollFrame DS.L 1 ; single collision frames
|
|
mCollFrame DS.L 1 ; multiple collision frames
|
|
CollFrame DS.L 1 ; collision frames
|
|
DefTx DS.L 1 ; deferred transmissions
|
|
LateColl DS.L 1 ; late collisions
|
|
ExcessColl DS.L 1 ; excessive collisions
|
|
ExcessDef DS.L 1 ; excessive defferals
|
|
InMACTxErr DS.L 1 ; internal MAC transmit errors
|
|
RxOK DS.L 1 ; frames received OK
|
|
MultiRxOK DS.L 1 ; multicast frames recd OK
|
|
BroadRxOK DS.L 1 ; broadcast frames recd OK
|
|
FCSerr DS.L 1 ; frame check sequence errors
|
|
FAerr DS.L 1 ; frame alignment errors
|
|
MPerr DS.L 1 ; missed packet errors
|
|
Size EQU *
|
|
ENDR
|
|
|
|
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ General Equates
|
|
TalliesPerSec EQU 5000000 ; number of timer ticks/second
|
|
TxMaxRetries EQU 4 ; max attempts to retry aborted xmits
|
|
Max_Tx_Packets EQU 16 ; maximum # of chained Tx packets
|
|
Min_Pkt_Size EQU 60 ; minimum packet size
|
|
Min_Rx_Buffs EQU 2 ; minimum # of recv descriptors/buffers
|
|
Max_Pkt_Size EQU 1518 ; maximum packet size (inc. CRC)
|
|
EOL_Bit EQU 0 ; end-of-link bit
|
|
|
|
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ For GetMemory call
|
|
GetMem RECORD 0
|
|
memsize DS.l 1 ; requested size
|
|
memoptions DS.l 1 ; requested options
|
|
memhndl DS.l 1 ; handle to memory mgr block
|
|
memhndla DS.l 1 ; handle to 4 or 8k aligned memory
|
|
memhndlasz DS.l 1 ; ptr to 4 or 8k aligned memory size
|
|
GetMemSz EQU *
|
|
ENDR
|
|
|
|
Locked EQU 0 ; want locked memory
|
|
Contig EQU 1 ; want contiguous memory
|
|
CacheOff EQU 2 ; want non-cacheable memory
|
|
|
|
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ For FreeMemory call
|
|
FreeMem RECORD 0
|
|
memoptions DS.l 1 ; requested options
|
|
memptr DS.l 1 ; ptr to memory mgr block
|
|
memptra DS.l 1 ; ptr to 4 or 8k aligned memory
|
|
memptrasz DS.l 1 ; 4 or 8k aligned memory size
|
|
FreeMemSz EQU *
|
|
ENDR
|
|
|
|
;¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Initialization Parameters
|
|
MACEInitParms RECORD 0
|
|
RecvRtn DS.l 1 ; address of Ethernet receive routine
|
|
RecvPrms DS.l 1 ; parms to pass @ receive
|
|
XmitRtn DS.l 1 ; address of Ethernet xmit complete routine
|
|
XmitPrms DS.l 1 ; parms to pass @ xmit complete
|
|
MACECfgPtr DS.l 1 ; ptr to MACE config record
|
|
Dot3NetStats DS.l 1 ; ptr to 802.3 statistics array
|
|
LAPMIBNetStats DS.l 1 ; ptr to LAP MIB statistics array
|
|
EnetAddr DS.l 1 ; ptr to ethernet address
|
|
FastMoveRtn DS.l 1 ; ->proc to move memory FAST
|
|
IPSize EQU *
|
|
ENDR
|
|
|
|
;¥¥¥¥ Parms passed to .ENET "RecvRtn"
|
|
RcvParms RECORD {A6Link}
|
|
Size EQU * ; no local vars
|
|
A6Link DS.l 2 ; saved A6 and return addr
|
|
Parm DS.l 1 ; parm passed to MaceInit
|
|
Buff DS.l 1 ; ptr to Mace's buffer containing pkt
|
|
Pkt DS.l 1 ; ptr to packet data
|
|
Len DS.w 1 ; pkt length
|
|
Stat DS.l 1 ; pkt status
|
|
; Stat definition:
|
|
; Byte 0: Receive Runt Packet Count (Bits 31-24)
|
|
; -number of runts recv'd since last successfully recv'd pkt
|
|
; -maxs at 255
|
|
; Byte 1: Receive Collision Count (Bits 23-16)
|
|
; -number of collisions since last successfully recv'd pkt
|
|
; -maxs at 255
|
|
; Byte 2-3: Receive Status (Bits 15-0)
|
|
; Bits 15-7,3-0 : reserved, read as 0's
|
|
; Bits 6-4 : Recv Message Status bits
|
|
; RcvCLSN EQU 6 ; late collision during recv
|
|
; RcvFRAM EQU 5 ; frame error, non-integer # of bytes
|
|
; RcvFCS EQU 4 ; frame check sequence error
|
|
ParmsSz EQU * - Parm ; len of passed parms
|
|
ENDR
|
|
|
|
Configrsrc EQU 'ecfg' ; rsrc type for MACE config data rsrc
|
|
|
|
; Mace Configuration Record
|
|
MACECfg RECORD 0 ; Config values from config rsrc
|
|
MACECfgVers DS.w 1 ; record version
|
|
MACEBase DS.l 1 ; Base address of MACE
|
|
EnetPROM DS.l 1 ; base address of Address Prom
|
|
XmitFrmCtl DS.b 1 ; MACE transmit frame control register value
|
|
RecvFrmCtl DS.b 1 ; MACE receive frame control register value
|
|
FIFOCfgCtl DS.b 1 ; MACE xmit/recv fifo config control register value
|
|
MACCfgCtl DS.b 1 ; MACE MAC config control register value
|
|
; The following are optional values; ignored if zero
|
|
EnetAddr DS.b 6 ; Alternate Ethernet Address, overrides Address PROM
|
|
XmitBuffs DS.w 1 ; Alternate number of transmit buffers
|
|
RecvBuffs DS.w 1 ; Alternate number of receive buffers
|
|
RecvChains DS.w 1 ; Alternate number of receive "chains"
|
|
CfgSize EQU *
|
|
ENDR
|