2017-09-17 09:09:04 +00:00
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;
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; File: Clock.a
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;
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; Contains: This file contains routines to directly access the clock.
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;
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; Copyright: <09> 1985-1993 by Apple Computer, Inc., all rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM8> 12/13/93 PN Roll in KAOs and Horror changes to support Malcom and AJ
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; machines.
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; <SM7> 11/9/93 KW added eieioSTP macros. Only expanded for CygnusX1 ROM
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; <SM6> 5/28/92 kc Change the conventions of ValidatePRAM so that it can be called
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; by bsr instead of bsr6.
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; <SM5> 5/28/92 kc Added Register saves/.restores to ValidatePRAM.
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; <SM4> 5/28/92 kc Roll in Horror Changes. Comments follow:
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; <H2> 11/6/91 SWC Re-wrote clock and PRAM routines to be table-driven so that
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; future expansion should be really simple (and clean). Hardware
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; dependent routines will now be found in ClockPRAMPrimitives.a.
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; Moved PRamIO here from ClockPatches.a since that was all that
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; was left there.
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; <SM3> 5/17/92 kc Prepend via equates with "v".
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; <SM2> 5/5/92 SES Rolled in ReadDateTime patch functionality from PatchIIciROM.a.
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; This patch is only for machines with Egret. Egret's tick handler
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; was modified to update the Time lowmem global, so ReadTime
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; simply returns with noErr if on an Egret-based machine.
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; <15> 10/18/91 JSM Get rid of all the stupid conditionals.
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; <14> 8/29/91 JSM Cleanup header.
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; <13> 6/12/91 LN Changed #include 'HardwareEqu.a' to 'HardwarePrivateEqu.a'
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; <12> 9/14/90 MSH Removed the lame video-based PRAM scheme for Waimea and power
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; manager based clock. TIM has a conventional RTC.
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; <11> 7/3/90 CCH Fixed problem with PRAMIO writes.
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; <10> 5/14/90 MSH Test for clock in Power Manager used wrong bits.
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; <9> 4/12/90 MSH Fixed the Waimea PRAM interface to use the universal tables
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; correctly.
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; <8> 3/27/90 HJR Add Conditional so that HcMac will build.
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; <7> 3/22/90 MSH SysUtil and Clock rewritten to place all hardware dependent
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; routines in clock and to remove redundant parameter RAM reading
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; and writing routines. Also added Waimea versions of these
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; routines.
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; <6> 2/28/90 GMR Made changes for Egret code to match new Egret equates.
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; <5> 2/12/90 GMR Added ENDIF to fix build for MacPP,HcMac.
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; <4> 2/11/90 GMR Fixed WriteEgretPRAM, to delay 100us at end of packet, to give
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; Egret time to see completion (fixes a lock up problem).
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; <3> 2/10/90 GMR Made ValidatePRAM universal, to support Egret. Pram calls now
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; temporarily use Egret's Wr6805Addr command instead of WrPram
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; until 6805 code is fixed in next mask.
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; <2> 2/4/90 GMR Added partial Egret support, in ReadXPram, WriteXPram, and new
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; low level ReadPramByte (for use before Egret manager is
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; initialized, e.g. by MMU.a). Still need Egret version of
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; ValidatePRAM
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; <1.6> 6/16/89 SWC PRAM validation didn't: shifted one byte too many, but doesn't
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; anymore.
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; <1.5> 6/15/89 SWC Added ValidatePRAM to validate, and if necessary, initialize
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; PRAM at start time.
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; <1.4> 4/13/89 GGD Removed the support for the Rev7 MacII logic board, and all of
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; the ugly conditionals that were needed to support it. Removed
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; usage of nEqu.d and StartMacs. Removed conditionals which
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; supported two spellings of vRTCEnb (with and without the 'v'),
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; and made the spellings consistent in HardwareEqu.a, changed to
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; use bit definition equate instead of hard coded constants for
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; vRTCData. Converted to feature based conditionals. Added offset
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; vBufB to via accesses to clarify which register is being
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; accessed. Changed interface to ClkNoMem to have caller pass in
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; VIA base address in A1.
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; <1.3> 3/6/89 GGD Moved OneSecInt handler from IntHnd to Clock.a.
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; <1.2> 2/16/89 rwh Removed conditionals for non-working Vias.
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; <1.1> 11/10/88 CCH Fixed Header.
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; <1.0> 11/9/88 CCH Adding to EASE.
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; <<3C>1.3> 9/23/88 CCH Got rid of inc.sum.d and empty nFiles
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; <1.2> 9/16/88 rwh Roll-in onMvMac changes
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; <1.1> 6/10/88 MSH Changes made in Feb 88 did not get rolled into ease... Brian!
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; <1.0> 2/10/88 BBM Adding file for the first time into EASE<53>
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; <C968> 11/18/87 rwh Fix C880 - no RTS5 @ end of ClkNoMem for non-Laguna machines!
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; <C914> 10/29/87 rwh Port to Modern Victorian (onMvMac)
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; <C919> 10/27/87 MSH Bug fixes mostly, but did add a XPram mapping table for Laguna.
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; <C916> 10/21/87 MSH Forgot to load some pointers before call pmgr for Laguna.
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; <C880> 9/3/87 MSH Port to HcMac (Laguna) requires power manager interface. Does
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; not support parameter ram bytes $60-$DF. ReadFrClk, SendToClk
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; not supported. Removed ReadPram IMPORT, nobody uses it.
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; <C206> 10/9/86 bbm Modified to mpw aincludes.
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; <C112> 8/7/86 RDC Added changes for new NuMac hardware (clk now same as Mac)
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; <C56> 6/26/86 WRL Put ClkNoMem, ReadFrClk, and SendToClk back in this file (from
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; StartInit).
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; <C1> 4/15/86 RDC Enabled access to XPRamRead and XPRamWrite routines for Reno
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; (NuMac)
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; 2/19/86 BBM Made some modifications to work under MPW
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; 10/31/85 BBM arithmetic done wrong in Read/WriteXPRam.
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; 10/30/85 LAK No longer call ReadPram after extended read/write. Use jump
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; table vector rather than GetTrapAddress.
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; 10/29/85 BBM needed to save one more register across ClkNoMem call.
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; 10/25/85 RDC Removed MidMac equate for clock routines (now moved to
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; startmain)
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; 10/23/85 BBM Changed calling interface to ReadXPRam and WriteXPRam. Also now
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; checks if new clock chip present before executing ReadXPRam and
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; WriteXPRam.
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; 10/3/85 so these routines can be called from the start code (before memory
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; test). This is done via three macros: RTS5, BSR6 and RTS6. Also
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; supported is the extended command for reads and writes to the
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; new clock chip for mac. The entry for the lowest level routine
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; just added is ClkNoMem, and it is accessed via BSR5. Added two
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; new traps to access all of extra parameter ram, ReadXPRam and
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; WriteXPRam.
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; 10/2/85 BBM made the lowest level routines not use any memory (like the
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; stack),
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; 7/24/85 RDC new today - moved from Sysutil.text added changes for MidMac to
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; use new interface, int levels
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;___________________________________________________________________________________
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BLANKS ON
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STRING ASIS
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PRINT OFF ; <C56>
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LOAD 'StandardEqu.d'
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INCLUDE 'HardwarePrivateEqu.a'
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INCLUDE 'UniversalEqu.a' ; <1.5>
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INCLUDE 'IOPrimitiveEqu.a' ; <H2>
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PRINT ON ; <C56>
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Clock PROC EXPORT
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EXPORT OneSecInt ; <1.3>
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EXPORT ReadXPRam,WriteXPRam
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EXPORT ValidatePRAM,PramIO
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IMPORT PRAMInit ; <1.5>
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IMPORT PRAMInitTbl ; <1.5>
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PRINT NOGEN
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IF NOT BlackBirdDebug THEN
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;_______________________________________________________________________ <1.3>
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;
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2017-09-20 11:58:54 +00:00
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; Routine: OneSecInt 8180
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2017-09-17 09:09:04 +00:00
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;
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; Arguments: A1 (input) -- Address of VIA1
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;
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; Function: Services 1-second interrupt from clock . . .
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;
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; NOTE: This handler expects that the interrupt is still pending, and clears
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; it by clearing the CA2 interrupt flag on VIA 1 (base address passed
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; in register A1). This is correct for all current hardware implementations
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; but may not be in the future.
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; we support alarm clock flash here in the system code: other functions may
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; start the flash simply by clearing bit 1 of AlarmState
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;
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; AlarmState bit 7 = flash parity
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; bit 6 = 1 to enable initial beep
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; bit 5 = set to 0 every second by this code (flag to GNEFilter)
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; bit 1 = 0 to start flashing
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; bit 0 = 0 for global flash enable
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;
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;_______________________________________________________________________
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OneSecInt MOVE.B #1<<ifCA2,VIFR(A1) ; clear the interrupt <1.4>
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2017-09-20 11:58:54 +00:00
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NOP
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2017-09-17 09:09:04 +00:00
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BCLR #5,AlarmState ; flag GNEFilter to flash if enabled
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TST.B SPVolCtl ; bit 7 is alarm enable
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BPL.S @done ; exit if not enabled
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MOVE.L SPAlarm,D0
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BEQ.S @done ; exit if no alarm
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CMP.L Time,D0 ; is it past time?
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BHI.S @done ; exit if not
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; flash apple menu item if there's a window world
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BCLR #1,AlarmState ; flag GNEFilter to flash
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@done RTS ; <1.3>
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ENDIF
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;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <K2>
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; This is a hack for the one second interrupt. PG&E is suppose to be providing the interrupt
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; and it currently does not. After it is working again, this code should disappear.
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; REALLY!!! Disappear...
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;
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IF BlackBirdDebug THEN
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OneSecInt MOVEA.l A1, A0 ;
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MOVE.l #1000,D0 ; 1 second
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MOVEA.l jPrimeTime, A1 ; get pointer to the PrimeTime routine
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JSR (A1) ; restart time manager task
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ADDQ.L #1,Time ; count the second
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BCLR #5,AlarmState ; flag GNEFilter to flash if enabled
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; we support alarm clock flash here in the system code: other functions may
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; start the flash simply by clearing bit 1 of AlarmState
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;
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; AlarmState bit 7 = flash parity
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; bit 6 = 1 to enable initial beep
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; bit 5 = set to 0 every second by this code (flag to GNEFilter)
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; bit 1 = 0 to start flashing
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; bit 0 = 0 for global flash enable
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TST.B SPVolCtl ; bit 7 is alarm enable
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BPL.S @done ; exit if not enabled
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MOVE.L SPAlarm,D0
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BEQ.S @done ; exit if no alarm
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CMP.L Time,D0 ; is it past time?
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BHI.S @done ; exit if not
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; flash apple menu item if there's a window world
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BCLR #1,AlarmState ; flag GNEFilter to flash
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@done RTS ; <1.3>
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ENDIF
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;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <K2>
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;________________________________________________________________________________________
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;
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2017-09-20 11:58:54 +00:00
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; Routine: PramIO 81a8
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2017-09-17 09:09:04 +00:00
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;
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; Inputs: A0 - pointer to table of base addresses
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; A1 - pointer to ProductInfo record for this machine
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; A3 - pointer to PRAM I/O buffer
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; D1 - flags indicating which external features are valid
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; D3 - bit 31: 0=read, 1=write
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; bits 30..16: number of PRAM bytes to read/write (1-256)
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; bits 15.. 0: starting PRAM address (0-255)
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;
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; Outputs: none
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;
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; Trashes: A3,D3
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;
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; Function: reads/writes PRAM bytes from the caller's buffer before traps are set up
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;________________________________________________________________________________________
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PramIO MOVEM.L D0-D2/A0-A2,-(SP) ; <H2>
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MOVEA.L A1,A2 ; point to the ProductInfo <H2>
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ADDA.L ProductInfo.ClockPRAMPtr(A1),A2 ; and get the address of its clock/PRAM table <H2>
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MOVE.L 4*cpXPRAMIO(A2),D2 ; get the offset to the routine <H2>
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BEQ.S @NoEntry ; -> this function is not supported <H2>
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ADDA.L D2,A2 ; calculate the routine's address <H2>
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JSR (A2) ; and call it <H2>
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@NoEntry MOVEM.L (SP)+,D0-D2/A0-A2 ; <H2>
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RTS ; <H2>
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;________________________________________________________________________________________
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;
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2017-09-20 11:58:54 +00:00
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; Routine: ReadXPRAM 81c2, WriteXPRAM 81cc
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2017-09-17 09:09:04 +00:00
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;
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; Inputs: A0 - pointer to caller's buffer
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; D0 - [number of bytes to transfer][starting PRAM address]
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; D1 - bit 12: 1=read, 0=write
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;
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; Outputs: D0 - result code
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;
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; Trashes: none
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;
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; Function: reads or writes extended PRAM bytes into the caller's buffer
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;________________________________________________________________________________________
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ReadXPRAM MOVEM.L A0-A3/D1-D3,-(SP) ; <H2>
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MOVE.W #($17<<8)+%11100000,D1 ; control byte + mask for reg address[7..5] <H2>
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BRA.S rwXCommon ; <H2>
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WriteXPRAM MOVEM.L A0-A3/D1-D3,-(SP) ; <H2>
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MOVE.W #($07<<8)+%11100000,D1 ; control byte + mask for reg address[7..5] <H2>
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rwXCommon BTST.B #hwCbClock-8,HWCfgFlags ; do we have a new clock chip (256 PRAM bytes)? <H2>
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BEQ.S @rwXPRAMErr ; -> no <H2>
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MOVEA.L UnivInfoPtr,A1 ; point to this machine's product info <H2>
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ADDA.L ProductInfo.ClockPRAMPtr(A1),A1 ; and get the address of its clock/PRAM table <H2>
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MOVE.L 4*cpXParam(A1),D3 ; get the offset to the routine <H2>
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BEQ.S @NoEntry ; -> this function is not supported <H2>
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ADDA.L D3,A1 ; calculate the routine's address <H2>
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JSR (A1) ; and call it <H2>
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@NoEntry MOVEM.L (SP)+,A0-A3/D1-D3 ; <H2>
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RTS ; <H2>
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@rwXPRAMErr MOVEQ #PRWrErr,D0 ; no extended PRAM so just return an error <H2>
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BRA.S @NoEntry ; <H2>
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;________________________________________________________________________________________ <H2>
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;
|
2017-09-20 11:58:54 +00:00
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; Routine: ValidatePRAM 81f8
|
2017-09-17 09:09:04 +00:00
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;
|
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; Inputs: A6 - return address
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; A0 - pointer to table of base addresses
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; A1 - pointer to ProductInfo record for this machine
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; D0 - flags indicating which base addresses are valid
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; D1 - flags indicating which external features are valid
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; D2 - bits 31..16, hwCfgFlags info (possibly unknown)
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; bits 15.. 8, BoxFlag info (possibly unknown)
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; bits 7.. 0, Address Decoder Kind (zero if unknown)
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; D7 - bits 31..16: logic board type
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; bits 15.. 0: CPU type (0 = 68000, 1 = 68010, etc)
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;
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; Outputs: none
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;
|
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; Trashes: A2,A3
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;
|
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; Function: checks that parameter RAM is valid, and if it's not, initializes it to
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; its default state
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;________________________________________________________________________________________
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ValidatePRAM
|
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MOVEM.L D0-D3/A0-A3,-(SP) ; register saves from StartINIT <SM5> <8.6>
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LEA -256(SP),SP ; allocate a PRAM buffer on the stack <H2>
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MOVEA.L SP,A3 ; point to the buffer <H2>
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MOVE.L #(0<<31)|\ ; read <H2>
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(32<<16)|\ ; 32 bytes <H2>
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(0<<0),D3 ; from PRAM address 0 <H2>
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BSR PramIO ; <H2>
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CMPI.B #$A8,16(SP) ; is the "old" (20 byte) PRAM signature valid? <H2>
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BEQ.S @CheckXPRAM ; -> yes, move on <H2>
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BIGLEA PRAMInit,A3 ; point to table of default values <H2>
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MOVE.L #(1<<31)|\ ; write <H2>
|
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|
(16<<16)|\ ; 16 bytes <H2>
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|
(16<<0),D3 ; starting at PRAM address 16 <H2>
|
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|
BSR PramIO ; write out the first 16 bytes of original PRAM <H2>
|
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|
BIGLEA PRAMInit+16,A3 ; point to table of default values <H2>
|
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|
|
MOVE.L #(1<<31)|\ ; write <H2>
|
|
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|
(4<<16)|\ ; 4 bytes <H2>
|
|
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|
(8<<0),D3 ; starting at PRAM address 8 <H2>
|
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|
|
BSR PramIO ; write out the last 4 bytes of original PRAM <H2>
|
|
|
|
|
|
|
2017-09-20 11:58:54 +00:00
|
|
|
|
LEA @other,A3
|
|
|
|
|
|
MOVE.L #(1<<31)|\ ; write
|
|
|
|
|
|
(1<<16)|\ ; 1 byte
|
|
|
|
|
|
(16<<0),D3 ; starting at PRAM address 16
|
|
|
|
|
|
BSR PramIO
|
|
|
|
|
|
|
2017-09-17 09:09:04 +00:00
|
|
|
|
@CheckXPRAM LEA @XPRAMSig,A3 ; <H2>
|
|
|
|
|
|
MOVE.L 12(SP),D3 ; are the extended PRAM signature bytes valid? <H2>
|
|
|
|
|
|
CMP.L (A3),D3 ; <H2>
|
|
|
|
|
|
BEQ.S @Done ; -> yes, we're done <H2>
|
|
|
|
|
|
|
|
|
|
|
|
MOVEA.L SP,A3 ; point to our stack buffer <H2>
|
|
|
|
|
|
MOVEQ #(256-32)/4-1,D3 ; and zero each byte <H2>
|
|
|
|
|
|
@ClearBuf CLR.L (A3)+ ; <H2>
|
|
|
|
|
|
DBRA D3,@ClearBuf ; <H2>
|
|
|
|
|
|
|
|
|
|
|
|
BIGLEA PRAMInitTbl,A2 ; point to the table of default extended PRAM values <H2>
|
2017-09-20 11:58:54 +00:00
|
|
|
|
BIGLEA *+$373c,A3
|
|
|
|
|
|
SUB.L A2,A3
|
|
|
|
|
|
MOVE.L A3,D3
|
|
|
|
|
|
SUB.L #1,D3
|
2017-09-17 09:09:04 +00:00
|
|
|
|
LEA $76-32(SP),A3 ; and where they'll go in the buffer <H2>
|
|
|
|
|
|
@CopyXDefs MOVE.B (A2)+,(A3)+ ; <H2>
|
|
|
|
|
|
DBRA D3,@CopyXDefs ; <H2>
|
|
|
|
|
|
|
|
|
|
|
|
MOVEA.L SP,A3 ; point to the buffer <H2>
|
|
|
|
|
|
MOVE.L #(1<<31)|\ ; write <H2>
|
|
|
|
|
|
((256-32)<<16)|\ ; 256-32 bytes <H2>
|
|
|
|
|
|
(32<<0),D3 ; starting at PRAM address 32 <H2>
|
|
|
|
|
|
BSR PramIO ; <H2>
|
|
|
|
|
|
|
2017-09-20 11:58:54 +00:00
|
|
|
|
LEA @XPRAMSig,A3
|
|
|
|
|
|
MOVE.L #(1<<31)|\ ; write
|
|
|
|
|
|
(4<<16)|\ ; 4 bytes
|
|
|
|
|
|
(12<<0),D3 ; starting at PRAM address 12
|
|
|
|
|
|
BSR PramIO
|
|
|
|
|
|
|
2017-09-17 09:09:04 +00:00
|
|
|
|
@Done
|
|
|
|
|
|
LEA 256(SP),SP ; clean up the stack <H2>
|
|
|
|
|
|
MOVEM.L (SP)+,D0-D3/A0-A3 ; restore regs from StartINIT <SM5> <8.6>
|
|
|
|
|
|
RTS ; <H2>
|
|
|
|
|
|
|
2017-09-20 11:58:54 +00:00
|
|
|
|
@other DC.W $A800
|
|
|
|
|
|
|
2017-09-17 09:09:04 +00:00
|
|
|
|
@XPRAMSig DC.L 'NuMc' ; extended PRAM validity bytes (slot-based machines) <H2>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
END
|
