Partially reverse console logging
This commit is contained in:
DBJ314
Elliot Nunn
parent
f20a0216aa
commit
9fd3316452
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@ -501,99 +501,98 @@ serial_flush ; OUTSIDE REFERER
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ori r30, r31, MSR_DR
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mtmsr r30
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isync
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x09
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stb r29, 0x0002(r28)
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stb r29, 0x0002(r28);set register pointer to 9 (next write goes to WR9)
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eieio
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li r29, 0x80
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stb r29, 0x0002(r28)
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li r29, 0x80;load code for channel A (also disables interrupts)
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stb r29, 0x0002(r28);reset channel A
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x04
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stb r29, 0x0002(r28);set register pointer to 4 (next write goes to WR4)
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eieio
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li r29, 0x48;X16 clock, 8-bit sync, 1.5 stop bits, parity off
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x48
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x03
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stb r29, 0x0002(r28);set reg pointer to 3 (next write to WR3)
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eieio
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li r29, 0xc0;recieve 8 bits per character (but recieve off)
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stb r29, 0x0002(r28)
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eieio
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li r29, 0xc0
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x05
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stb r29, 0x0002(r28);set reg pointer to 5 (next write to WR5)
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eieio
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li r29, 0x60;transmit 8 bits per char (but transmit off)
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x60
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x09
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stb r29, 0x0002(r28)
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stb r29, 0x0002(r28);set reg pointer to 9 (next write to WR9)
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eieio
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li r29, 0x00
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stb r29, 0x0002(r28)
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stb r29, 0x0002(r28);stop channel A reset?
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x0a
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stb r29, 0x0002(r28);set reg pointer to 10 (next write to WR10)
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eieio
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li r29, 0x00;8-bit sync, NRZ encoding
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x00
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x0b
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stb r29, 0x0002(r28);set reg pointer to 11 (next write to WR11)
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eieio
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li r29, 0x50;rx and tx using BR Generator
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x50
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x0c
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stb r29, 0x0002(r28);set reg pointer to 12 (next write to WR12)
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eieio
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li r29, 0x00;0 time constant low byte
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x00
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x0d
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stb r29, 0x0002(r28);set reg pointer to 13 (next write to WR13)
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eieio
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li r29, 0x00;0 time constant high byte
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x00
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x0e
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stb r29, 0x0002(r28);set reg pointer to 14 (next write to WR14)
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eieio
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li r29, 0x01;enable Baud Rate generator
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stb r29, 0x0002(r28)
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eieio
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li r29, 0x01
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x03
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stb r29, 0x0002(r28);set reg pointer to 3 (next write to WR3)
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eieio
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li r29, 0xc1;enable reciever
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stb r29, 0x0002(r28)
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eieio
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li r29, 0xc1
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stb r29, 0x0002(r28)
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eieio
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lbz r29, 0x0002(r28)
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lbz r29, 0x0002(r28);make sure next write goes to command register
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li r29, 0x05
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stb r29, 0x0002(r28);set reg pointer to 5 (next write to WR5)
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eieio
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li r29, 0xea;assert DTR and RTS, set 8 bit characters, and enable transmitter
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stb r29, 0x0002(r28)
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eieio
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li r29, 0xea
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stb r29, 0x0002(r28)
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eieio
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mtmsr r31
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mtmsr r31 ;restore previous MSR
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isync
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blr
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; serial_io
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; See disclaimer above.
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;appears to set BAT 3 so the scc can be accessed from logical memory space.
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serial_io ; OUTSIDE REFERER
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mfspr r26, srr0
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