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Elliot Nunn 2018-07-28 14:20:23 +08:00
parent 7c05aaf190
commit b28fd136c0
21 changed files with 4354 additions and 3938 deletions
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20
NanoKernel/MRInterrupts.s
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@ -1,4 +1,16 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKExceptions
; Exception
; MRException
; NKMemory
; GetPhysical
; PutPTE
; NKSystemCrash
; SystemCrash
; EXPORTS:
; MRDataStorageInt (=> NKReset)
; MRMachineCheckInt (=> NKReset)
; Special MR registers to investigate: r19 (inst addr), r26 (error) ; Special MR registers to investigate: r19 (inst addr), r26 (error)
@ -12,8 +24,8 @@ MRDataStorageInt ; Consult DSISR and the page table to decide what to do
bne @possible_htab_miss bne @possible_htab_miss
andis. r28, r31, 0x0800 ; Illegal data access (else crash!) andis. r28, r31, 0x0800 ; Illegal data access (else crash!)
addi r29, r1, 0x320 ; ?bug -> PutPTE used to accept this arg addi r29, r1, KDP.CurDBAT0
bnel GetPhysical ; Read the failing PTE to r30/r31 ; TODO fix! bnel GetPhysical ; Get LBAT or lower PTE
li r28, 0x43 ; Filter Writethru and Protection bits li r28, 0x43 ; Filter Writethru and Protection bits
and r28, r31, r28 and r28, r31, r28
cmpwi cr7, r28, 0x43 cmpwi cr7, r28, 0x43
@ -62,7 +74,7 @@ MRMachineCheckInt ; Always gives HW fault
lwz r27, KDP.HtabLastEA(r1) lwz r27, KDP.HtabLastEA(r1)
subf r28, r19, r27 ; Delete last HTAB entry if suspicious subf r28, r19, r27 ; Delete last HTAB entry if suspicious
cmpwi r28, -16 cmpwi r28, -16 ; (i.e. within 16b of MemRetried EA)
blt @no_htab_del blt @no_htab_del
cmpwi r28, 16 cmpwi r28, 16
bgt @no_htab_del bgt @no_htab_del

57
NanoKernel/MRMemtab.s
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@ -1,4 +1,59 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MRMemtabCode
; MRLoad1
; MRLoad11
; MRLoad12
; MRLoad121
; MRLoad122
; MRLoad1221
; MRLoad124
; MRLoad1241
; MRLoad14
; MRLoad141
; MRLoad142
; MRLoad1421
; MRLoad21
; MRLoad221
; MRLoad24
; MRLoad241
; MRLoad242
; MRLoad4
; MRLoad41
; MRLoad42
; MRLoad421
; MRLoad44
; MRLoad8
; MRStore1
; MRStore11
; MRStore12
; MRStore121
; MRStore122
; MRStore1221
; MRStore124
; MRStore1241
; MRStore14
; MRStore141
; MRStore142
; MRStore1421
; MRStore2
; MRStore21
; MRStore221
; MRStore24
; MRStore241
; MRStore242
; MRStore4
; MRStore41
; MRStore42
; MRStore421
; MRStore44
; MRStore8
; MROptabCode
; MRLoad2
; MRLoad22
; MRStore22
; EXPORTS:
; MRMemtab (=> MROptabCode, NKExceptions)
; Indexing this table: ; Indexing this table:
; bits 0-23 MRCode ; bits 0-23 MRCode

56
NanoKernel/MRMemtabCode.s
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@ -1,4 +1,58 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MROptabCode
; MRDoSecondary
; MRLoad2
; MRLoad22
; MRStore22
; EXPORTS:
; MRLoad1 (=> MRMemtab)
; MRLoad11 (=> MRMemtab)
; MRLoad12 (=> MRMemtab)
; MRLoad121 (=> MRMemtab)
; MRLoad122 (=> MRMemtab)
; MRLoad1221 (=> MRMemtab)
; MRLoad124 (=> MRMemtab)
; MRLoad1241 (=> MRMemtab)
; MRLoad14 (=> MRMemtab)
; MRLoad141 (=> MRMemtab)
; MRLoad142 (=> MRMemtab)
; MRLoad1421 (=> MRMemtab)
; MRLoad21 (=> MRMemtab)
; MRLoad221 (=> MRMemtab)
; MRLoad24 (=> MRMemtab)
; MRLoad241 (=> MRMemtab)
; MRLoad242 (=> MRMemtab)
; MRLoad4 (=> MRMemtab)
; MRLoad41 (=> MRMemtab)
; MRLoad42 (=> MRMemtab)
; MRLoad421 (=> MRMemtab)
; MRLoad44 (=> MRMemtab)
; MRLoad8 (=> MRMemtab)
; MRStore1 (=> MRMemtab)
; MRStore11 (=> MRMemtab)
; MRStore12 (=> MRMemtab)
; MRStore121 (=> MRMemtab)
; MRStore122 (=> MRMemtab)
; MRStore1221 (=> MRMemtab)
; MRStore124 (=> MRMemtab)
; MRStore1241 (=> MRMemtab)
; MRStore14 (=> MRMemtab)
; MRStore141 (=> MRMemtab)
; MRStore142 (=> MRMemtab)
; MRStore1421 (=> MRMemtab)
; MRStore2 (=> MRMemtab)
; MRStore21 (=> MRMemtab)
; MRStore221 (=> MRMemtab)
; MRStore24 (=> MRMemtab)
; MRStore241 (=> MRMemtab)
; MRStore242 (=> MRMemtab)
; MRStore4 (=> MRMemtab)
; MRStore41 (=> MRMemtab)
; MRStore42 (=> MRMemtab)
; MRStore421 (=> MRMemtab)
; MRStore44 (=> MRMemtab)
; MRStore8 (=> MRMemtab)
; Each routine accepts: ; Each routine accepts:
; r17 = pretend inst with accessLen (range 1-8) in bits 27-30 (will be decremented) ; r17 = pretend inst with accessLen (range 1-8) in bits 27-30 (will be decremented)

76
NanoKernel/MROptab.s
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@ -1,4 +1,74 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MROptabCode
; MRPriCrash
; MRPriDCBZ
; MRPriLSCBX
; MRPriLSWI
; MRPriLSWX
; MRPriPlainLoad
; MRPriPlainStore
; MRPriSTFDUx
; MRPriSTFDx
; MRPriSTFSUx
; MRPriSTFSx
; MRPriSTHBRX
; MRPriSTSWI
; MRPriSTSWX
; MRPriSTWBRX
; MRPriUpdLoad
; MRPriUpdStore
; MRSecDCBZ
; MRSecDone
; MRSecException
; MRSecException2
; MRSecLFDu
; MRSecLFSu
; MRSecLHBRX
; MRSecLMW
; MRSecLSCBX
; MRSecLSWix
; MRSecLWARX
; MRSecLWBRX
; MRSecLoad
; MRSecLoadExt
; MRSecRedoNoTrace
; MRSecSTMW
; MRSecSTWCX
; MRSecStrStore
; MRRestab
; MRResBlank
; MRResDCBZ
; MRResLBZux
; MRResLDARX
; MRResLDux
; MRResLFDux
; MRResLFSux
; MRResLHAux
; MRResLHBRX
; MRResLHZux
; MRResLMW
; MRResLSCBX
; MRResLSWix
; MRResLWARX
; MRResLWAux
; MRResLWBRX
; MRResLWZux
; MRResRedoNoTrace
; MRResST1ux
; MRResST2ux
; MRResST4ux
; MRResST8ux
; MRResSTDCX
; MRResSTMW
; MRResSTSWix
; MRResSTWCX
; MRResX1012
; MRResX884
; MRRestab
; EXPORTS:
; MROptabD (=> NKHotInts)
; MROptabX (=> NKHotInts)
######################################################################## ########################################################################
@ -7,8 +77,8 @@
_L set 1 _L set 1
_S set 0 _S set 0
DC.W (&myAccLen << 11) | (&myLoadStore << 10) | (((&resLabel - MRResTab) >> 1) << 4) | &myFlags DC.W (&myAccLen << 11) | (&myLoadStore << 10) | (((&resLabel - MRResTab) >> 1) << 4) | &myFlags
DC.B (&primLabel - MRBase) >> 2 DC.B (&primLabel-MRBase) >> 2
DC.B (&secLabel - MRBase) >> 2 DC.B (&secLabel-MRBase) >> 2
ENDM ENDM
; LEGEND .... access size (r17 bits 27-30) and 0=Store/1=Load (r17 bit 31) ; LEGEND .... access size (r17 bits 27-30) and 0=Store/1=Load (r17 bit 31)

153
NanoKernel/MROptabCode.s
View File

@ -1,31 +1,82 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MRMemtab
; MRMemtab
; NKExceptions
; MRException
; NKFloatingPt
; LFDTable
; STFDTable
; NKSystemCrash
; SystemCrash
; EXPORTS:
; MRDoSecondary (=> MRMemtabCode, NKExceptions)
; MRDoneTableSTFD (=> NKFloatingPt)
; MRLoad2 (=> MRMemtab, MRMemtabCode)
; MRLoad22 (=> MRMemtab, MRMemtabCode)
; MRPriCrash (=> MROptab)
; MRPriDCBZ (=> MROptab)
; MRPriLSCBX (=> MROptab)
; MRPriLSWI (=> MROptab)
; MRPriLSWX (=> MROptab)
; MRPriPlainLoad (=> MROptab)
; MRPriPlainStore (=> MROptab)
; MRPriSTFDUx (=> MROptab)
; MRPriSTFDx (=> MROptab)
; MRPriSTFSUx (=> MROptab)
; MRPriSTFSx (=> MROptab)
; MRPriSTHBRX (=> MROptab)
; MRPriSTSWI (=> MROptab)
; MRPriSTSWX (=> MROptab)
; MRPriSTWBRX (=> MROptab)
; MRPriUpdLoad (=> MROptab)
; MRPriUpdStore (=> MROptab)
; MRSecDCBZ (=> MROptab, MRRestab)
; MRSecDone (=> MROptab, MRRestab, NKFloatingPt, NKSoftInts)
; MRSecException (=> MROptab, MRRestab)
; MRSecException2 (=> MROptab, MRRestab)
; MRSecLFDu (=> MROptab, MRRestab)
; MRSecLFSu (=> MROptab, MRRestab)
; MRSecLHBRX (=> MROptab, MRRestab)
; MRSecLMW (=> MROptab, MRRestab)
; MRSecLSCBX (=> MROptab, MRRestab)
; MRSecLSWix (=> MROptab, MRRestab)
; MRSecLWARX (=> MROptab, MRRestab)
; MRSecLWBRX (=> MROptab, MRRestab)
; MRSecLoad (=> MROptab, MRRestab)
; MRSecLoadExt (=> MROptab, MRRestab)
; MRSecRedoNoTrace (=> MROptab, MRRestab)
; MRSecSTMW (=> MROptab, MRRestab)
; MRSecSTWCX (=> MROptab, MRRestab)
; MRSecStrStore (=> MROptab, MRRestab)
; MRStore22 (=> MRMemtab, MRMemtabCode)
######################################################################## ########################################################################
MRPriCrash ; C00 MRPriCrash
bl SystemCrash bl SystemCrash
MRSecException ; C04 MRSecException
b MRSecException2 b MRSecException2
######################################################################## ########################################################################
MRPriSTFSx ; C08 MRPriSTFSx
rlwinm r17, r17, 0,16,10 rlwinm r17, r17, 0,16,10
MRPriSTFSUx ; C0C MRPriSTFSUx
crclr cr7_so crclr cr7_so
b MRDoTableSTFD b MRDoTableSTFD
MRPriSTFDx ; C14 MRPriSTFDx
rlwinm r17, r17, 0,16,10 rlwinm r17, r17, 0,16,10
MRPriSTFDUx ; C18 MRPriSTFDUx
crset cr7_so crset cr7_so
MRDoTableSTFD ; C1C MRDoTableSTFD
; This table is of the form: ; This table is of the form:
; stfd <reg>, KDP.FloatScratch(r1) ; stfd <reg>, KDP.FloatScratch(r1)
; b ; b MRDoneTableSTFD
clrrwi r19, r25, 10 clrrwi r19, r25, 10
rlwimi r19, r17, 14,24,28 rlwimi r19, r17, 14,24,28
@ -35,7 +86,7 @@ MRDoTableSTFD ; C1C
mtmsr r14 mtmsr r14
blr blr
MRDoneTableSTFD ; c38 MRDoneTableSTFD
ori r11, r11, 0x2000 ori r11, r11, 0x2000
lwz r20, KDP.FloatScratch(r1) lwz r20, KDP.FloatScratch(r1)
lwz r21, KDP.FloatScratch+4(r1) lwz r21, KDP.FloatScratch+4(r1)
@ -58,12 +109,12 @@ MRDoneTableSTFD ; c38
######################################################################## ########################################################################
MRPriSTWBRX ; C84 MRPriSTWBRX
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
lwbrx r21, r1, r28 lwbrx r21, r1, r28
b MRPriPlainLoad b MRPriPlainLoad
MRPriSTHBRX ; C90 MRPriSTHBRX
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
addi r21, r1, 2 addi r21, r1, 2
lhbrx r21, r21, r28 lhbrx r21, r21, r28
@ -71,25 +122,25 @@ MRPriSTHBRX ; C90
######################################################################## ########################################################################
MRPriUpdStore ; CA0 MRPriUpdStore
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
lwzx r21, r1, r28 lwzx r21, r1, r28
b MRPriUpdLoad b MRPriUpdLoad
MRPriPlainStore ; CAC MRPriPlainStore
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
lwzx r21, r1, r28 lwzx r21, r1, r28
MRPriPlainLoad ; CB4 MRPriPlainLoad
rlwinm r17, r17, 0,16,10 rlwinm r17, r17, 0,16,10
MRPriUpdLoad ; CB8 MRPriUpdLoad
extrwi. r22, r17, 4,27 extrwi. r22, r17, 4,27
add r19, r18, r22 add r19, r18, r22
######################################################################## ########################################################################
MRPriDone ; CC0 MRPriDone
clrrwi r25, r25, 10 clrrwi r25, r25, 10
insrwi r25, r19, 3,28 insrwi r25, r19, 3,28
insrwi r25, r17, 4,24 insrwi r25, r17, 4,24
@ -119,7 +170,7 @@ MRLoad2
lhz r23, -2(r19) lhz r23, -2(r19)
insrwi r21, r23, 16,16 insrwi r21, r23, 16,16
MRDoSecondary ; D18 MRDoSecondary
sync sync
rlwinm. r28, r17, 18,25,29 rlwinm. r28, r17, 18,25,29
mtlr r25 mtlr r25
@ -133,10 +184,10 @@ MRDoSecondary ; D18
######################################################################## ########################################################################
MRSecLoadExt ; D40 MRSecLoadExt
extsh r21, r21 extsh r21, r21
MRSecLoad ; D44 MRSecLoad
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
crset mrFlagDidLoad crset mrFlagDidLoad
stwx r21, r1, r28 stwx r21, r1, r28
@ -179,10 +230,10 @@ MRSecDone
######################################################################## ########################################################################
MRSecLHBRX ; DC0 MRSecLHBRX
slwi r21, r21, 16 slwi r21, r21, 16
MRSecLWBRX ; DC4 MRSecLWBRX
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
crset mrFlagDidLoad crset mrFlagDidLoad
stwbrx r21, r1, r28 stwbrx r21, r1, r28
@ -190,7 +241,7 @@ MRSecLWBRX ; DC4
######################################################################## ########################################################################
MRSecLFSu ; DD4 MRSecLFSu
clrrwi r20, r21, 31 clrrwi r20, r21, 31
xor. r21, r20, r21 xor. r21, r20, r21
beq MRSecLFDu beq MRSecLFDu
@ -213,7 +264,7 @@ MRSecLFSu ; DD4
slwi r21, r21, 21 slwi r21, r21, 21
insrwi r20, r23, 11,1 insrwi r20, r23, 11,1
MRSecLFDu ; E28 MRSecLFDu
; This table is of the form: ; This table is of the form:
; lfd <reg>, KDP.FloatScratch(r1) ; lfd <reg>, KDP.FloatScratch(r1)
; b MRSecDone ; b MRSecDone
@ -230,7 +281,7 @@ MRSecLFDu ; E28
######################################################################## ########################################################################
MRSecLMW ; E50 MRSecLMW
rlwinm. r28, r17, 13,25,29 rlwinm. r28, r17, 13,25,29
rlwinm r23, r17, 18,25,29 rlwinm r23, r17, 18,25,29
cmpw cr7, r28, r23 cmpw cr7, r28, r23
@ -238,10 +289,10 @@ MRSecLMW ; E50
beq loc_E68 beq loc_E68
beq cr7, loc_E6C beq cr7, loc_E6C
loc_E68 ; E68 loc_E68
stwx r21, r1, r28 stwx r21, r1, r28
loc_E6C ; E6C loc_E6C
cmpwi r28, 0x7C cmpwi r28, 0x7C
li r22, 9 li r22, 9
insrwi r17, r22, 6,26 insrwi r17, r22, 6,26
@ -249,7 +300,7 @@ loc_E6C ; E6C
bne MRPriDone bne MRPriDone
b MRSecDone b MRSecDone
MRSecSTMW ; E84 MRSecSTMW
addis r17, r17, 0x20 addis r17, r17, 0x20
rlwinm. r28, r17, 13,25,29 rlwinm. r28, r17, 13,25,29
beq MRSecDone beq MRSecDone
@ -265,12 +316,12 @@ MRPriDCBZ ; Zero four 8b chunks of the cache blk
clrrwi r19, r18, 5 ; r19 = address of chunk to zero clrrwi r19, r18, 5 ; r19 = address of chunk to zero
b MRComDCBZ ; (for use by this code only) b MRComDCBZ ; (for use by this code only)
MRSecDCBZ ; EAC MRSecDCBZ
andi. r22, r19, 0x18 andi. r22, r19, 0x18
clrrwi r19, r19, 3 ; MemAccess code decrements this reg clrrwi r19, r19, 3 ; MemAccess code decrements this reg
beq MRSecDone ; Zeroed all foun chunks -> done! beq MRSecDone ; Zeroed all foun chunks -> done!
MRComDCBZ ; EB8 MRComDCBZ
li r22, 0x10 ; Set 8 bytes (? set bit 27) li r22, 0x10 ; Set 8 bytes (? set bit 27)
insrwi. r17, r22, 6,26 insrwi. r17, r22, 6,26
addi r19, r19, 8 ; Align ptr to right hand size of chunk addi r19, r19, 8 ; Align ptr to right hand size of chunk
@ -280,14 +331,14 @@ MRComDCBZ ; EB8
######################################################################## ########################################################################
MRSecLWARX ; ED0 MRSecLWARX
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
crset mrFlagDidLoad crset mrFlagDidLoad
stwx r21, r1, r28 stwx r21, r1, r28
stwcx. r21, r1, r28 stwcx. r21, r1, r28
b MRSecDone b MRSecDone
MRSecSTWCX ; EE4 MRSecSTWCX
stwcx. r0, 0, r1 stwcx. r0, 0, r1
mfcr r23 mfcr r23
rlwinm r23, r23, 0,3,1 rlwinm r23, r23, 0,3,1
@ -304,31 +355,31 @@ MRSecRedoNoTrace ; Rerun the (cache) instruction, but not its Trace Exception
######################################################################## ########################################################################
MRSecException2 ; F08 MRSecException2
li r8, ecDataInvalidAddress li r8, ecDataInvalidAddress
b MRException b MRException
######################################################################## ########################################################################
MRPriSTSWI ; F10 MRPriSTSWI
addi r22, r27, -0x800 addi r22, r27, -0x800
extrwi r22, r22, 5,16 extrwi r22, r22, 5,16
b loc_F2C b loc_F2C
MRPriSTSWX ; F1C MRPriSTSWX
mfxer r22 mfxer r22
andi. r22, r22, 0x7F andi. r22, r22, 0x7F
addi r22, r22, -1 addi r22, r22, -1
beq MRSecDone beq MRSecDone
loc_F2C ; F2C loc_F2C
rlwimi r17, r22, 4,21,25 rlwimi r17, r22, 4,21,25
not r22, r22 not r22, r22
insrwi r17, r22, 2,4 insrwi r17, r22, 2,4
mr r19, r18 mr r19, r18
b loc_1008 b loc_1008
MRSecStrStore ; F40 MRSecStrStore
andi. r22, r17, 0x7C0 andi. r22, r17, 0x7C0
addis r28, r17, 0x20 addis r28, r17, 0x20
rlwimi r17, r28, 0,6,10 rlwimi r17, r28, 0,6,10
@ -338,21 +389,21 @@ MRSecStrStore ; F40
######################################################################## ########################################################################
MRPriLSWI ; F58 MRPriLSWI
addi r22, r27, -0x800 addi r22, r27, -0x800
extrwi r22, r22, 5,16 extrwi r22, r22, 5,16
addis r28, r27, 0x3E0 addis r28, r27, 0x3E0
rlwimi r17, r28, 22,16,20 rlwimi r17, r28, 22,16,20
b loc_F80 b loc_F80
MRPriLSWX ; F6C MRPriLSWX
mfxer r22 mfxer r22
andi. r22, r22, 0x7F andi. r22, r22, 0x7F
rlwimi r17, r27, 0,16,20 rlwimi r17, r27, 0,16,20
addi r22, r22, -1 addi r22, r22, -1
beq MRSecDone beq MRSecDone
loc_F80 ; F80 loc_F80
andis. r23, r17, 0x1F andis. r23, r17, 0x1F
rlwimi r17, r22, 4,21,25 rlwimi r17, r22, 4,21,25
not r22, r22 not r22, r22
@ -362,7 +413,7 @@ loc_F80 ; F80
rlwimi r17, r17, 5,11,15 rlwimi r17, r17, 5,11,15
b loc_1070 b loc_1070
MRSecLSWix ; FA0 MRSecLSWix
andi. r22, r17, 0x7C0 andi. r22, r17, 0x7C0
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
bne loc_1044 bne loc_1044
@ -372,7 +423,7 @@ MRSecLSWix ; FA0
######################################################################## ########################################################################
MRPriLSCBX ; FB8 MRPriLSCBX
mfxer r22 mfxer r22
andi. r22, r22, 0x7F andi. r22, r22, 0x7F
rlwimi r17, r27, 0,16,20 rlwimi r17, r27, 0,16,20
@ -388,7 +439,7 @@ MRPriLSCBX ; FB8
rlwimi r17, r17, 5,11,15 rlwimi r17, r17, 5,11,15
b loc_10C8 b loc_10C8
MRSecLSCBX ; FF0 MRSecLSCBX
rlwinm. r22, r17, 28,25,29 rlwinm. r22, r17, 28,25,29
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
bne loc_109C bne loc_109C
@ -398,7 +449,7 @@ MRSecLSCBX ; FF0
######################################################################## ########################################################################
loc_1008 ; 1008 loc_1008
andi. r23, r17, 0x7C0 andi. r23, r17, 0x7C0
rlwinm r28, r17, 13,25,29 rlwinm r28, r17, 13,25,29
lwzx r21, r1, r28 lwzx r21, r1, r28
@ -415,7 +466,7 @@ loc_1008 ; 1008
insrwi. r17, r22, 5,26 insrwi. r17, r22, 5,26
b MRPriDone b MRPriDone
loc_1044 ; 1044 loc_1044
rlwinm r23, r17, 18,25,29 rlwinm r23, r17, 18,25,29
cmpw cr7, r28, r23 cmpw cr7, r28, r23
rlwinm r23, r17, 23,25,29 rlwinm r23, r17, 23,25,29
@ -424,13 +475,13 @@ loc_1044 ; 1044
beq cr6, loc_1060 beq cr6, loc_1060
stwx r21, r1, r28 stwx r21, r1, r28
loc_1060 ; 1060 loc_1060
addis r28, r17, 0x20 addis r28, r17, 0x20
rlwimi r17, r28, 0,6,10 rlwimi r17, r28, 0,6,10
addi r17, r17, -0x40 addi r17, r17, -0x40
beq MRSecDone beq MRSecDone
loc_1070 ; 1070 loc_1070
andi. r23, r17, 0x7C0 andi. r23, r17, 0x7C0
li r22, 9 li r22, 9
insrwi r17, r22, 6,26 insrwi r17, r22, 6,26
@ -443,7 +494,7 @@ loc_1070 ; 1070
insrwi. r17, r22, 5,26 insrwi. r17, r22, 5,26
b MRPriDone b MRPriDone
loc_109C ; 109C loc_109C
rlwinm r23, r17, 18,25,29 rlwinm r23, r17, 18,25,29
cmpw cr7, r28, r23 cmpw cr7, r28, r23
rlwinm r23, r17, 23,25,29 rlwinm r23, r17, 23,25,29
@ -452,13 +503,13 @@ loc_109C ; 109C
beq cr6, loc_10B8 beq cr6, loc_10B8
stwx r21, r1, r28 stwx r21, r1, r28
loc_10B8 ; 10B8 loc_10B8
addis r28, r17, 0x20 addis r28, r17, 0x20
rlwimi r17, r28, 0,6,10 rlwimi r17, r28, 0,6,10
addi r17, r17, -0x40 addi r17, r17, -0x40
beq MRSecDone beq MRSecDone
loc_10C8 ; 10C8 loc_10C8
not r22, r22 not r22, r22
rlwimi r22, r17, 6,30,31 rlwimi r22, r17, 6,30,31
li r28, 1 li r28, 1
@ -485,7 +536,7 @@ loc_10C8 ; 10C8
beq cr7, loc_112C beq cr7, loc_112C
bne loc_1070 bne loc_1070
loc_112C ; 112C loc_112C
rlwinm. r28, r17, 0,3,3 rlwinm. r28, r17, 0,3,3
mfxer r23 mfxer r23
add r22, r22, r23 add r22, r22, r23

62
NanoKernel/MRRestab.s
View File

@ -1,12 +1,62 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MROptabCode
; MRSecDCBZ
; MRSecDone
; MRSecException
; MRSecException2
; MRSecLFDu
; MRSecLFSu
; MRSecLHBRX
; MRSecLMW
; MRSecLSCBX
; MRSecLSWix
; MRSecLWARX
; MRSecLWBRX
; MRSecLoad
; MRSecLoadExt
; MRSecRedoNoTrace
; MRSecSTMW
; MRSecSTWCX
; MRSecStrStore
; EXPORTS:
; MRResBlank (=> MROptab)
; MRResDCBZ (=> MROptab)
; MRResLBZux (=> MROptab)
; MRResLDARX (=> MROptab)
; MRResLDux (=> MROptab)
; MRResLFDux (=> MROptab)
; MRResLFSux (=> MROptab)
; MRResLHAux (=> MROptab)
; MRResLHBRX (=> MROptab)
; MRResLHZux (=> MROptab)
; MRResLMW (=> MROptab)
; MRResLSCBX (=> MROptab)
; MRResLSWix (=> MROptab)
; MRResLWARX (=> MROptab)
; MRResLWAux (=> MROptab)
; MRResLWBRX (=> MROptab)
; MRResLWZux (=> MROptab)
; MRResRedoNoTrace (=> MROptab)
; MRResST1ux (=> MROptab)
; MRResST2ux (=> MROptab)
; MRResST4ux (=> MROptab)
; MRResST8ux (=> MROptab)
; MRResSTDCX (=> MROptab)
; MRResSTMW (=> MROptab)
; MRResSTSWix (=> MROptab)
; MRResSTWCX (=> MROptab)
; MRResX1012 (=> MROptab)
; MRResX884 (=> MROptab)
; MRRestab (=> MROptab, NKExceptions)
######################################################################## ########################################################################
MACRO MACRO
restabLine &myFlags, &secLabel restabLine &myFlags, &secLabel
DC.B &myFlags DC.B &myFlags
DC.B (&secLabel - MRBase) >> 2 DC.B (&secLabel-MRBase) >> 2
ENDM ENDM
MRRestab MRRestab
MRResLBZux restabLine %0001, MRSecLoad ; 0 ; LBZ(U)(X) MRResLBZux restabLine %0001, MRSecLoad ; 0 ; LBZ(U)(X)

78
NanoKernel/NKColdInts.s
View File

@ -1,49 +1,59 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKExceptions
; Exception
; LoadInterruptRegisters
; ReturnFromInt
; NKMemory
; PutPTE
; EXPORTS:
; InstStorageInt (=> NKReset)
; MachineCheckInt (=> NKReset)
######################################################################## ########################################################################
InstStorageInt InstStorageInt
bl LoadInterruptRegisters bl LoadInterruptRegisters
andis. r8, r11, 0x4020 ; Not in HTAB || Bad seg reg andis. r8, r11, 0x4020 ; Not in HTAB || Bad seg reg
beq @already_in_htab beq @already_in_htab
stmw r14, KDP.r14(r1) stmw r14, KDP.r14(r1)
mr r27, r10 mr r27, r10
bl PutPTE bl PutPTE
bne @illegal_address ; Could not find in SegMap bne @illegal_address ; Could not find in SegMap
mfsprg r24, 3 mfsprg r24, 3
mfmsr r14 mfmsr r14
_set r15, r14, bitMsrDR _set r15, r14, bitMsrDR
addi r23, r1, KDP.VecTblMemRetry addi r23, r1, KDP.VecTblMemRetry
mtsprg 3, r23 mtsprg 3, r23
mr r19, r10 mr r19, r10
mtmsr r15 mtmsr r15
lbz r23, 0(r19) lbz r23, 0(r19)
sync sync
mtmsr r14 mtmsr r14
mtsprg 3, r24 mtsprg 3, r24
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
b ReturnFromInt b ReturnFromInt
@illegal_address @illegal_address
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
li r8, ecInstPageFault li r8, ecInstPageFault
blt Exception blt Exception
li r8, ecInstInvalidAddress li r8, ecInstInvalidAddress
b Exception b Exception
@already_in_htab @already_in_htab
andis. r8, r11, 0x800 ; Illegal access to legal EA? andis. r8, r11, 0x800 ; Illegal access to legal EA?
li r8, ecInstSupAccessViolation li r8, ecInstSupAccessViolation
bne Exception bne Exception
li r8, ecInstHardwareFault li r8, ecInstHardwareFault
b Exception b Exception
######################################################################## ########################################################################
MachineCheckInt MachineCheckInt
bl LoadInterruptRegisters bl LoadInterruptRegisters
li r8, ecMachineCheck li r8, ecMachineCheck
b Exception b Exception

152
NanoKernel/NKEquates.s
View File

@ -1,106 +1,106 @@
;_______________________________________________________________________ ;_______________________________________________________________________
; Equates for the whole NanoKernel ; Equates for the whole NanoKernel
;_______________________________________________________________________ ;_______________________________________________________________________
; Helps with making equates ; Helps with making equates
; X = 0x00008000, Xbit=16, Xshift=15 ; X = 0x00008000, Xbit=16, Xshift=15
macro macro
_bitEqu &bit, &name _bitEqu &bit, &name
&name equ 1 << (31-&bit) &name equ 1 << (31-&bit)
bit&name equ &bit bit&name equ &bit
shift&name equ 31 - &bit shift&name equ 31 - &bit
endm endm
kNanoKernelVersion equ $0101 kNanoKernelVersion equ $0101
; PowerPC Machine Status Register (MSR) bits ; PowerPC Machine Status Register (MSR) bits
; (borrowing the _bitEqu macro from NKInfoRecordsPriv.s) ; (borrowing the _bitEqu macro from NKInfoRecordsPriv.s)
_bitEqu 13, MsrPOW _bitEqu 13, MsrPOW
_bitEqu 15, MsrILE _bitEqu 15, MsrILE
_bitEqu 16, MsrEE _bitEqu 16, MsrEE
_bitEqu 17, MsrPR _bitEqu 17, MsrPR
_bitEqu 18, MsrFP _bitEqu 18, MsrFP
_bitEqu 19, MsrME _bitEqu 19, MsrME
_bitEqu 20, MsrFE0 _bitEqu 20, MsrFE0
_bitEqu 21, MsrSE _bitEqu 21, MsrSE
_bitEqu 22, MsrBE _bitEqu 22, MsrBE
_bitEqu 23, MsrFE1 _bitEqu 23, MsrFE1
_bitEqu 25, MsrIP _bitEqu 25, MsrIP
_bitEqu 26, MsrIR _bitEqu 26, MsrIR
_bitEqu 27, MsrDR _bitEqu 27, MsrDR
_bitEqu 30, MsrRI _bitEqu 30, MsrRI
_bitEqu 31, MsrLE _bitEqu 31, MsrLE
; Special Purpose Registers (SPRs) not understood by MPW ; Special Purpose Registers (SPRs) not understood by MPW
l2cr equ 1017 l2cr equ 1017
; Alignment for NanoKernel interrupt routines (mostly Interrupts.s) ; Alignment for NanoKernel interrupt routines (mostly Interrupts.s)
kIntAlign equ 5 kIntAlign equ 5
; Junk ; Junk
; IRP is 10 pages below KDP (measured start to start) ; IRP is 10 pages below KDP (measured start to start)
; This should be neatened up to describe the kernel global area ; This should be neatened up to describe the kernel global area
IRPOffset equ (-10) * 4096 IRPOffset equ (-10) * 4096
kKDPfromIRP equ 10 * 4096 kKDPfromIRP equ 10 * 4096
kPoolOffsetFromGlobals equ (-7) * 4096 ; goes all the way up to 24 bytes short of PSA kPoolOffsetFromGlobals equ (-7) * 4096 ; goes all the way up to 24 bytes short of PSA
; Branch instruction BO fields ; Branch instruction BO fields
; (disregarding static prediction :) ; (disregarding static prediction :)
BO_IF equ 12 BO_IF equ 12
BO_IF_NOT equ 4 BO_IF_NOT equ 4
Z equ 0x80000000 Z equ 0x80000000
; SIGP (SIGnal Plugin) selectors used by the kernel: ; SIGP (SIGnal Plugin) selectors used by the kernel:
kStartProcessor equ 1 ; r4 = target CPU idx, r5 = cpu's entry point, r6 = entry point's r3 (CPU struct ptr) kStartProcessor equ 1 ; r4 = target CPU idx, r5 = cpu's entry point, r6 = entry point's r3 (CPU struct ptr)
kStopProcessor equ 3 ; r4 = target CPU idx kStopProcessor equ 3 ; r4 = target CPU idx
kResetProcessor equ 4 ; r4 = target CPU idx kResetProcessor equ 4 ; r4 = target CPU idx
kAlert equ 5 ; r4 = target CPU idx? ; my name, has something to do with timers kAlert equ 5 ; r4 = target CPU idx? ; my name, has something to do with timers
kSIGP6 equ 6 ; r4 = target CPU idx? kSIGP6 equ 6 ; r4 = target CPU idx?
kSIGP7 equ 7 ; r4 = target CPU idx? kSIGP7 equ 7 ; r4 = target CPU idx?
kSynchClock equ 8 ; r4 = target CPU idx, kSynchClock equ 8 ; r4 = target CPU idx,
kSIGP9 equ 9 ; no args? kSIGP9 equ 9 ; no args?
kGetProcessorTemp equ 12 ; r4 = selector (ignored on Core99), r5 = cpu ID ; my name kGetProcessorTemp equ 12 ; r4 = selector (ignored on Core99), r5 = cpu ID ; my name
kSIGP17 equ 17 ; r4 = target CPU idx? kSIGP17 equ 17 ; r4 = target CPU idx?
; Exception cause equates ; Exception cause equates
; System = FFFFFFFF, Alt = 7DF2F700 (ecInstPageFault and ecDataPageFault disabled), same +/- VM ; System = FFFFFFFF, Alt = 7DF2F700 (ecInstPageFault and ecDataPageFault disabled), same +/- VM
ecNoException equ 0 ecNoException equ 0
ecSystemCall equ 1 ecSystemCall equ 1
ecTrapInstr equ 2 ecTrapInstr equ 2
ecFloatException equ 3 ecFloatException equ 3
ecInvalidInstr equ 4 ecInvalidInstr equ 4
ecPrivilegedInstr equ 5 ecPrivilegedInstr equ 5
ecMachineCheck equ 7 ecMachineCheck equ 7
ecInstTrace equ 8 ecInstTrace equ 8
ecInstInvalidAddress equ 10 ecInstInvalidAddress equ 10
ecInstHardwareFault equ 11 ecInstHardwareFault equ 11
ecInstPageFault equ 12 ecInstPageFault equ 12
ecInstSupAccessViolation equ 14 ecInstSupAccessViolation equ 14
ecDataInvalidAddress equ 18 ecDataInvalidAddress equ 18
ecDataHardwareFault equ 19 ecDataHardwareFault equ 19
ecDataPageFault equ 20 ecDataPageFault equ 20
ecDataWriteViolation equ 21 ecDataWriteViolation equ 21
ecDataSupAccessViolation equ 22 ecDataSupAccessViolation equ 22
ecDataSupWriteViolation equ 23 ecDataSupWriteViolation equ 23
ecUnknown24 equ 24 ecUnknown24 equ 24
; FLAGS r7/cr ; FLAGS r7/cr
@ -117,19 +117,19 @@ maskFlags equ 0x00FFFFFF
; Bits 8-15 (CR2-CR3) Global Flags ; Bits 8-15 (CR2-CR3) Global Flags
crMaskGlobalFlags equ %00110000 crMaskGlobalFlags equ %00110000
maskGlobalFlags equ 0x00FF0000 maskGlobalFlags equ 0x00FF0000
_bitEqu 8, GlobalFlagSystem ; raised when System (Emulator) Context is running _bitEqu 8, GlobalFlagSystem ; raised when System (Emulator) Context is running
_bitEqu 13, GlobalFlagMQReg ; raised when POWER "Multiply-Quotient" register is present _bitEqu 13, GlobalFlagMQReg ; raised when POWER "Multiply-Quotient" register is present
; Bits 24-31 (CR6-CR7) Context Flags ; Bits 24-31 (CR6-CR7) Context Flags
crMaskContextFlags equ %00001111 crMaskContextFlags equ %00001111
maskContextFlags equ 0x0000FFFF maskContextFlags equ 0x0000FFFF
; Bits 20-23 (CR5) MSR Flags FE0/SE/BE/FE1: ; Bits 20-23 (CR5) MSR Flags FE0/SE/BE/FE1:
crMaskMsrFlags equ %00000100 crMaskMsrFlags equ %00000100
maskMsrFlags equ 0x00000F00 maskMsrFlags equ 0x00000F00
; Bits 24-31 (CR6-CR7) Other Context Flags: ; Bits 24-31 (CR6-CR7) Other Context Flags:
_bitEqu 26, ContextFlagTraceWhenDone ; raised when MSR[SE] is up but we get an unrelated interrupt _bitEqu 26, ContextFlagTraceWhenDone ; raised when MSR[SE] is up but we get an unrelated interrupt
_bitEqu 27, ContextFlagMemRetryErr ; raised when an exception is raised during MemRetry _bitEqu 27, ContextFlagMemRetryErr ; raised when an exception is raised during MemRetry
_bitEqu 31, ContextFlagResumeMemRetry ; allows MemRetry to be resumed (raised by userspace?) _bitEqu 31, ContextFlagResumeMemRetry ; allows MemRetry to be resumed (raised by userspace?)
mrOpflag1 equ cr3_lt mrOpflag1 equ cr3_lt

743
NanoKernel/NKExceptions.s
View File

@ -1,471 +1,492 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MRMemtab
; MRMemtab
; MROptabCode
; MRDoSecondary
; MRRestab
; MRRestab
; NKFloatingPt
; DisableFPU
; EnableFPU
; ReloadFPU
; NKSystemCrash
; SystemCrash
; EXPORTS:
; Exception (=> MRInterrupts, NKColdInts, NKSoftInts)
; KCallReturnFromException (=> NKReset)
; KCallReturnFromExceptionFastPath (=> NKSoftInts)
; LoadInterruptRegisters (=> NKColdInts, NKSoftInts)
; MRException (=> MRInterrupts, MROptabCode)
; ReturnFromInt (=> NKColdInts, NKLegacyVM, NKSoftInts)
; SwitchContext (=> NKSoftInts)
######################################################################## ########################################################################
; MemRetry error ; MemRetry error
MRException MRException
mtsprg 3, r24 mtsprg 3, r24
lwz r9, KDP.Enables(r1) lwz r9, KDP.Enables(r1)
extrwi r23, r17, 5, 26 ; extract accessLen field extrwi r23, r17, 5, 26 ; extract accessLen field
rlwnm. r9, r9, r8, 0, 0 ; BGE taken if exception disabled rlwnm. r9, r9, r8, 0, 0 ; BGE taken if exception disabled
bcl BO_IF, mrFlagDidLoad, LoadExtraMRRegs bcl BO_IF, mrFlagDidLoad, LoadExtraMRRegs
lwz r6, KDP.ContextPtr(r1) lwz r6, KDP.ContextPtr(r1)
_set r7, r16, bitContextFlagMemRetryErr _set r7, r16, bitContextFlagMemRetryErr
neg r23, r23 neg r23, r23
mtcrf crMaskFlags, r7 mtcrf crMaskFlags, r7
add r19, r19, r23 ; convert r19 from end address back to start address?? add r19, r19, r23 ; convert r19 from end address back to start address??
insrwi r7, r8, 8, 0 ; ec code -> high byte of flags insrwi r7, r8, 8, 0 ; ec code -> high byte of flags
slwi r8, r8, 2 ; increment counter slwi r8, r8, 2 ; increment counter
add r8, r8, r1 add r8, r8, r1
lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8) lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NKInfo.ExceptionCauseCounts(r8) stw r9, KDP.NKInfo.ExceptionCauseCounts(r8)
; Move regs from KDP to ContextBlock ; Move regs from KDP to ContextBlock
lwz r8, KDP.r7(r1) lwz r8, KDP.r7(r1)
stw r8, CB.r7+4(r6) stw r8, CB.r7+4(r6)
lwz r8, KDP.r8(r1) lwz r8, KDP.r8(r1)
stw r8, CB.r8+4(r6) stw r8, CB.r8+4(r6)
lwz r8, KDP.r9(r1) lwz r8, KDP.r9(r1)
stw r8, CB.r9+4(r6) stw r8, CB.r9+4(r6)
lwz r8, KDP.r10(r1) lwz r8, KDP.r10(r1)
stw r8, CB.r10+4(r6) stw r8, CB.r10+4(r6)
lwz r8, KDP.r11(r1) lwz r8, KDP.r11(r1)
stw r8, CB.r11+4(r6) stw r8, CB.r11+4(r6)
lwz r8, KDP.r12(r1) lwz r8, KDP.r12(r1)
stw r8, CB.r12+4(r6) stw r8, CB.r12+4(r6)
lwz r8, KDP.r13(r1) lwz r8, KDP.r13(r1)
stw r8, CB.r13+4(r6) stw r8, CB.r13+4(r6)
bge RunSystemContext ; Alt Context has left exception disabled => Sys Context bge RunSystemContext ; Alt Context has left exception disabled => Sys Context
;fall through ; exception enabled => run userspace handler ;fall through ; exception enabled => run userspace handler
######################################################################## ########################################################################
; Exception or MRException that is Enabled (i.e. not being auto-forced to System) ; Exception or MRException that is Enabled (i.e. not being auto-forced to System)
ExceptionCommon ExceptionCommon
stw r10, CB.FaultSrcPC+4(r6) ; Save r10/SRR0, r12/LR, r3, r4 stw r10, CB.FaultSrcPC+4(r6) ; Save r10/SRR0, r12/LR, r3, r4
stw r12, CB.FaultSrcLR+4(r6) stw r12, CB.FaultSrcLR+4(r6)
stw r3, CB.FaultSrcR3+4(r6) stw r3, CB.FaultSrcR3+4(r6)
stw r4, CB.FaultSrcR4+4(r6) stw r4, CB.FaultSrcR4+4(r6)
lwz r8, KDP.Enables(r1) ; Save Enables & Flags, inc ContextFlagMemRetryErr lwz r8, KDP.Enables(r1) ; Save Enables & Flags, inc ContextFlagMemRetryErr
stw r7, CB.IntraState.Flags(r6) stw r7, CB.IntraState.Flags(r6)
stw r8, CB.IntraState.Enables(r6) stw r8, CB.IntraState.Enables(r6)
; Use IntraState because context handles its own error ; Use IntraState because context handles its own error
li r8, 0 ; Enables=0 (any exceptions in handler go to System) li r8, 0 ; Enables=0 (any exceptions in handler go to System)
lwz r10, CB.IntraState.Handler+4(r6) ; SRR0 = handler addr lwz r10, CB.IntraState.Handler+4(r6) ; SRR0 = handler addr
lwz r4, CB.IntraState.HandlerArg+4(r6) ; r4 = arbitrary second argument lwz r4, CB.IntraState.HandlerArg+4(r6) ; r4 = arbitrary second argument
lwz r3, KDP.ECBPtrLogical(r1) ; r3 = ContextBlock ptr lwz r3, KDP.ECBPtrLogical(r1) ; r3 = ContextBlock ptr
bc BO_IF, bitGlobalFlagSystem, @sys bc BO_IF, bitGlobalFlagSystem, @sys
lwz r3, KDP.NCBCacheLA0(r1) lwz r3, KDP.NCBCacheLA0(r1)
@sys @sys
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; r12/LR = address of KCallReturnFromException trap lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; r12/LR = address of KCallReturnFromException trap
bcl BO_IF, bitContextFlagMemRetryErr, SaveFailingMemRetryState bcl BO_IF, bitContextFlagMemRetryErr, SaveFailingMemRetryState
rlwinm r7, r7, 0, 29, 15 ; unset flags 16-28 rlwinm r7, r7, 0, 29, 15 ; unset flags 16-28
stw r8, KDP.Enables(r1) stw r8, KDP.Enables(r1)
rlwimi r11, r7, 0, 20, 23 ; threfore unset MSR[FE0/SE/BE/FE1] rlwimi r11, r7, 0, 20, 23 ; threfore unset MSR[FE0/SE/BE/FE1]
b ReturnFromInt b ReturnFromInt
######################################################################## ########################################################################
LoadExtraMRRegs LoadExtraMRRegs
lwz r0, KDP.r0(r1) lwz r0, KDP.r0(r1)
lwz r2, KDP.r2(r1) lwz r2, KDP.r2(r1)
lwz r3, KDP.r3(r1) lwz r3, KDP.r3(r1)
lwz r4, KDP.r4(r1) lwz r4, KDP.r4(r1)
lwz r5, KDP.r5(r1) lwz r5, KDP.r5(r1)
blr blr
SaveFailingMemRetryState SaveFailingMemRetryState
stw r17, CB.IntraState.MemRet17+4(r6) stw r17, CB.IntraState.MemRet17+4(r6)
stw r20, CB.IntraState.MemRetData(r6) stw r20, CB.IntraState.MemRetData(r6)
stw r21, CB.IntraState.MemRetData+4(r6) stw r21, CB.IntraState.MemRetData+4(r6)
stw r19, CB.IntraState.MemRet19+4(r6) stw r19, CB.IntraState.MemRet19+4(r6)
stw r18, CB.IntraState.MemRet18+4(r6) stw r18, CB.IntraState.MemRet18+4(r6)
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
blr blr
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
KCallReturnFromExceptionFastPath KCallReturnFromExceptionFastPath
lwz r11, KDP.NKInfo.NanoKernelCallCounts(r1) lwz r11, KDP.NKInfo.NanoKernelCallCounts(r1)
mr r10, r12 mr r10, r12
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NKInfo.NanoKernelCallCounts(r1) stw r11, KDP.NKInfo.NanoKernelCallCounts(r1)
mfsrr1 r11 mfsrr1 r11
rlwimi r7, r7, 32+bitMsrSE-bitContextFlagTraceWhenDone, ContextFlagTraceWhenDone rlwimi r7, r7, 32+bitMsrSE-bitContextFlagTraceWhenDone, ContextFlagTraceWhenDone
KCallReturnFromException KCallReturnFromException
cmplwi cr1, r3, 1 ; exception handler return value cmplwi cr1, r3, 1 ; exception handler return value
blt cr1, @dispose blt cr1, @dispose
mtcrf crMaskFlags, r7 mtcrf crMaskFlags, r7
beq cr1, @propagate beq cr1, @propagate
; If handler returns an exception cause code 2-255, "force" this exception to the System Context. ; If handler returns an exception cause code 2-255, "force" this exception to the System Context.
subi r8, r3, 32 subi r8, r3, 32
lwz r9, KDP.NKInfo.ExceptionForcedCount(r1) lwz r9, KDP.NKInfo.ExceptionForcedCount(r1)
cmplwi r8, 256-32 cmplwi r8, 256-32
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NKInfo.ExceptionForcedCount(r1) stw r9, KDP.NKInfo.ExceptionForcedCount(r1)
insrwi r7, r3, 8, 0 insrwi r7, r3, 8, 0
blt RunSystemContext blt RunSystemContext
li r8, ecTrapInstr li r8, ecTrapInstr
b Exception ; (error if number is > max exception number) b Exception ; (error if number is > max exception number)
; If handler returns 0 (System Context must always do this), return to userspace. ; If handler returns 0 (System Context must always do this), return to userspace.
@dispose @dispose
lwz r8, CB.IntraState.Flags(r6) ; Restore Context flags (inc exception number?) lwz r8, CB.IntraState.Flags(r6) ; Restore Context flags (inc exception number?)
lwz r10, CB.FaultSrcPC+4(r6) lwz r10, CB.FaultSrcPC+4(r6)
rlwimi r7, r8, 0, maskExceptionNum | maskContextFlags ; preserve global flags rlwimi r7, r8, 0, maskExceptionNum | maskContextFlags ; preserve global flags
lwz r8, CB.IntraState.Enables(r6) lwz r8, CB.IntraState.Enables(r6)
rlwimi r11, r7, 0, maskMsrFlags rlwimi r11, r7, 0, maskMsrFlags
stw r8, KDP.Enables(r1) stw r8, KDP.Enables(r1)
andi. r8, r11, MsrFE0 + MsrFE1 ; check: are floating-pt exceptions enabled? andi. r8, r11, MsrFE0 + MsrFE1 ; check: are floating-pt exceptions enabled?
lwz r12, CB.FaultSrcLR+4(r6) ; restore LR/r3/r4 lwz r12, CB.FaultSrcLR+4(r6) ; restore LR/r3/r4
lwz r3, CB.FaultSrcR3+4(r6) lwz r3, CB.FaultSrcR3+4(r6)
lwz r4, CB.FaultSrcR4+4(r6) lwz r4, CB.FaultSrcR4+4(r6)
bnel EnableFPU bnel EnableFPU
addi r9, r6, CB.IntraState ; If MemRetry was interrupted, resume it. addi r9, r6, CB.IntraState ; If MemRetry was interrupted, resume it.
b ReturnFromInt b ReturnFromInt
; If handler returns 1, "propagate" this exception to the System Context ; If handler returns 1, "propagate" this exception to the System Context
; (When we get back to the Alternate Context, it will be as if the exception was disposed.) ; (When we get back to the Alternate Context, it will be as if the exception was disposed.)
@propagate @propagate
lwz r9, KDP.NKInfo.ExceptionPropagateCount(r1) lwz r9, KDP.NKInfo.ExceptionPropagateCount(r1)
lwz r8, CB.IntraState.Flags(r6) lwz r8, CB.IntraState.Flags(r6)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NKInfo.ExceptionPropagateCount(r1) stw r9, KDP.NKInfo.ExceptionPropagateCount(r1)
lwz r10, CB.FaultSrcPC+4(r6) lwz r10, CB.FaultSrcPC+4(r6)
rlwimi r7, r8, 0, maskExceptionNum | maskContextFlags ; preserve global flags rlwimi r7, r8, 0, maskExceptionNum | maskContextFlags ; preserve global flags
lwz r8, CB.IntraState.Enables(r6) lwz r8, CB.IntraState.Enables(r6)
mtcrf crMaskContextFlags, r7 mtcrf crMaskContextFlags, r7
rlwimi r11, r7, 0, maskMsrFlags rlwimi r11, r7, 0, maskMsrFlags
stw r8, KDP.Enables(r1) stw r8, KDP.Enables(r1)
lwz r12, CB.FaultSrcLR+4(r6) ; restore LR/r3/r4 lwz r12, CB.FaultSrcLR+4(r6) ; restore LR/r3/r4
lwz r3, CB.FaultSrcR3+4(r6) lwz r3, CB.FaultSrcR3+4(r6)
lwz r4, CB.FaultSrcR4+4(r6) lwz r4, CB.FaultSrcR4+4(r6)
bc BO_IF_NOT, bitContextFlagMemRetryErr, RunSystemContext bc BO_IF_NOT, bitContextFlagMemRetryErr, RunSystemContext
stmw r14, KDP.r14(r1) ; When we *do* get back to this context, stmw r14, KDP.r14(r1) ; When we *do* get back to this context,
lwz r17, CB.IntraState.MemRet17+4(r6) ; make sure MemRetry state can be resumed lwz r17, CB.IntraState.MemRet17+4(r6) ; make sure MemRetry state can be resumed
lwz r20, CB.IntraState.MemRetData(r6) ; from InterState lwz r20, CB.IntraState.MemRetData(r6) ; from InterState
lwz r21, CB.IntraState.MemRetData+4(r6) lwz r21, CB.IntraState.MemRetData+4(r6)
lwz r19, CB.IntraState.MemRet19+4(r6) lwz r19, CB.IntraState.MemRet19+4(r6)
lwz r18, CB.IntraState.MemRet18+4(r6) lwz r18, CB.IntraState.MemRet18+4(r6)
b RunSystemContext b RunSystemContext
######################################################################## ########################################################################
; BEFORE ; BEFORE
; PowerPC exception vector saved r1/LR in SPRG1/2 and ; PowerPC exception vector saved r1/LR in SPRG1/2 and
; jumped where directed by the VecTbl pointed to by ; jumped where directed by the VecTbl pointed to by
; SPRG3. That function bl'ed here. ; SPRG3. That function bl'ed here.
; ;
; AFTER ; AFTER
; Reg Contains Original saved in ; Reg Contains Original saved in
; --------------------------------------------- ; ---------------------------------------------
; r0 (itself) ; r0 (itself)
; r1 KDP SPRG1 ; r1 KDP SPRG1
; r2 (itself) ; r2 (itself)
; r3 (itself) ; r3 (itself)
; r4 (itself) ; r4 (itself)
; r5 (itself) ; r5 (itself)
; r6 ContextBlock EWA ; r6 ContextBlock EWA
; r7 Flags ContextBlock ; r7 Flags ContextBlock
; r8 KDP ContextBlock ; r8 KDP ContextBlock
; r9 (scratch CB ptr) ContextBlock ; r9 (scratch CB ptr) ContextBlock
; r10 SRR0 ContextBlock ; r10 SRR0 ContextBlock
; r11 SRR1 ContextBlock ; r11 SRR1 ContextBlock
; r12 LR ContextBlock ; r12 LR ContextBlock
; r13 CR ContextBlock ; r13 CR ContextBlock
LoadInterruptRegisters LoadInterruptRegisters
mfsprg r1, 0 mfsprg r1, 0
stw r6, KDP.r6(r1) stw r6, KDP.r6(r1)
mfsprg r6, 1 mfsprg r6, 1
stw r6, KDP.r1(r1) stw r6, KDP.r1(r1)
lwz r6, KDP.ContextPtr(r1) lwz r6, KDP.ContextPtr(r1)
stw r7, CB.r7+4(r6) stw r7, CB.r7+4(r6)
stw r8, CB.r8+4(r6) stw r8, CB.r8+4(r6)
stw r9, CB.r9+4(r6) stw r9, CB.r9+4(r6)
stw r10, CB.r10+4(r6) stw r10, CB.r10+4(r6)
stw r11, CB.r11+4(r6) stw r11, CB.r11+4(r6)
stw r12, CB.r12+4(r6) stw r12, CB.r12+4(r6)
stw r13, CB.r13+4(r6) stw r13, CB.r13+4(r6)
mfsrr0 r10 mfsrr0 r10
mfcr r13 mfcr r13
lwz r7, KDP.Flags(r1) lwz r7, KDP.Flags(r1)
mfsprg r12, 2 mfsprg r12, 2
mfsrr1 r11 mfsrr1 r11
blr blr
######################################################################## ########################################################################
Exception Exception
lwz r9, KDP.Enables(r1) lwz r9, KDP.Enables(r1)
mtcrf crMaskFlags, r7 mtcrf crMaskFlags, r7
rlwnm. r9, r9, r8, 0, 0 ; BLT taken if exception enabled rlwnm. r9, r9, r8, 0, 0 ; BLT taken if exception enabled
insrwi r7, r8, 8, 0 ; Exception code to hi byte of Flags insrwi r7, r8, 8, 0 ; Exception code to hi byte of Flags
slwi r8, r8, 2 ; Increment counter, easy enough slwi r8, r8, 2 ; Increment counter, easy enough
add r8, r8, r1 add r8, r8, r1
lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8) lwz r9, KDP.NKInfo.ExceptionCauseCounts(r8)
addi r9, r9, 1 addi r9, r9, 1
stw r9, KDP.NKInfo.ExceptionCauseCounts(r8) stw r9, KDP.NKInfo.ExceptionCauseCounts(r8)
blt ExceptionCommon ; exception enabled => run userspace handler blt ExceptionCommon ; exception enabled => run userspace handler
;fall through ; Alt Context has left exception disabled => Sys Context ;fall through ; Alt Context has left exception disabled => Sys Context
######################################################################## ########################################################################
RunSystemContext RunSystemContext
lwz r9, KDP.ECBPtr(r1) ; System ("Emulator") ContextBlock lwz r9, KDP.ECBPtr(r1) ; System ("Emulator") ContextBlock
addi r8, r1, KDP.VecTblSystem ; System VecTbl addi r8, r1, KDP.VecTblSystem ; System VecTbl
mtsprg 3, r8 mtsprg 3, r8
bcl BO_IF, bitGlobalFlagSystem, SystemCrash ; System Context already running! bcl BO_IF, bitGlobalFlagSystem, SystemCrash ; System Context already running!
; Fallthru (new CB in r9, old CB in r6) ; Fallthru (new CB in r9, old CB in r6)
######################################################################## ########################################################################
SwitchContext ; OldCB *r6, NewCB *r9 SwitchContext ; OldCB *r6, NewCB *r9
; Run the System or Alternate Context ; Run the System or Alternate Context
lwz r8, KDP.Enables(r1) lwz r8, KDP.Enables(r1)
stw r7, CB.InterState.Flags(r6) stw r7, CB.InterState.Flags(r6)
stw r8, CB.InterState.Enables(r6) stw r8, CB.InterState.Enables(r6)
bc BO_IF_NOT, bitContextFlagMemRetryErr, @can_dispose_mr_state bc BO_IF_NOT, bitContextFlagMemRetryErr, @can_dispose_mr_state
stw r17, CB.InterState.MemRet17+4(r6) stw r17, CB.InterState.MemRet17+4(r6)
stw r20, CB.InterState.MemRetData(r6) stw r20, CB.InterState.MemRetData(r6)
stw r21, CB.InterState.MemRetData+4(r6) stw r21, CB.InterState.MemRetData+4(r6)
stw r19, CB.InterState.MemRet19+4(r6) stw r19, CB.InterState.MemRet19+4(r6)
stw r18, CB.InterState.MemRet18+4(r6) stw r18, CB.InterState.MemRet18+4(r6)
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
@can_dispose_mr_state @can_dispose_mr_state
mfxer r8 mfxer r8
stw r13, CB.CR+4(r6) stw r13, CB.CR+4(r6)
stw r8, CB.XER+4(r6) stw r8, CB.XER+4(r6)
stw r12, CB.LR+4(r6) stw r12, CB.LR+4(r6)
mfctr r8 mfctr r8
stw r10, CB.PC+4(r6) stw r10, CB.PC+4(r6)
stw r8, CB.CTR+4(r6) stw r8, CB.CTR+4(r6)
bc BO_IF_NOT, bitGlobalFlagMQReg, @no_mq bc BO_IF_NOT, bitGlobalFlagMQReg, @no_mq
lwz r8, CB.MQ+4(r9) lwz r8, CB.MQ+4(r9)
mfspr r12, mq mfspr r12, mq
mtspr mq, r8 mtspr mq, r8
stw r12, CB.MQ+4(r6) stw r12, CB.MQ+4(r6)
@no_mq @no_mq
lwz r8, KDP.r1(r1) lwz r8, KDP.r1(r1)
stw r0, CB.r0+4(r6) stw r0, CB.r0+4(r6)
stw r8, CB.r1+4(r6) stw r8, CB.r1+4(r6)
stw r2, CB.r2+4(r6) stw r2, CB.r2+4(r6)
stw r3, CB.r3+4(r6) stw r3, CB.r3+4(r6)
stw r4, CB.r4+4(r6) stw r4, CB.r4+4(r6)
lwz r8, KDP.r6(r1) lwz r8, KDP.r6(r1)
stw r5, CB.r5+4(r6) stw r5, CB.r5+4(r6)
stw r8, CB.r6+4(r6) stw r8, CB.r6+4(r6)
_band. r8, r11, bitMsrFP _band. r8, r11, bitMsrFP
stw r14, CB.r14+4(r6) stw r14, CB.r14+4(r6)
stw r15, CB.r15+4(r6) stw r15, CB.r15+4(r6)
stw r16, CB.r16+4(r6) stw r16, CB.r16+4(r6)
stw r17, CB.r17+4(r6) stw r17, CB.r17+4(r6)
stw r18, CB.r18+4(r6) stw r18, CB.r18+4(r6)
stw r19, CB.r19+4(r6) stw r19, CB.r19+4(r6)
stw r20, CB.r20+4(r6) stw r20, CB.r20+4(r6)
stw r21, CB.r21+4(r6) stw r21, CB.r21+4(r6)
stw r22, CB.r22+4(r6) stw r22, CB.r22+4(r6)
stw r23, CB.r23+4(r6) stw r23, CB.r23+4(r6)
stw r24, CB.r24+4(r6) stw r24, CB.r24+4(r6)
stw r25, CB.r25+4(r6) stw r25, CB.r25+4(r6)
stw r26, CB.r26+4(r6) stw r26, CB.r26+4(r6)
stw r27, CB.r27+4(r6) stw r27, CB.r27+4(r6)
stw r28, CB.r28+4(r6) stw r28, CB.r28+4(r6)
stw r29, CB.r29+4(r6) stw r29, CB.r29+4(r6)
stw r30, CB.r30+4(r6) stw r30, CB.r30+4(r6)
stw r31, CB.r31+4(r6) stw r31, CB.r31+4(r6)
bnel DisableFPU bnel DisableFPU
lwz r8, KDP.OtherContextDEC(r1) lwz r8, KDP.OtherContextDEC(r1)
mfdec r31 mfdec r31
cmpwi r8, 0 cmpwi r8, 0
stw r31, KDP.OtherContextDEC(r1) stw r31, KDP.OtherContextDEC(r1)
mtdec r8 mtdec r8
blel ResetDEC ; to r8 blel ResetDEC ; to r8
lwz r8, CB.InterState.Flags(r9) ; r8 is the new Flags variable lwz r8, CB.InterState.Flags(r9) ; r8 is the new Flags variable
stw r9, KDP.ContextPtr(r1) stw r9, KDP.ContextPtr(r1)
xoris r7, r7, GlobalFlagSystem >> 16 ; flip Emulator flag xoris r7, r7, GlobalFlagSystem >> 16 ; flip Emulator flag
rlwimi r11, r8, 0, maskMsrFlags rlwimi r11, r8, 0, maskMsrFlags
mr r6, r9 ; change the magic ContextBlock register mr r6, r9 ; change the magic ContextBlock register
rlwimi r7, r8, 0, maskContextFlags ; change bottom half of flags only rlwimi r7, r8, 0, maskContextFlags ; change bottom half of flags only
andi. r8, r11, MsrFE0 + MsrFE1 ; FP exceptions enabled in new context? andi. r8, r11, MsrFE0 + MsrFE1 ; FP exceptions enabled in new context?
lwz r8, CB.InterState.Enables(r6) lwz r8, CB.InterState.Enables(r6)
lwz r13, CB.CR+4(r6) lwz r13, CB.CR+4(r6)
stw r8, KDP.Enables(r1) stw r8, KDP.Enables(r1)
lwz r8, CB.XER+4(r6) lwz r8, CB.XER+4(r6)
lwz r12, CB.LR+4(r6) lwz r12, CB.LR+4(r6)
mtxer r8 mtxer r8
lwz r8, CB.CTR+4(r6) lwz r8, CB.CTR+4(r6)
lwz r10, CB.PC+4(r6) lwz r10, CB.PC+4(r6)
mtctr r8 mtctr r8
bnel ReloadFPU ; FP exceptions enabled, so load FPU bnel ReloadFPU ; FP exceptions enabled, so load FPU
stwcx. r0, 0, r1 stwcx. r0, 0, r1
lwz r8, CB.r1+4(r6) lwz r8, CB.r1+4(r6)
lwz r0, CB.r0+4(r6) lwz r0, CB.r0+4(r6)
stw r8, KDP.r1(r1) stw r8, KDP.r1(r1)
lwz r2, CB.r2+4(r6) lwz r2, CB.r2+4(r6)
lwz r3, CB.r3+4(r6) lwz r3, CB.r3+4(r6)
lwz r4, CB.r4+4(r6) lwz r4, CB.r4+4(r6)
lwz r8, CB.r6+4(r6) lwz r8, CB.r6+4(r6)
lwz r5, CB.r5+4(r6) lwz r5, CB.r5+4(r6)
stw r8, KDP.r6(r1) stw r8, KDP.r6(r1)
lwz r14, CB.r14+4(r6) lwz r14, CB.r14+4(r6)
lwz r15, CB.r15+4(r6) lwz r15, CB.r15+4(r6)
lwz r16, CB.r16+4(r6) lwz r16, CB.r16+4(r6)
lwz r17, CB.r17+4(r6) lwz r17, CB.r17+4(r6)
lwz r18, CB.r18+4(r6) lwz r18, CB.r18+4(r6)
lwz r19, CB.r19+4(r6) lwz r19, CB.r19+4(r6)
lwz r20, CB.r20+4(r6) lwz r20, CB.r20+4(r6)
lwz r21, CB.r21+4(r6) lwz r21, CB.r21+4(r6)
lwz r22, CB.r22+4(r6) lwz r22, CB.r22+4(r6)
lwz r23, CB.r23+4(r6) lwz r23, CB.r23+4(r6)
lwz r24, CB.r24+4(r6) lwz r24, CB.r24+4(r6)
lwz r25, CB.r25+4(r6) lwz r25, CB.r25+4(r6)
lwz r26, CB.r26+4(r6) lwz r26, CB.r26+4(r6)
lwz r27, CB.r27+4(r6) lwz r27, CB.r27+4(r6)
lwz r28, CB.r28+4(r6) lwz r28, CB.r28+4(r6)
lwz r29, CB.r29+4(r6) lwz r29, CB.r29+4(r6)
lwz r30, CB.r30+4(r6) lwz r30, CB.r30+4(r6)
lwz r31, CB.r31+4(r6) lwz r31, CB.r31+4(r6)
######################################################################## ########################################################################
ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please pass KernelState ptr in r9 ReturnFromInt ; If ContextFlagMemRetryErr && ContextFlagResumeMemRetry, please pass KernelState ptr in r9
andi. r8, r7, ContextFlagTraceWhenDone | ContextFlagMemRetryErr andi. r8, r7, ContextFlagTraceWhenDone | ContextFlagMemRetryErr
bnel @special_cases ; Keep rare cases out of the hot path bnel @special_cases ; Keep rare cases out of the hot path
stw r7, KDP.Flags(r1) ; Save kernel flags for next interrupt stw r7, KDP.Flags(r1) ; Save kernel flags for next interrupt
mtlr r12 ; Restore user SPRs from kernel GPRs mtlr r12 ; Restore user SPRs from kernel GPRs
mtsrr0 r10 mtsrr0 r10
mtsrr1 r11 mtsrr1 r11
mtcr r13 mtcr r13
lwz r10, CB.r10+4(r6) ; Restore user GPRs from ContextBlock lwz r10, CB.r10+4(r6) ; Restore user GPRs from ContextBlock
lwz r11, CB.r11+4(r6) lwz r11, CB.r11+4(r6)
lwz r12, CB.r12+4(r6) lwz r12, CB.r12+4(r6)
lwz r13, CB.r13+4(r6) lwz r13, CB.r13+4(r6)
lwz r7, CB.r7+4(r6) lwz r7, CB.r7+4(r6)
lwz r8, CB.r8+4(r6) lwz r8, CB.r8+4(r6)
lwz r9, CB.r9+4(r6) lwz r9, CB.r9+4(r6)
lwz r6, KDP.r6(r1) ; Restore last two registers from EWA lwz r6, KDP.r6(r1) ; Restore last two registers from EWA
lwz r1, KDP.r1(r1) lwz r1, KDP.r1(r1)
rfi ; Go rfi ; Go
@special_cases @special_cases
mtcrf crMaskFlags, r7 mtcrf crMaskFlags, r7
bc BO_IF_NOT, bitContextFlagMemRetryErr, @no_memretry ; If MemRetry had to be paused for an exception bc BO_IF_NOT, bitContextFlagMemRetryErr, @no_memretry ; If MemRetry had to be paused for an exception
_clear r7, r7, bitContextFlagMemRetryErr ; which is now finished, finish MemRetry. _clear r7, r7, bitContextFlagMemRetryErr ; which is now finished, finish MemRetry.
bc BO_IF, bitContextFlagResumeMemRetry, @resume_memretry bc BO_IF, bitContextFlagResumeMemRetry, @resume_memretry
_clear r7, r7, bitContextFlagTraceWhenDone _clear r7, r7, bitContextFlagTraceWhenDone
b @justreturn b @justreturn
@no_memretry @no_memretry
bc BO_IF_NOT, bitContextFlagTraceWhenDone, @justreturn ; If this current interrupt was raised when bc BO_IF_NOT, bitContextFlagTraceWhenDone, @justreturn ; If this current interrupt was raised when
_clear r7, r7, bitContextFlagTraceWhenDone ; every instruction should be followed by a _clear r7, r7, bitContextFlagTraceWhenDone ; every instruction should be followed by a
stw r7, KDP.Flags(r1) ; Trace exception, then raise one. stw r7, KDP.Flags(r1) ; Trace exception, then raise one.
li r8, ecInstTrace li r8, ecInstTrace
b Exception b Exception
@justreturn @justreturn
blr blr
@resume_memretry ; Pick up where an MRException left off, now that the Exception has been disposed. @resume_memretry ; Pick up where an MRException left off, now that the Exception has been disposed.
stw r7, KDP.Flags(r1) stw r7, KDP.Flags(r1)
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r2, KDP.r2(r1) stw r2, KDP.r2(r1)
stw r3, KDP.r3(r1) stw r3, KDP.r3(r1)
stw r4, KDP.r4(r1) stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1) stw r5, KDP.r5(r1)
lwz r8, CB.r7+4(r6) lwz r8, CB.r7+4(r6)
stw r8, KDP.r7(r1) stw r8, KDP.r7(r1)
lwz r8, CB.r8+4(r6) lwz r8, CB.r8+4(r6)
stw r8, KDP.r8(r1) stw r8, KDP.r8(r1)
lwz r8, CB.r9+4(r6) lwz r8, CB.r9+4(r6)
stw r8, KDP.r9(r1) stw r8, KDP.r9(r1)
lwz r8, CB.r10+4(r6) lwz r8, CB.r10+4(r6)
stw r8, KDP.r10(r1) stw r8, KDP.r10(r1)
lwz r8, CB.r11+4(r6) lwz r8, CB.r11+4(r6)
stw r8, KDP.r11(r1) stw r8, KDP.r11(r1)
lwz r8, CB.r12+4(r6) lwz r8, CB.r12+4(r6)
stw r8, KDP.r12(r1) stw r8, KDP.r12(r1)
lwz r8, CB.r13+4(r6) lwz r8, CB.r13+4(r6)
stw r8, KDP.r13(r1) stw r8, KDP.r13(r1)
stmw r14, KDP.r14(r1) stmw r14, KDP.r14(r1)
lwz r17, KernelState.MemRet17+4(r9) ; Get the MR state from IntraState (if context was never switched) lwz r17, KernelState.MemRet17+4(r9) ; Get the MR state from IntraState (if context was never switched)
lwz r20, KernelState.MemRetData(r9) ; or InterState (if exception was propagated to System Context and lwz r20, KernelState.MemRetData(r9) ; or InterState (if exception was propagated to System Context and
lwz r21, KernelState.MemRetData+4(r9) ; we are now switching back to Alternate Context). lwz r21, KernelState.MemRetData+4(r9) ; we are now switching back to Alternate Context).
lwz r19, KernelState.MemRet19+4(r9) lwz r19, KernelState.MemRet19+4(r9)
lwz r18, KernelState.MemRet18+4(r9) lwz r18, KernelState.MemRet18+4(r9)
_clear r16, r7, bitContextFlagMemRetryErr _clear r16, r7, bitContextFlagMemRetryErr
lwz r25, KDP.MRBase(r1) ; MRRestab is indexed by the first arg of MROptab? lwz r25, KDP.MRBase(r1) ; MRRestab is indexed by the first arg of MROptab?
extrwi. r22, r17, 4, 27 ; extrwi. r22, r17, 4, 27 ;
add r19, r19, r22 ; Correct r19 (EA) by adding len from r17 add r19, r19, r22 ; Correct r19 (EA) by adding len from r17
rlwimi r25, r17, 7, 25, 30 rlwimi r25, r17, 7, 25, 30
lhz r26, MRRestab-MRBase(r25) lhz r26, MRRestab-MRBase(r25)
insrwi r25, r19, 3, 28 ; Set Memtab alignment modulus insrwi r25, r19, 3, 28 ; Set Memtab alignment modulus
stw r16, KDP.Flags(r1) stw r16, KDP.Flags(r1)
rlwimi r26, r26, 8, 8, 15 ; First byte of MRRestab is for cr3/cr4 rlwimi r26, r26, 8, 8, 15 ; First byte of MRRestab is for cr3/cr4
insrwi r25, r17, 4, 24 ; len and load/store from second arg of MROptab? insrwi r25, r17, 4, 24 ; len and load/store from second arg of MROptab?
mtcrf 0x10, r26 ; Set CR3 mtcrf 0x10, r26 ; Set CR3
lha r22, MRMemtab-MRBase(r25) ; Jump to MRMemtab... lha r22, MRMemtab-MRBase(r25) ; Jump to MRMemtab...
addi r23, r1, KDP.VecTblMemRetry addi r23, r1, KDP.VecTblMemRetry
add r22, r22, r25 add r22, r22, r25
mfsprg r24, 3 mfsprg r24, 3
mtlr r22 mtlr r22
mtsprg 3, r23 mtsprg 3, r23
mfmsr r14 mfmsr r14
_set r15, r14, bitMsrDR _set r15, r14, bitMsrDR
mtmsr r15 mtmsr r15
rlwimi r25, r26, 2, 22, 29 ; Second byte of MRRestab is a secondary routine rlwimi r25, r26, 2, 22, 29 ; Second byte of MRRestab is a secondary routine
bnelr bnelr
b MRDoSecondary b MRDoSecondary
######################################################################## ########################################################################
ResetDEC ; to r8 ResetDEC ; to r8
lis r31, 0x7FFF lis r31, 0x7FFF
mtdec r31 mtdec r31
mtdec r8 mtdec r8
blr blr

245
NanoKernel/NKFloatingPt.s
View File

@ -1,155 +1,166 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MROptabCode
; MRDoneTableSTFD
; MRSecDone
; EXPORTS:
; DisableFPU (=> NKExceptions)
; EnableFPU (=> NKExceptions)
; FPUnavailInt (=> NKReset)
; LFDTable (=> MROptabCode)
; ReloadFPU (=> NKExceptions)
; STFDTable (=> MROptabCode)
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
FPUnavailInt FPUnavailInt
; Reload the FPU ; Reload the FPU
mfsprg r1, 0 mfsprg r1, 0
stw r11, KDP.FloatingPtTemp1(r1) stw r11, KDP.FloatingPtTemp1(r1)
lwz r11, KDP.NKInfo.FPUReloadCount(r1) lwz r11, KDP.NKInfo.FPUReloadCount(r1)
stw r6, KDP.FloatingPtTemp2(r1) stw r6, KDP.FloatingPtTemp2(r1)
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NKInfo.FPUReloadCount(r1) stw r11, KDP.NKInfo.FPUReloadCount(r1)
mfsrr1 r11 mfsrr1 r11
_set r11, r11, bitMsrFP _set r11, r11, bitMsrFP
mtsrr1 r11 mtsrr1 r11
mfmsr r11 ; need this to access float registers mfmsr r11 ; need this to access float registers
_set r11, r11, bitMsrFP _set r11, r11, bitMsrFP
lwz r6, KDP.ContextPtr(r1) lwz r6, KDP.ContextPtr(r1)
mtmsr r11 mtmsr r11
bl LoadFloats bl LoadFloats
lwz r11, KDP.FloatingPtTemp1(r1) lwz r11, KDP.FloatingPtTemp1(r1)
lwz r6, KDP.FloatingPtTemp2(r1) lwz r6, KDP.FloatingPtTemp2(r1)
mfsprg r1, 2 mfsprg r1, 2
mtlr r1 mtlr r1
mfsprg r1, 1 mfsprg r1, 1
rfi rfi
######################################################################## ########################################################################
EnableFPU EnableFPU
rlwinm. r8, r11, 0, 18, 18 rlwinm. r8, r11, 0, 18, 18
bnelr bnelr
ReloadFPU ReloadFPU
lwz r8, CB.FPSCR+4(r6) lwz r8, CB.FPSCR+4(r6)
rlwinm. r8, r8, 1, 0, 0 rlwinm. r8, r8, 1, 0, 0
mfmsr r8 mfmsr r8
_set r8, r8, bitMsrFP _set r8, r8, bitMsrFP
beqlr beqlr
mtmsr r8 mtmsr r8
_set r11, r11, bitMsrFP _set r11, r11, bitMsrFP
######################################################################## ########################################################################
LoadFloats LoadFloats
lfd f31, CB.FPSCR(r6) lfd f31, CB.FPSCR(r6)
lfd f0, CB.f0(r6) lfd f0, CB.f0(r6)
lfd f1, CB.f1(r6) lfd f1, CB.f1(r6)
lfd f2, CB.f2(r6) lfd f2, CB.f2(r6)
lfd f3, CB.f3(r6) lfd f3, CB.f3(r6)
lfd f4, CB.f4(r6) lfd f4, CB.f4(r6)
lfd f5, CB.f5(r6) lfd f5, CB.f5(r6)
lfd f6, CB.f6(r6) lfd f6, CB.f6(r6)
lfd f7, CB.f7(r6) lfd f7, CB.f7(r6)
mtfs f31 mtfs f31
lfd f8, CB.f8(r6) lfd f8, CB.f8(r6)
lfd f9, CB.f9(r6) lfd f9, CB.f9(r6)
lfd f10, CB.f10(r6) lfd f10, CB.f10(r6)
lfd f11, CB.f11(r6) lfd f11, CB.f11(r6)
lfd f12, CB.f12(r6) lfd f12, CB.f12(r6)
lfd f13, CB.f13(r6) lfd f13, CB.f13(r6)
lfd f14, CB.f14(r6) lfd f14, CB.f14(r6)
lfd f15, CB.f15(r6) lfd f15, CB.f15(r6)
lfd f16, CB.f16(r6) lfd f16, CB.f16(r6)
lfd f17, CB.f17(r6) lfd f17, CB.f17(r6)
lfd f18, CB.f18(r6) lfd f18, CB.f18(r6)
lfd f19, CB.f19(r6) lfd f19, CB.f19(r6)
lfd f20, CB.f20(r6) lfd f20, CB.f20(r6)
lfd f21, CB.f21(r6) lfd f21, CB.f21(r6)
lfd f22, CB.f22(r6) lfd f22, CB.f22(r6)
lfd f23, CB.f23(r6) lfd f23, CB.f23(r6)
lfd f24, CB.f24(r6) lfd f24, CB.f24(r6)
lfd f25, CB.f25(r6) lfd f25, CB.f25(r6)
lfd f26, CB.f26(r6) lfd f26, CB.f26(r6)
lfd f27, CB.f27(r6) lfd f27, CB.f27(r6)
lfd f28, CB.f28(r6) lfd f28, CB.f28(r6)
lfd f29, CB.f29(r6) lfd f29, CB.f29(r6)
lfd f30, CB.f30(r6) lfd f30, CB.f30(r6)
lfd f31, CB.f31(r6) lfd f31, CB.f31(r6)
blr blr
######################################################################## ########################################################################
DisableFPU DisableFPU
mfmsr r8 mfmsr r8
_set r8, r8, bitMsrFP _set r8, r8, bitMsrFP
mtmsr r8 mtmsr r8
_clear r11, r11, bitMsrFP _clear r11, r11, bitMsrFP
stfd f0, CB.f0(r6) stfd f0, CB.f0(r6)
stfd f1, CB.f1(r6) stfd f1, CB.f1(r6)
stfd f2, CB.f2(r6) stfd f2, CB.f2(r6)
stfd f3, CB.f3(r6) stfd f3, CB.f3(r6)
stfd f4, CB.f4(r6) stfd f4, CB.f4(r6)
stfd f5, CB.f5(r6) stfd f5, CB.f5(r6)
stfd f6, CB.f6(r6) stfd f6, CB.f6(r6)
stfd f7, CB.f7(r6) stfd f7, CB.f7(r6)
stfd f8, CB.f8(r6) stfd f8, CB.f8(r6)
stfd f9, CB.f9(r6) stfd f9, CB.f9(r6)
stfd f10, CB.f10(r6) stfd f10, CB.f10(r6)
stfd f11, CB.f11(r6) stfd f11, CB.f11(r6)
stfd f12, CB.f12(r6) stfd f12, CB.f12(r6)
stfd f13, CB.f13(r6) stfd f13, CB.f13(r6)
stfd f14, CB.f14(r6) stfd f14, CB.f14(r6)
stfd f15, CB.f15(r6) stfd f15, CB.f15(r6)
stfd f16, CB.f16(r6) stfd f16, CB.f16(r6)
stfd f17, CB.f17(r6) stfd f17, CB.f17(r6)
stfd f18, CB.f18(r6) stfd f18, CB.f18(r6)
stfd f19, CB.f19(r6) stfd f19, CB.f19(r6)
stfd f20, CB.f20(r6) stfd f20, CB.f20(r6)
stfd f21, CB.f21(r6) stfd f21, CB.f21(r6)
stfd f22, CB.f22(r6) stfd f22, CB.f22(r6)
stfd f23, CB.f23(r6) stfd f23, CB.f23(r6)
mffs f0 mffs f0
stfd f24, CB.f24(r6) stfd f24, CB.f24(r6)
stfd f25, CB.f25(r6) stfd f25, CB.f25(r6)
stfd f26, CB.f26(r6) stfd f26, CB.f26(r6)
stfd f27, CB.f27(r6) stfd f27, CB.f27(r6)
stfd f28, CB.f28(r6) stfd f28, CB.f28(r6)
stfd f29, CB.f29(r6) stfd f29, CB.f29(r6)
stfd f30, CB.f30(r6) stfd f30, CB.f30(r6)
stfd f31, CB.f31(r6) stfd f31, CB.f31(r6)
stfd f0, CB.FPSCR(r6) stfd f0, CB.FPSCR(r6)
blr blr
######################################################################## ########################################################################
; This is used by MemRetry ; This is used by MemRetry
MACRO MACRO
MakeFloatJumpTable &OPCODE, &DEST, &highest==31 MakeFloatJumpTable &OPCODE, &DEST, &highest==31
if &highest > 0 if &highest > 0
MakeFloatJumpTable &OPCODE, &DEST, highest = (&highest) - 1 MakeFloatJumpTable &OPCODE, &DEST, highest = (&highest) - 1
endif endif
&OPCODE &highest, KDP.FloatScratch(r1) &OPCODE &highest, KDP.FloatScratch(r1)
b &DEST b &DEST
ENDM ENDM
LFDTable LFDTable
MakeFloatJumpTable lfd, MRSecDone MakeFloatJumpTable lfd, MRSecDone
STFDTable STFDTable
MakeFloatJumpTable stfd, MRDoneTableSTFD MakeFloatJumpTable stfd, MRDoneTableSTFD

607
NanoKernel/NKHotInts.s
View File

@ -1,379 +1,392 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MROptab
; MROptabD
; MROptabX
; EXPORTS:
; AlignmentInt (=> NKReset)
; DataStorageInt (=> NKReset)
; DecrementerIntAlt (=> NKReset)
; DecrementerIntSys (=> NKReset)
; EmulateDataAccess (=> NKSoftInts)
; ExternalInt0 (=> NKReset)
; ExternalInt1 (=> NKReset)
; ExternalInt2 (=> NKReset)
######################################################################## ########################################################################
_align 6 _align 6
ExternalInt0 ExternalInt0
mfsprg r1, 0 ; Init regs and increment ctr mfsprg r1, 0 ; Init regs and increment ctr
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r2, KDP.r2(r1) stw r2, KDP.r2(r1)
lwz r2, KDP.NKInfo.ExternalIntCount(r1) lwz r2, KDP.NKInfo.ExternalIntCount(r1)
stw r3, KDP.r3(r1) stw r3, KDP.r3(r1)
addi r2, r2, 1 addi r2, r2, 1
stw r2, KDP.NKInfo.ExternalIntCount(r1) stw r2, KDP.NKInfo.ExternalIntCount(r1)
mfmsr r2 ; Save a self-ptr to FF880000... why? mfmsr r2 ; Save a self-ptr to FF880000... why?
lis r3, 0xFF88 lis r3, 0xFF88
_set r0, r2, bitMsrDR _set r0, r2, bitMsrDR
stw r4, KDP.r4(r1) stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1) stw r5, KDP.r5(r1)
mfsrr0 r4 mfsrr0 r4
mfsrr1 r5 mfsrr1 r5
mtmsr r0 mtmsr r0
stw r3, 0(r3) stw r3, 0(r3)
mtmsr r2 mtmsr r2
mtsrr0 r4 mtsrr0 r4
mtsrr1 r5 mtsrr1 r5
lwz r4, KDP.r4(r1) lwz r4, KDP.r4(r1)
lwz r5, KDP.r5(r1) lwz r5, KDP.r5(r1)
lwz r2, KDP.DebugIntPtr(r1) ; Query the shared mem (debug?) for int num lwz r2, KDP.DebugIntPtr(r1) ; Query the shared mem (debug?) for int num
mfcr r0 mfcr r0
lha r2, 0(r2) lha r2, 0(r2)
lwz r3, KDP.EmuIntLevelPtr(r1) lwz r3, KDP.EmuIntLevelPtr(r1)
rlwinm. r2, r2, 0, 0x80000007 rlwinm. r2, r2, 0, 0x80000007
ori r2, r2, 0x8000 ori r2, r2, 0x8000
sth r2, 0(r3) sth r2, 0(r3)
mfsprg r2, 2 mfsprg r2, 2
lwz r3, KDP.r3(r1) lwz r3, KDP.r3(r1)
mtlr r2 mtlr r2
beq @clear ; 0 -> clear interrupt beq @clear ; 0 -> clear interrupt
bgt @return ; negative -> no interrupt flag bgt @return ; negative -> no interrupt flag
; positive -> post interrupt ; positive -> post interrupt
lwz r2, KDP.PostIntMaskInit(r1) ; Post an interrupt via Cond Reg lwz r2, KDP.PostIntMaskInit(r1) ; Post an interrupt via Cond Reg
or r0, r0, r2 or r0, r0, r2
@return @return
mtcr r0 ; Set CR and return mtcr r0 ; Set CR and return
lwz r0, KDP.r0(r1) lwz r0, KDP.r0(r1)
lwz r2, KDP.r2(r1) lwz r2, KDP.r2(r1)
mfsprg r1, 1 mfsprg r1, 1
rfi rfi
@clear @clear
lwz r2, KDP.ClearIntMaskInit(r1) ; Clear an interrupt via Cond Reg lwz r2, KDP.ClearIntMaskInit(r1) ; Clear an interrupt via Cond Reg
and r0, r0, r2 and r0, r0, r2
b @return b @return
######################################################################## ########################################################################
_align 6 _align 6
IntLookupTable IntLookupTable
dc.b 0, 1, 2, 2, 4, 4, 4, 4 dc.b 0, 1, 2, 2, 4, 4, 4, 4
dc.b 3, 3, 3, 3, 4, 4, 4, 4 dc.b 3, 3, 3, 3, 4, 4, 4, 4
dc.b 4, 4, 4, 4, 4, 4, 4, 4 dc.b 4, 4, 4, 4, 4, 4, 4, 4
dc.b 4, 4, 4, 4, 4, 4, 4, 4 dc.b 4, 4, 4, 4, 4, 4, 4, 4
dc.b 7, 7, 7, 7, 7, 7, 7, 7 dc.b 7, 7, 7, 7, 7, 7, 7, 7
dc.b 7, 7, 7, 7, 7, 7, 7, 7 dc.b 7, 7, 7, 7, 7, 7, 7, 7
dc.b 7, 7, 7, 7, 7, 7, 7, 7 dc.b 7, 7, 7, 7, 7, 7, 7, 7
dc.b 7, 7, 7, 7, 7, 7, 7, 7 dc.b 7, 7, 7, 7, 7, 7, 7, 7
_align 6 _align 6
ExternalInt1 ExternalInt1
mfsprg r1, 0 ; Init regs and increment ctr mfsprg r1, 0 ; Init regs and increment ctr
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r2, KDP.r2(r1) stw r2, KDP.r2(r1)
lwz r2, KDP.NKInfo.ExternalIntCount(r1) lwz r2, KDP.NKInfo.ExternalIntCount(r1)
stw r3, KDP.r3(r1) stw r3, KDP.r3(r1)
addi r2, r2, 1 addi r2, r2, 1
stw r2, KDP.NKInfo.ExternalIntCount(r1) stw r2, KDP.NKInfo.ExternalIntCount(r1)
lis r2, 0x50F3 ; Query OpenPIC at 50F2A000 lis r2, 0x50F3 ; Query OpenPIC at 50F2A000
mfmsr r3 mfmsr r3
_set r0, r3, bitMsrDR _set r0, r3, bitMsrDR
stw r4, KDP.r4(r1) stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1) stw r5, KDP.r5(r1)
mfsrr0 r4 mfsrr0 r4
mfsrr1 r5 mfsrr1 r5
mtmsr r0 mtmsr r0
li r0, 0xC0 li r0, 0xC0
stb r0, -0x6000(r2) stb r0, -0x6000(r2)
eieio eieio
lbz r0, -0x6000(r2) lbz r0, -0x6000(r2)
mtmsr r3 mtmsr r3
mtsrr0 r4 mtsrr0 r4
mtsrr1 r5 mtsrr1 r5
lwz r4, KDP.r4(r1) lwz r4, KDP.r4(r1)
lwz r5, KDP.r5(r1) lwz r5, KDP.r5(r1)
lwz r3, KDP.CodeBase(r1) ; Loop that number up in the table lwz r3, KDP.CodeBase(r1) ; Loop that number up in the table
rlwimi r3, r0, 0, 0x0000003F rlwimi r3, r0, 0, 0x0000003F
lbz r2, IntLookupTable-CodeBase(r3) lbz r2, IntLookupTable-CodeBase(r3)
mfcr r0 mfcr r0
lwz r3, KDP.EmuIntLevelPtr(r1) lwz r3, KDP.EmuIntLevelPtr(r1)
clrlwi. r2, r2, 29 clrlwi. r2, r2, 29
sth r2, 0(r3) sth r2, 0(r3)
mfsprg r2, 2 mfsprg r2, 2
lwz r3, KDP.r3(r1) lwz r3, KDP.r3(r1)
mtlr r2 mtlr r2
beq @clear ; 0 -> clear interrupt beq @clear ; 0 -> clear interrupt
; nonzero -> post interrupt ; nonzero -> post interrupt
lwz r2, KDP.PostIntMaskInit(r1) ; Post an interrupt via Cond Reg lwz r2, KDP.PostIntMaskInit(r1) ; Post an interrupt via Cond Reg
or r0, r0, r2 or r0, r0, r2
@return @return
mtcr r0 ; Set CR and return mtcr r0 ; Set CR and return
lwz r0, KDP.r0(r1) lwz r0, KDP.r0(r1)
lwz r2, KDP.r2(r1) lwz r2, KDP.r2(r1)
mfsprg r1, 1 mfsprg r1, 1
rfi rfi
@clear @clear
lwz r2, KDP.ClearIntMaskInit(r1) ; Clear an interrupt via Cond Reg lwz r2, KDP.ClearIntMaskInit(r1) ; Clear an interrupt via Cond Reg
and r0, r0, r2 and r0, r0, r2
b @return b @return
######################################################################## ########################################################################
_align 6 _align 6
ExternalInt2 ExternalInt2
mfsprg r1, 0 ; Init regs and increment ctr mfsprg r1, 0 ; Init regs and increment ctr
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r2, KDP.r2(r1) stw r2, KDP.r2(r1)
lwz r2, KDP.NKInfo.ExternalIntCount(r1) lwz r2, KDP.NKInfo.ExternalIntCount(r1)
stw r3, KDP.r3(r1) stw r3, KDP.r3(r1)
addi r2, r2, 1 addi r2, r2, 1
stw r2, KDP.NKInfo.ExternalIntCount(r1) stw r2, KDP.NKInfo.ExternalIntCount(r1)
lis r2, 0xF300 ; Query OpenPIC at F3000028/C lis r2, 0xF300 ; Query OpenPIC at F3000028/C
mfmsr r0 mfmsr r0
_set r3, r0, bitMsrDR _set r3, r0, bitMsrDR
stw r4, KDP.r4(r1) stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1) stw r5, KDP.r5(r1)
mfsrr0 r4 mfsrr0 r4
mfsrr1 r5 mfsrr1 r5
mtmsr r3 mtmsr r3
lis r3, 0x8000 lis r3, 0x8000
stw r3, 0x28(r2) stw r3, 0x28(r2)
eieio eieio
lwz r3, 0x2C(r2) lwz r3, 0x2C(r2)
mtmsr r0 mtmsr r0
mtsrr0 r4 mtsrr0 r4
mtsrr1 r5 mtsrr1 r5
lwz r4, KDP.r4(r1) lwz r4, KDP.r4(r1)
lwz r5, KDP.r5(r1) lwz r5, KDP.r5(r1)
mfcr r0 mfcr r0
; Interpret OpenPic result: ; Interpret OpenPic result:
rlwinm. r2, r3, 0, 11, 11 ; bit 11 -> 7 rlwinm. r2, r3, 0, 11, 11 ; bit 11 -> 7
li r2, 7 li r2, 7
bne @gotnum bne @gotnum
rlwinm r2, r3, 0, 15, 16 ; bit 15-16/21/31 -> 4 rlwinm r2, r3, 0, 15, 16 ; bit 15-16/21/31 -> 4
rlwimi. r2, r3, 0, 21, 31 rlwimi. r2, r3, 0, 21, 31
li r2, 4 li r2, 4
bne @gotnum bne @gotnum
rlwinm. r2, r3, 0, 18, 18 ; bit 18 -> 3 rlwinm. r2, r3, 0, 18, 18 ; bit 18 -> 3
li r2, 3 li r2, 3
bne @gotnum bne @gotnum
andis. r2, r3, 0x7FEA ; bit 1-10/12/14/19-20 -> 2 andis. r2, r3, 0x7FEA ; bit 1-10/12/14/19-20 -> 2
rlwimi. r2, r3, 0, 19, 20 rlwimi. r2, r3, 0, 19, 20
li r2, 2 li r2, 2
bne @gotnum bne @gotnum
extrwi. r2, r3, 1, 13 ; bit 13 -> 1 extrwi. r2, r3, 1, 13 ; bit 13 -> 1
; else -> 0 ; else -> 0
@gotnum @gotnum
lwz r3, KDP.EmuIntLevelPtr(r1) lwz r3, KDP.EmuIntLevelPtr(r1)
sth r2, 0(r3) sth r2, 0(r3)
mfsprg r2, 2 mfsprg r2, 2
lwz r3, KDP.r3(r1) lwz r3, KDP.r3(r1)
mtlr r2 mtlr r2
beq @clear ; 0 -> clear interrupt beq @clear ; 0 -> clear interrupt
; nonzero -> post interrupt ; nonzero -> post interrupt
lwz r2, KDP.PostIntMaskInit(r1) ; Post an interrupt via Cond Reg lwz r2, KDP.PostIntMaskInit(r1) ; Post an interrupt via Cond Reg
or r0, r0, r2 or r0, r0, r2
@return @return
mtcr r0 ; Set CR and return mtcr r0 ; Set CR and return
lwz r0, KDP.r0(r1) lwz r0, KDP.r0(r1)
lwz r2, KDP.r2(r1) lwz r2, KDP.r2(r1)
mfsprg r1, 1 mfsprg r1, 1
rfi rfi
@clear @clear
lwz r2, KDP.ClearIntMaskInit(r1) ; Clear an interrupt via Cond Reg lwz r2, KDP.ClearIntMaskInit(r1) ; Clear an interrupt via Cond Reg
and r0, r0, r2 and r0, r0, r2
b @return b @return
######################################################################## ########################################################################
; Increment the Sys/Alt CPU clocks, and the Dec-int counter ; Increment the Sys/Alt CPU clocks, and the Dec-int counter
_align 6 _align 6
DecrementerIntSys DecrementerIntSys
mfsprg r1, 0 mfsprg r1, 0
stmw r2, KDP.r2(r1) stmw r2, KDP.r2(r1)
mfdec r31 mfdec r31
lwz r30, KDP.OtherContextDEC(r1) lwz r30, KDP.OtherContextDEC(r1)
DecCommon ; DEC for Alternate=r30, System=r31 DecCommon ; DEC for Alternate=r30, System=r31
mfxer r29 ; we will do carries mfxer r29 ; we will do carries
lwz r28, KDP.ProcInfo.DecClockRateHz(r1) lwz r28, KDP.ProcInfo.DecClockRateHz(r1)
stw r28, KDP.OtherContextDEC(r1) stw r28, KDP.OtherContextDEC(r1)
mtdec r28 ; reset Sys and Alt decrementers mtdec r28 ; reset Sys and Alt decrementers
subf r31, r31, r28 ; System ticks actually elapsed subf r31, r31, r28 ; System ticks actually elapsed
subf r30, r30, r28 ; Alternate ticks actually elapsed subf r30, r30, r28 ; Alternate ticks actually elapsed
lwz r28, KDP.NKInfo.SysContextCpuTime+4(r1) lwz r28, KDP.NKInfo.SysContextCpuTime+4(r1)
lwz r27, KDP.NKInfo.SysContextCpuTime(r1) lwz r27, KDP.NKInfo.SysContextCpuTime(r1)
addc r28, r28, r31 addc r28, r28, r31
addze r27, r27 addze r27, r27
stw r28, KDP.NKInfo.SysContextCpuTime+4(r1) stw r28, KDP.NKInfo.SysContextCpuTime+4(r1)
stw r27, KDP.NKInfo.SysContextCpuTime(r1) stw r27, KDP.NKInfo.SysContextCpuTime(r1)
lwz r28, KDP.NKInfo.AltContextCpuTime+4(r1) lwz r28, KDP.NKInfo.AltContextCpuTime+4(r1)
lwz r27, KDP.NKInfo.AltContextCpuTime(r1) lwz r27, KDP.NKInfo.AltContextCpuTime(r1)
addc r28, r28, r30 addc r28, r28, r30
addze r27, r27 addze r27, r27
stw r28, KDP.NKInfo.AltContextCpuTime+4(r1) stw r28, KDP.NKInfo.AltContextCpuTime+4(r1)
stw r27, KDP.NKInfo.AltContextCpuTime(r1) stw r27, KDP.NKInfo.AltContextCpuTime(r1)
mtxer r29 mtxer r29
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
mfsprg r31, 1 mfsprg r31, 1
stw r31, KDP.r1(r1) stw r31, KDP.r1(r1)
lwz r31, KDP.NKInfo.DecrementerIntCount(r1) lwz r31, KDP.NKInfo.DecrementerIntCount(r1)
addi r31, r31, 1 addi r31, r31, 1
stw r31, KDP.NKInfo.DecrementerIntCount(r1) stw r31, KDP.NKInfo.DecrementerIntCount(r1)
lmw r27, KDP.r27(r1) lmw r27, KDP.r27(r1)
mfsprg r1, 2 mfsprg r1, 2
mtlr r1 mtlr r1
mfsprg r1, 1 mfsprg r1, 1
rfi rfi
DecrementerIntAlt DecrementerIntAlt
mfsprg r1, 0 mfsprg r1, 0
stmw r2, KDP.r2(r1) stmw r2, KDP.r2(r1)
lwz r31, KDP.OtherContextDEC(r1) lwz r31, KDP.OtherContextDEC(r1)
mfdec r30 mfdec r30
b DecCommon b DecCommon
######################################################################## ########################################################################
_align 6 _align 6
DataStorageInt DataStorageInt
mfsprg r1, 0 mfsprg r1, 0
stmw r2, KDP.r2(r1) stmw r2, KDP.r2(r1)
mfsprg r11, 1 mfsprg r11, 1
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r11, KDP.r1(r1) stw r11, KDP.r1(r1)
mfsrr0 r10 mfsrr0 r10
mfsrr1 r11 mfsrr1 r11
mfsprg r12, 2 mfsprg r12, 2
mfcr r13 mfcr r13
mfmsr r14 mfmsr r14
_set r15, r14, bitMsrDR _set r15, r14, bitMsrDR
mtmsr r15 mtmsr r15
lwz r27, 0(r10) ; r27 = INSTRUCTION lwz r27, 0(r10) ; r27 = INSTRUCTION
mtmsr r14 mtmsr r14
EmulateDataAccess EmulateDataAccess
rlwinm. r18, r27, 18, 25, 29 ; r16 = 4 * rA (r0 wired to 0) rlwinm. r18, r27, 18, 25, 29 ; r16 = 4 * rA (r0 wired to 0)
lwz r25, KDP.MRBase(r1) lwz r25, KDP.MRBase(r1)
li r21, 0 li r21, 0
beq @r0 beq @r0
lwzx r18, r1, r18 ; r16 = contents of rA lwzx r18, r1, r18 ; r16 = contents of rA
@r0 @r0
andis. r26, r27, 0xec00 ; intended to extract the major opcode? seems wrong though! andis. r26, r27, 0xec00 ; intended to extract the major opcode? seems wrong though!
lwz r16, KDP.Flags(r1) lwz r16, KDP.Flags(r1)
mfsprg r24, 3 mfsprg r24, 3
rlwinm r17, r27, 0, 6, 15 ; r17 = rS/D and rA fields rlwinm r17, r27, 0, 6, 15 ; r17 = rS/D and rA fields
rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
bge @xform bge @xform
;dform ;dform
rlwimi r25, r27, 7, 26, 29 rlwimi r25, r27, 7, 26, 29
rlwimi r25, r27, 12, 25, 25 rlwimi r25, r27, 12, 25, 25
lwz r26, MROptabD - MRBase(r25) ; table of 4b elements, index = major opcode bits 51234 (this is the last quarter of MROptabX) lwz r26, MROptabD-MRBase(r25) ; table of 4b elements, index = major opcode bits 51234 (this is the last quarter of MROptabX)
extsh r23, r27 ; r23 = register offset field, sign-extended extsh r23, r27 ; r23 = register offset field, sign-extended
rlwimi r25, r26, 26, 22, 29 rlwimi r25, r26, 26, 22, 29
mtlr r25 ; dest = r25 = first of two function ptrs in table entry mtlr r25 ; dest = r25 = first of two function ptrs in table entry
mtcr r26 ; using the flags in the arbitrary upper 16 bits of the table entry? mtcr r26 ; using the flags in the arbitrary upper 16 bits of the table entry?
add r18, r18, r23 ; r18 = effective address attempted by instruction add r18, r18, r23 ; r18 = effective address attempted by instruction
rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl) rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl)
blr blr
@xform @xform
rlwimi r25, r27, 27, 26, 29 rlwimi r25, r27, 27, 26, 29
rlwimi r25, r27, 0, 25, 25 rlwimi r25, r27, 0, 25, 25
rlwimi r25, r27, 6, 23, 24 rlwimi r25, r27, 6, 23, 24
lwz r26, MROptabX - MRBase(r25) ; table of 4b elements, index = minor (x-form) opcode bits 8940123 lwz r26, MROptabX-MRBase(r25) ; table of 4b elements, index = minor (x-form) opcode bits 8940123
rlwinm r23, r27, 23, 25, 29 ; r23 = 4 * rB rlwinm r23, r27, 23, 25, 29 ; r23 = 4 * rB
rlwimi r25, r26, 26, 22, 29 rlwimi r25, r26, 26, 22, 29
mtlr r25 ; dest = r25 = first of two function ptrs in table entry mtlr r25 ; dest = r25 = first of two function ptrs in table entry
mtcr r26 mtcr r26
lwzx r23, r1, r23 ; get rB from saved registers lwzx r23, r1, r23 ; get rB from saved registers
rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl) rlwimi r17, r26, 6, 26, 5 ; r17 = pretend X-form inst with: maj opcode (from tbl), rS/D and RA (from inst), min opcode (from tbl)
add r18, r18, r23 ; r18 = effective address attempted by instruction add r18, r18, r23 ; r18 = effective address attempted by instruction
bclr BO_IF_NOT, mrOpflag2 bclr BO_IF_NOT, mrOpflag2
neg r23, r23 neg r23, r23
add r18, r18, r23 add r18, r18, r23
blr blr
######################################################################## ########################################################################
_align 6 _align 6
AlignmentInt AlignmentInt
mfsprg r1, 0 mfsprg r1, 0
stmw r2, KDP.r2(r1) stmw r2, KDP.r2(r1)
lwz r11, KDP.NKInfo.MisalignmentCount(r1) lwz r11, KDP.NKInfo.MisalignmentCount(r1)
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NKInfo.MisalignmentCount(r1) stw r11, KDP.NKInfo.MisalignmentCount(r1)
mfsprg r11, 1 mfsprg r11, 1
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r11, KDP.r1(r1) stw r11, KDP.r1(r1)
mfsrr0 r10 mfsrr0 r10
mfsrr1 r11 mfsrr1 r11
mfsprg r12, 2 mfsprg r12, 2
mfcr r13 mfcr r13
mfsprg r24, 3 mfsprg r24, 3
mfdsisr r27 mfdsisr r27
mfdar r18 mfdar r18
extrwi. r21, r27, 2, 15 ; evaluate hi two bits of XO (or 0 for d-form?) extrwi. r21, r27, 2, 15 ; evaluate hi two bits of XO (or 0 for d-form?)
lwz r25, KDP.MRBase(r1) lwz r25, KDP.MRBase(r1)
rlwinm r17, r27, 16, 0x03FF0000 rlwinm r17, r27, 16, 0x03FF0000
lwz r16, KDP.Flags(r1) lwz r16, KDP.Flags(r1)
rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP rlwimi r25, r27, 24, 23, 29 ; add constant fields from dsisr (*4) to FDP
rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE rlwimi r16, r16, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
bne @xform bne @xform
;dform ;dform
lwz r26, MROptabD - MRBase(r25) ; use upper quarter of table lwz r26, MROptabD-MRBase(r25) ; use upper quarter of table
mfmsr r14 mfmsr r14
rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP rlwimi r25, r26, 26, 22, 29 ; third byte of lookup value is a /4 code offset in FDP
mtlr r25 ; so get ready to go there mtlr r25 ; so get ready to go there
_set r15, r14, bitMsrDR _set r15, r14, bitMsrDR
mtcr r26 mtcr r26
rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values rlwimi r17, r26, 6, 26, 5 ; wrap some shite around the register values
blr blr
@xform @xform
lwz r26, MROptabX - MRBase(r25) lwz r26, MROptabX-MRBase(r25)
mfmsr r14 mfmsr r14
rlwimi r25, r26, 26, 22, 29 rlwimi r25, r26, 26, 22, 29
mtlr r25 mtlr r25
_set r15, r14, bitMsrDR _set r15, r14, bitMsrDR
mtcr r26 mtcr r26
rlwimi r17, r26, 6, 26, 5 rlwimi r17, r26, 6, 26, 5
bclr BO_IF_NOT, mrOpflag1 bclr BO_IF_NOT, mrOpflag1
mtmsr r15 mtmsr r15
lwz r27, 0(r10) lwz r27, 0(r10)
mtmsr r14 mtmsr r14
blr blr

608
NanoKernel/NKInit.s
View File

@ -1,433 +1,433 @@
; Registers passed in by HardwareInit ; Registers passed in by HardwareInit
rCI set r3 ; NKConfigurationInfo rCI set r3 ; NKConfigurationInfo
rPI set r4 ; NKProcessorInfo rPI set r4 ; NKProcessorInfo
rSI set r5 ; NKSystemInfo rSI set r5 ; NKSystemInfo
rDI set r6 ; NKDiagInfo rDI set r6 ; NKDiagInfo
; Other registers we use ; Other registers we use
rED set r8 ; Emulator Data Page rED set r8 ; Emulator Data Page
######################################################################## ########################################################################
li r0, 0 ; Zero lots of fields li r0, 0 ; Zero lots of fields
######################################################################## ########################################################################
ClearSPRs ClearSPRs
mtsr 0, r0 mtsr 0, r0
mtsr 1, r0 mtsr 1, r0
mtsr 2, r0 mtsr 2, r0
mtsr 3, r0 mtsr 3, r0
mtsr 4, r0 mtsr 4, r0
mtsr 5, r0 mtsr 5, r0
mtsr 6, r0 mtsr 6, r0
mtsr 7, r0 mtsr 7, r0
mtsr 8, r0 mtsr 8, r0
mtsr 9, r0 mtsr 9, r0
mtsr 10, r0 mtsr 10, r0
mtsr 11, r0 mtsr 11, r0
mtsr 12, r0 mtsr 12, r0
mtsr 13, r0 mtsr 13, r0
mtsr 14, r0 mtsr 14, r0
mtsr 15, r0 mtsr 15, r0
mtspr rtcl, r0 mtspr rtcl, r0
mtspr rtcu, r0 mtspr rtcu, r0
######################################################################## ########################################################################
AlignFirstBankToPAR AlignFirstBankToPAR
lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(rCI) ; Scoop the ram before this ptr out of banks lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(rCI) ; Scoop the ram before this ptr out of banks
; so that PAR starts at PA_RelocatedLowMemInit ; so that PAR starts at PA_RelocatedLowMemInit
lwz r11, NKSystemInfo.Bank0Start(rSI) lwz r11, NKSystemInfo.Bank0Start(rSI)
add r11, r11, r12 add r11, r11, r12
stw r11, NKSystemInfo.Bank0Start(rSI) stw r11, NKSystemInfo.Bank0Start(rSI)
lwz r11, NKSystemInfo.Bank0Size(rSI) lwz r11, NKSystemInfo.Bank0Size(rSI)
subf r11, r12, r11 subf r11, r12, r11
stw r11, NKSystemInfo.Bank0Size(rSI) stw r11, NKSystemInfo.Bank0Size(rSI)
lwz r11, NKSystemInfo.PhysicalMemorySize(rSI) lwz r11, NKSystemInfo.PhysicalMemorySize(rSI)
subf r11, r12, r11 subf r11, r12, r11
stw r11, NKSystemInfo.PhysicalMemorySize(rSI) stw r11, NKSystemInfo.PhysicalMemorySize(rSI)
######################################################################## ########################################################################
InitKernelMemory InitKernelMemory
lwz r15, NKSystemInfo.PhysicalMemorySize(rSI) ; Size the HTAB for 2 entries per page lwz r15, NKSystemInfo.PhysicalMemorySize(rSI) ; Size the HTAB for 2 entries per page
subi r15, r15, 1 subi r15, r15, 1
cntlzw r12, r15 cntlzw r12, r15
lis r14, 0x00ff ; r14 = size-1 lis r14, 0x00ff ; r14 = size-1
srw r14, r14, r12 srw r14, r14, r12
ori r14, r14, 0xffff ; Obey architecture min and max size ori r14, r14, 0xffff ; Obey architecture min and max size
clrlwi r14, r14, 9 clrlwi r14, r14, 9
addis r15, r15, 0x40 ; Size the PageList addis r15, r15, 0x40 ; Size the PageList
rlwinm r15, r15, 32-10, 10, 19 ; (4b entry per page, total rounded to nearest page) rlwinm r15, r15, 32-10, 10, 19 ; (4b entry per page, total rounded to nearest page)
add r15, r15, r14 ; Total = PageList + KDP/EDP (2 pages) + HTAB add r15, r15, r14 ; Total = PageList + KDP/EDP (2 pages) + HTAB
addi r15, r15, 0x2001 addi r15, r15, 0x2001
addi r10, rSI, NKSystemInfo.EndOfBanks ; Choose which bank of physical RAM to use addi r10, rSI, NKSystemInfo.EndOfBanks ; Choose which bank of physical RAM to use
@nextbank ; (no need to edit the bank table) @nextbank ; (no need to edit the bank table)
lwz r11, -4(r10) lwz r11, -4(r10)
lwzu r12, -8(r10) lwzu r12, -8(r10)
add r11, r12, r11 ; r12 = bank start, r11 = bank end add r11, r12, r11 ; r12 = bank start, r11 = bank end
andc r13, r11, r14 ; Check if HTAB fits in this bank, andc r13, r11, r14 ; Check if HTAB fits in this bank,
subf r13, r15, r13 ; while remaining aligned to its own size subf r13, r15, r13 ; while remaining aligned to its own size
cmplw r13, r12 cmplw r13, r12
blt @nextbank blt @nextbank
cmplw r13, r11 cmplw r13, r11
bgt @nextbank bgt @nextbank
add r12, r13, r15 ; base of address range we will use add r12, r13, r15 ; base of address range we will use
subf r12, r14, r12 ; r12 = ptr to HTAB (inside address range) subf r12, r14, r12 ; r12 = ptr to HTAB (inside address range)
inslwi r12, r14, 16, 16 ; SDR1 = HTABORG || HTABMASK (16b each) inslwi r12, r14, 16, 16 ; SDR1 = HTABORG || HTABMASK (16b each)
mtspr sdr1, r12 mtspr sdr1, r12
clrrwi r11, r12, 16 ; Init KDP, 2 pages below HTAB clrrwi r11, r12, 16 ; Init KDP, 2 pages below HTAB
subi r1, r11, 0x2000 subi r1, r11, 0x2000
lwz r11, KDP.CrashSDR1(r1) lwz r11, KDP.CrashSDR1(r1)
mtsprg 0, r1 mtsprg 0, r1
cmpw r12, r11 cmpw r12, r11
lis r11, 0x7fff lis r11, 0x7fff
bne @did_not_panic bne @did_not_panic
subf r11, r13, r1 subf r11, r13, r1
addi r11, r11, KDP.CrashTop addi r11, r11, KDP.CrashTop
@did_not_panic @did_not_panic
subf r12, r14, r15 ; Erase all of kernel globals, except crash data subf r12, r14, r15 ; Erase all of kernel globals, except crash data
subi r12, r12, 1 subi r12, r12, 1
@eraseloop @eraseloop
subic. r12, r12, 4 subic. r12, r12, 4
subf r10, r11, r12 subf r10, r11, r12
cmplwi cr7, r10, KDP.CrashBtm - KDP.CrashTop cmplwi cr7, r10, KDP.CrashBtm - KDP.CrashTop
ble cr7, @skipwrite ble cr7, @skipwrite
stwx r0, r13, r12 stwx r0, r13, r12
@skipwrite @skipwrite
bne @eraseloop bne @eraseloop
######################################################################## ########################################################################
CopyInfoRecords CopyInfoRecords
addi r11, r1, KDP.ProcInfo addi r11, r1, KDP.ProcInfo
li r10, NKProcessorInfo.Size li r10, NKProcessorInfo.Size
@loop_procinfo @loop_procinfo
subic. r10, r10, 4 subic. r10, r10, 4
lwzx r12, rPI, r10 lwzx r12, rPI, r10
stwx r12, r11, r10 stwx r12, r11, r10
bgt @loop_procinfo bgt @loop_procinfo
addi r11, r1, KDP.SysInfo addi r11, r1, KDP.SysInfo
li r10, NKSystemInfo.Size li r10, NKSystemInfo.Size
@loop_sysinfo @loop_sysinfo
subic. r10, r10, 4 subic. r10, r10, 4
lwzx r12, rSI, r10 lwzx r12, rSI, r10
stwx r12, r11, r10 stwx r12, r11, r10
bgt @loop_sysinfo bgt @loop_sysinfo
addi r11, r1, KDP.DiagInfo addi r11, r1, KDP.DiagInfo
li r10, NKDiagInfo.Size li r10, NKDiagInfo.Size
@loop_diaginfo @loop_diaginfo
subic. r10, r10, 4 subic. r10, r10, 4
lwzx r12, rDI, r10 lwzx r12, rDI, r10
stwx r12, r11, r10 stwx r12, r11, r10
bgt @loop_diaginfo bgt @loop_diaginfo
######################################################################## ########################################################################
InitKernelGlobals InitKernelGlobals
stw rCI, KDP.ConfigInfoPtr(r1) stw rCI, KDP.ConfigInfoPtr(r1)
addi r12, r14, 1 addi r12, r14, 1
stw r12, KDP.SysInfo.HashTableSize(r1) stw r12, KDP.SysInfo.HashTableSize(r1)
addi rED, r1, 0x1000 addi rED, r1, 0x1000
stw rED, KDP.EDPPtr(r1) stw rED, KDP.EDPPtr(r1)
stw r13, KDP.KernelMemoryBase(r1) stw r13, KDP.KernelMemoryBase(r1)
add r12, r13, r15 add r12, r13, r15
stw r12, KDP.KernelMemoryEnd(r1) stw r12, KDP.KernelMemoryEnd(r1)
lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(rCI) lwz r12, NKConfigurationInfo.PA_RelocatedLowMemInit(rCI)
stw r12, KDP.LowMemPtr(r1) stw r12, KDP.LowMemPtr(r1)
lwz r12, NKConfigurationInfo.SharedMemoryAddr(rCI) lwz r12, NKConfigurationInfo.SharedMemoryAddr(rCI)
stw r12, KDP.SharedMemoryAddr(r1) stw r12, KDP.SharedMemoryAddr(r1)
lwz r12, NKConfigurationInfo.LA_EmulatorCode(rCI) lwz r12, NKConfigurationInfo.LA_EmulatorCode(rCI)
lwz r11, NKConfigurationInfo.KernelTrapTableOffset(rCI) lwz r11, NKConfigurationInfo.KernelTrapTableOffset(rCI)
add r12, r12, r11 add r12, r12, r11
stw r12, KDP.EmuKCallTblPtrLogical(r1) stw r12, KDP.EmuKCallTblPtrLogical(r1)
bl * + 4 bl * + 4
mflr r12 mflr r12
addi r12, r12, 4 - * addi r12, r12, 4 - *
stw r12, KDP.CodeBase(r1) stw r12, KDP.CodeBase(r1)
_kaddr r12, r12, MRBase _kaddr r12, r12, MRBase
stw r12, KDP.MRBase(r1) stw r12, KDP.MRBase(r1)
lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI) lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI)
lwz r11, NKConfigurationInfo.ECBOffset(rCI) lwz r11, NKConfigurationInfo.ECBOffset(rCI)
add r12, r12, r11 add r12, r12, r11
stw r12, KDP.ECBPtrLogical(r1) stw r12, KDP.ECBPtrLogical(r1)
add r12, rED, r11 add r12, rED, r11
stw r12, KDP.ECBPtr(r1) stw r12, KDP.ECBPtr(r1)
stw r12, KDP.ContextPtr(r1) stw r12, KDP.ContextPtr(r1)
lwz r12, NKConfigurationInfo.TestIntMaskInit(rCI) lwz r12, NKConfigurationInfo.TestIntMaskInit(rCI)
stw r12, KDP.TestIntMaskInit(r1) stw r12, KDP.TestIntMaskInit(r1)
lwz r12, NKConfigurationInfo.ClearIntMaskInit(rCI) lwz r12, NKConfigurationInfo.ClearIntMaskInit(rCI)
stw r12, KDP.ClearIntMaskInit(r1) stw r12, KDP.ClearIntMaskInit(r1)
lwz r12, NKConfigurationInfo.PostIntMaskInit(rCI) lwz r12, NKConfigurationInfo.PostIntMaskInit(rCI)
stw r12, KDP.PostIntMaskInit(r1) stw r12, KDP.PostIntMaskInit(r1)
lwz r12, NKConfigurationInfo.IplValueOffset(rCI) lwz r12, NKConfigurationInfo.IplValueOffset(rCI)
add r12, rED, r12 add r12, rED, r12
stw r12, KDP.EmuIntLevelPtr(r1) stw r12, KDP.EmuIntLevelPtr(r1)
lwz r12, NKConfigurationInfo.SharedMemoryAddr(rCI) lwz r12, NKConfigurationInfo.SharedMemoryAddr(rCI)
addi r12, r12, 0x7c addi r12, r12, 0x7c
stw r12, KDP.DebugIntPtr(r1) stw r12, KDP.DebugIntPtr(r1)
lwz r12, NKConfigurationInfo.PageAttributeInit(rCI) lwz r12, NKConfigurationInfo.PageAttributeInit(rCI)
stw r12, KDP.PageAttributeInit(r1) stw r12, KDP.PageAttributeInit(r1)
addi r13, r1, KDP.PageMap addi r13, r1, KDP.PageMap
lwz r12, NKConfigurationInfo.PageMapInitSize(rCI) lwz r12, NKConfigurationInfo.PageMapInitSize(rCI)
stw r13, KDP.PageMapStartPtr(r1) stw r13, KDP.PageMapStartPtr(r1)
add r13, r13, r12 add r13, r13, r12
stw r13, KDP.PageMapEndPtr(r1) stw r13, KDP.PageMapEndPtr(r1)
######################################################################## ########################################################################
InitInfoRecords InitInfoRecords
lwz r11, NKConfigurationInfo.LA_InfoRecord(rCI) lwz r11, NKConfigurationInfo.LA_InfoRecord(rCI)
addi r12, r11, 0xFC0 addi r12, r11, 0xFC0
stw r12, 0xFC0(r1) stw r12, 0xFC0(r1)
stw r0, 0xFC4(r1) stw r0, 0xFC4(r1)
addi r12, r11, 0xFC8 addi r12, r11, 0xFC8
stw r12, 0xFC8(r1) stw r12, 0xFC8(r1)
stw r0, 0xFCC(r1) stw r0, 0xFCC(r1)
addi r12, r11, 0xFD0 addi r12, r11, 0xFD0
stw r12, 0xFD0(r1) stw r12, 0xFD0(r1)
stw r0, 0xFD4(r1) stw r0, 0xFD4(r1)
addi r12, r11, KDP.ProcInfo addi r12, r11, KDP.ProcInfo
stw r12, NKProcessorInfoPtr & 0xFFF(r1) stw r12, NKProcessorInfoPtr & 0xFFF(r1)
li r12, 0x100 li r12, 0x100
sth r12, NKProcessorInfoVer & 0xFFF(r1) sth r12, NKProcessorInfoVer & 0xFFF(r1)
li r12, NKProcessorInfo.Size li r12, NKProcessorInfo.Size
sth r12, NKProcessorInfoLen & 0xFFF(r1) sth r12, NKProcessorInfoLen & 0xFFF(r1)
addi r12, r11, KDP.NKInfo addi r12, r11, KDP.NKInfo
stw r12, NKNanoKernelInfoPtr & 0xFFF(r1) stw r12, NKNanoKernelInfoPtr & 0xFFF(r1)
li r12, kNanoKernelVersion li r12, kNanoKernelVersion
sth r12, NKNanoKernelInfoVer & 0xFFF(r1) sth r12, NKNanoKernelInfoVer & 0xFFF(r1)
li r12, NKNanoKernelInfo.Size li r12, NKNanoKernelInfo.Size
sth r12, NKNanoKernelInfoLen & 0xFFF(r1) sth r12, NKNanoKernelInfoLen & 0xFFF(r1)
addi r12, r11, KDP.DiagInfo addi r12, r11, KDP.DiagInfo
stw r12, NKDiagInfoPtr & 0xFFF(r1) stw r12, NKDiagInfoPtr & 0xFFF(r1)
li r12, 0x100 li r12, 0x100
sth r12, NKDiagInfoVer & 0xFFF(r1) sth r12, NKDiagInfoVer & 0xFFF(r1)
li r12, NKDiagInfo.Size li r12, NKDiagInfo.Size
sth r12, NKDiagInfoLen & 0xFFF(r1) sth r12, NKDiagInfoLen & 0xFFF(r1)
addi r12, r11, KDP.SysInfo addi r12, r11, KDP.SysInfo
stw r12, NKSystemInfoPtr & 0xFFF(r1) stw r12, NKSystemInfoPtr & 0xFFF(r1)
li r12, 0x102 li r12, 0x102
sth r12, NKSystemInfoVer & 0xFFF(r1) sth r12, NKSystemInfoVer & 0xFFF(r1)
li r12, NKSystemInfo.Size li r12, NKSystemInfo.Size
sth r12, NKSystemInfoLen & 0xFFF(r1) sth r12, NKSystemInfoLen & 0xFFF(r1)
addi r12, r11, KDP.ProcInfo addi r12, r11, KDP.ProcInfo
stw r12, 0xFF8(r1) stw r12, 0xFF8(r1)
li r12, 0x100 li r12, 0x100
sth r12, 0xFFC(r1) sth r12, 0xFFC(r1)
li r12, NKProcessorInfo.Size li r12, NKProcessorInfo.Size
sth r12, 0xFFE(r1) sth r12, 0xFFE(r1)
######################################################################## ########################################################################
InitProcessorInfo InitProcessorInfo
mfpvr r12 mfpvr r12
stw r12, KDP.ProcInfo.ProcessorVersionReg(r1) stw r12, KDP.ProcInfo.ProcessorVersionReg(r1)
srwi r12, r12, 16 srwi r12, r12, 16
lwz r11, KDP.CodeBase(r1) lwz r11, KDP.CodeBase(r1)
addi r10, r1, KDP.ProcInfo.Ovr addi r10, r1, KDP.ProcInfo.Ovr
li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr li r9, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
cmpwi r12, 1 ; 601 cmpwi r12, 1 ; 601
_kaddr r11, r11, ProcessorInfoTable _kaddr r11, r11, ProcessorInfoTable
beq CopyProcessorInfo beq CopyProcessorInfo
cmpwi r12, 3 ; 603 cmpwi r12, 3 ; 603
addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
beq CopyProcessorInfo beq CopyProcessorInfo
cmpwi r12, 4 ; 604 cmpwi r12, 4 ; 604
addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr addi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
beq CopyProcessorInfo beq CopyProcessorInfo
subi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr subi r11, r11, NKProcessorInfo.OvrEnd - NKProcessorInfo.Ovr
b CopyProcessorInfo b CopyProcessorInfo
ProcessorInfoTable ProcessorInfoTable
; 601 ; 601
dc.l 0x1000 ; PageSize dc.l 0x1000 ; PageSize
dc.l 0x8000 ; DataCacheTotalSize dc.l 0x8000 ; DataCacheTotalSize
dc.l 0x8000 ; InstCacheTotalSize dc.l 0x8000 ; InstCacheTotalSize
dc.w 0x20 ; CoherencyBlockSize dc.w 0x20 ; CoherencyBlockSize
dc.w 0x20 ; ReservationGranuleSize dc.w 0x20 ; ReservationGranuleSize
dc.w 1 ; CombinedCaches dc.w 1 ; CombinedCaches
dc.w 0x40 ; InstCacheLineSize dc.w 0x40 ; InstCacheLineSize
dc.w 0x40 ; DataCacheLineSize dc.w 0x40 ; DataCacheLineSize
dc.w 0x20 ; DataCacheBlockSizeTouch dc.w 0x20 ; DataCacheBlockSizeTouch
dc.w 0x20 ; InstCacheBlockSize dc.w 0x20 ; InstCacheBlockSize
dc.w 0x20 ; DataCacheBlockSize dc.w 0x20 ; DataCacheBlockSize
dc.w 8 ; InstCacheAssociativity dc.w 8 ; InstCacheAssociativity
dc.w 8 ; DataCacheAssociativity dc.w 8 ; DataCacheAssociativity
dc.w 0x100 ; TransCacheTotalSize dc.w 0x100 ; TransCacheTotalSize
dc.w 2 ; TransCacheAssociativity dc.w 2 ; TransCacheAssociativity
; 603 ; 603
dc.l 0x1000 ; PageSize dc.l 0x1000 ; PageSize
dc.l 0x2000 ; DataCacheTotalSize dc.l 0x2000 ; DataCacheTotalSize
dc.l 0x2000 ; InstCacheTotalSize dc.l 0x2000 ; InstCacheTotalSize
dc.w 0x20 ; CoherencyBlockSize dc.w 0x20 ; CoherencyBlockSize
dc.w 0x20 ; ReservationGranuleSize dc.w 0x20 ; ReservationGranuleSize
dc.w 0 ; CombinedCaches dc.w 0 ; CombinedCaches
dc.w 0x20 ; InstCacheLineSize dc.w 0x20 ; InstCacheLineSize
dc.w 0x20 ; DataCacheLineSize dc.w 0x20 ; DataCacheLineSize
dc.w 0x20 ; DataCacheBlockSizeTouch dc.w 0x20 ; DataCacheBlockSizeTouch
dc.w 0x20 ; InstCacheBlockSize dc.w 0x20 ; InstCacheBlockSize
dc.w 0x20 ; DataCacheBlockSize dc.w 0x20 ; DataCacheBlockSize
dc.w 2 ; InstCacheAssociativity dc.w 2 ; InstCacheAssociativity
dc.w 2 ; DataCacheAssociativity dc.w 2 ; DataCacheAssociativity
dc.w 0x40 ; TransCacheTotalSize dc.w 0x40 ; TransCacheTotalSize
dc.w 2 ; TransCacheAssociativity dc.w 2 ; TransCacheAssociativity
; 604 ; 604
dc.l 0x1000 ; PageSize dc.l 0x1000 ; PageSize
dc.l 0x4000 ; DataCacheTotalSize dc.l 0x4000 ; DataCacheTotalSize
dc.l 0x4000 ; InstCacheTotalSize dc.l 0x4000 ; InstCacheTotalSize
dc.w 0x20 ; CoherencyBlockSize dc.w 0x20 ; CoherencyBlockSize
dc.w 0x20 ; ReservationGranuleSize dc.w 0x20 ; ReservationGranuleSize
dc.w 0 ; CombinedCaches dc.w 0 ; CombinedCaches
dc.w 0x20 ; InstCacheLineSize dc.w 0x20 ; InstCacheLineSize
dc.w 0x20 ; DataCacheLineSize dc.w 0x20 ; DataCacheLineSize
dc.w 0x20 ; DataCacheBlockSizeTouch dc.w 0x20 ; DataCacheBlockSizeTouch
dc.w 0x20 ; InstCacheBlockSize dc.w 0x20 ; InstCacheBlockSize
dc.w 0x20 ; DataCacheBlockSize dc.w 0x20 ; DataCacheBlockSize
dc.w 4 ; InstCacheAssociativity dc.w 4 ; InstCacheAssociativity
dc.w 4 ; DataCacheAssociativity dc.w 4 ; DataCacheAssociativity
dc.w 0x40 ; TransCacheTotalSize dc.w 0x40 ; TransCacheTotalSize
dc.w 2 ; TransCacheAssociativity dc.w 2 ; TransCacheAssociativity
CopyProcessorInfo CopyProcessorInfo
@loop @loop
subic. r9, r9, 4 subic. r9, r9, 4
lwzx r12, r11, r9 lwzx r12, r11, r9
stwx r12, r10, r9 stwx r12, r10, r9
bgt @loop bgt @loop
######################################################################## ########################################################################
InitEmulator InitEmulator
lwz r11, NKConfigurationInfo.BootVersionOffset(rCI) ; Copy 16b boot ver string lwz r11, NKConfigurationInfo.BootVersionOffset(rCI) ; Copy 16b boot ver string
lwz r12, NKConfigurationInfo.BootstrapVersion(rCI) ; ("Boot PDM 601 1.0") lwz r12, NKConfigurationInfo.BootstrapVersion(rCI) ; ("Boot PDM 601 1.0")
stwux r12, r11, rED ; into emulator data area stwux r12, r11, rED ; into emulator data area
lwz r12, NKConfigurationInfo.BootstrapVersion + 4(rCI) lwz r12, NKConfigurationInfo.BootstrapVersion + 4(rCI)
stw r12, 4(r11) stw r12, 4(r11)
lwz r12, NKConfigurationInfo.BootstrapVersion + 8(rCI) lwz r12, NKConfigurationInfo.BootstrapVersion + 8(rCI)
stw r12, 8(r11) stw r12, 8(r11)
lwz r12, NKConfigurationInfo.BootstrapVersion + 12(rCI) lwz r12, NKConfigurationInfo.BootstrapVersion + 12(rCI)
stw r12, 12(r11) stw r12, 12(r11)
lwz r12, NKConfigurationInfo.LA_EmulatorCode(rCI) ; Prepare the System ContextBlock: lwz r12, NKConfigurationInfo.LA_EmulatorCode(rCI) ; Prepare the System ContextBlock:
lwz r11, NKConfigurationInfo.EmulatorEntryOffset(rCI) lwz r11, NKConfigurationInfo.EmulatorEntryOffset(rCI)
add r12, r11, r12 add r12, r11, r12
lwz r11, NKConfigurationInfo.ECBOffset(rCI) ; address of declared Emu entry point lwz r11, NKConfigurationInfo.ECBOffset(rCI) ; address of declared Emu entry point
add r11, r11, rED add r11, r11, rED
stw r12, CB.FaultSrcPC+4(r11) stw r12, CB.FaultSrcPC+4(r11)
lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI) ; address of Emu global page lwz r12, NKConfigurationInfo.LA_EmulatorData(rCI) ; address of Emu global page
stw r12, CB.FaultSrcR3+4(r11) stw r12, CB.FaultSrcR3+4(r11)
lwz r12, NKConfigurationInfo.LA_DispatchTable(rCI) ; address of 512kb Emu dispatch table lwz r12, NKConfigurationInfo.LA_DispatchTable(rCI) ; address of 512kb Emu dispatch table
stw r12, CB.FaultSrcR4+4(r11) stw r12, CB.FaultSrcR4+4(r11)
lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; address of KCallReturnFromException trap lwz r12, KDP.EmuKCallTblPtrLogical(r1) ; address of KCallReturnFromException trap
stw r12, CB.IntraState.HandlerReturn+4(r11) stw r12, CB.IntraState.HandlerReturn+4(r11)
lwz r10, KDP.LowMemPtr(r1) ; Zero out bottom 8k of Low Memory lwz r10, KDP.LowMemPtr(r1) ; Zero out bottom 8k of Low Memory
li r9, 0x2000 li r9, 0x2000
@zeroloop @zeroloop
subic. r9, r9, 4 subic. r9, r9, 4
stwx r0, r10, r9 stwx r0, r10, r9
bne @zeroloop bne @zeroloop
lwz r11, NKConfigurationInfo.MacLowMemInitOffset(rCI) ; Read address/value pairs from ConfigInfo lwz r11, NKConfigurationInfo.MacLowMemInitOffset(rCI) ; Read address/value pairs from ConfigInfo
lwz r10, KDP.LowMemPtr(r1) ; and apply them to Low Memory lwz r10, KDP.LowMemPtr(r1) ; and apply them to Low Memory
lwzux r9, r11, rCI lwzux r9, r11, rCI
@setloop @setloop
mr. r9, r9 mr. r9, r9
beq @donelm beq @donelm
lwzu r12, 4(r11) lwzu r12, 4(r11)
stwx r12, r10, r9 stwx r12, r10, r9
lwzu r9, 4(r11) lwzu r9, 4(r11)
b @setloop b @setloop
@donelm @donelm
mfpvr r7 ; Calculate Flags: mfpvr r7 ; Calculate Flags:
srwi r7, r7, 16 srwi r7, r7, 16
cmpwi r7, 1 cmpwi r7, 1
lis r7, GlobalFlagSystem >> 16 ; we will enter System Context (all CPUs) lis r7, GlobalFlagSystem >> 16 ; we will enter System Context (all CPUs)
bne @not_601 bne @not_601
_set r7, r7, bitGlobalFlagMQReg ; but only 601 has MQ register _set r7, r7, bitGlobalFlagMQReg ; but only 601 has MQ register
@not_601 @not_601
stw r7, KDP.Flags(r1) stw r7, KDP.Flags(r1)
lwz r10, KDP.EmuKCallTblPtrLogical(r1) ; Start at KCallReturnFromException trap lwz r10, KDP.EmuKCallTblPtrLogical(r1) ; Start at KCallReturnFromException trap
mfmsr r14 ; Calculate the user space MSR mfmsr r14 ; Calculate the user space MSR
andi. r14, r14, MsrIP ; (not sure why the dot) andi. r14, r14, MsrIP ; (not sure why the dot)
ori r15, r14, MsrME | MsrDR | MsrRI ; does r15 even get used? ori r15, r14, MsrME | MsrDR | MsrRI ; does r15 even get used?
ori r11, r14, MsrEE | MsrPR | MsrME | MsrIR | MsrDR | MsrRI ; <- this is the real one ori r11, r14, MsrEE | MsrPR | MsrME | MsrIR | MsrDR | MsrRI ; <- this is the real one
li r13, 0 ; Zero important registers (r13=CR, r12=LR) li r13, 0 ; Zero important registers (r13=CR, r12=LR)
li r12, 0 li r12, 0
li r0, 0 li r0, 0
li r2, 0 li r2, 0
li r3, 0 li r3, 0
li r4, 0 li r4, 0
######################################################################## ########################################################################
ResetContextClock ResetContextClock
lwz r8, KDP.ProcInfo.DecClockRateHz(r1) lwz r8, KDP.ProcInfo.DecClockRateHz(r1)
stw r8, KDP.OtherContextDEC(r1) stw r8, KDP.OtherContextDEC(r1)
mtdec r8 mtdec r8
######################################################################## ########################################################################
b Reset b Reset

1721
NanoKernel/NKLegacyVM.s
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File diff suppressed because it is too large Load Diff

442
NanoKernel/NKMacros.s
View File

@ -1,337 +1,337 @@
MACRO MACRO
_log &s _log &s
BL @paststring BL @paststring
STRING AsIs STRING AsIs
DC.B &s, 0, 0 DC.B &s, 0, 0
ALIGN 2 ALIGN 2
@paststring @paststring
mflr r8 mflr r8
BL PrintS BL PrintS
ENDM ENDM
; Cool macro for one-line debug calls ; Cool macro for one-line debug calls
MACRO MACRO
_wlog &s1, &reg, &s2, &scratch==r8 _wlog &s1, &reg, &s2, &scratch==r8
if &TYPE('ExtraNKLogging') != 'UNDEFINED' if &TYPE('ExtraNKLogging') != 'UNDEFINED'
mr &scratch, r8 mr &scratch, r8
_log &s1 _log &s1
_log '[ ' _log '[ '
mr r8, &reg mr r8, &reg
bl PrintW bl PrintW
_log ']' _log ']'
_log &s2 _log &s2
mr r8, &scratch mr r8, &scratch
endif endif
ENDM ENDM
MACRO MACRO
_wlogh &s1, &reg, &s2, &scratch==r8 _wlogh &s1, &reg, &s2, &scratch==r8
if &TYPE('ExtraNKLogging') != 'UNDEFINED' if &TYPE('ExtraNKLogging') != 'UNDEFINED'
mr &scratch, r8 mr &scratch, r8
_log &s1 _log &s1
_log '[ ' _log '[ '
mr r8, &reg mr r8, &reg
bl PrintH bl PrintH
_log ']' _log ']'
_log &s2 _log &s2
mr r8, &scratch mr r8, &scratch
endif endif
ENDM ENDM
MACRO MACRO
_clog &s _clog &s
if &TYPE('ExtraNKLogging') != 'UNDEFINED' if &TYPE('ExtraNKLogging') != 'UNDEFINED'
_log &s _log &s
endif endif
ENDM ENDM
MACRO MACRO
LHHI &reg, &val LHHI &reg, &val
lis (&reg), ((&val) >> 16) & 0xffff lis (&reg), ((&val) >> 16) & 0xffff
ENDM ENDM
MACRO MACRO
LLHI &reg, &val LLHI &reg, &val
ori (&reg), (&reg), (&val) & 0xffff ori (&reg), (&reg), (&val) & 0xffff
ENDM ENDM
MACRO MACRO
lisori &reg, &val lisori &reg, &val
lis &reg, ((&val) >> 16) & 0xffff lis &reg, ((&val) >> 16) & 0xffff
ori &reg, &reg, (&val) & 0xffff ori &reg, &reg, (&val) & 0xffff
ENDM ENDM
MACRO MACRO
llabel &reg, &val llabel &reg, &val
lisori &reg, &val - CodeBase lisori &reg, &val - CodeBase
ENDM ENDM
MACRO MACRO
_lstart &reg, &val _lstart &reg, &val
LHHI (&reg), (&val) LHHI (&reg), (&val)
HalfLoadedWord set (&val) HalfLoadedWord set (&val)
HalfLoadedReg set (&reg) HalfLoadedReg set (&reg)
ENDM ENDM
MACRO MACRO
_lfinish _lfinish
LLHI HalfLoadedReg, HalfLoadedWord LLHI HalfLoadedReg, HalfLoadedWord
ENDM ENDM
MACRO MACRO
InitList &ptr, &sig, &scratch==r8 InitList &ptr, &sig, &scratch==r8
_lstart &scratch, &sig _lstart &scratch, &sig
stw &ptr, LLL.Next(&ptr) stw &ptr, LLL.Next(&ptr)
_lfinish _lfinish
stw &ptr, LLL.Prev(&ptr) stw &ptr, LLL.Prev(&ptr)
stw &scratch, LLL.Signature(&ptr) stw &scratch, LLL.Signature(&ptr)
ENDM ENDM
; Next is 8, Prev is C ; Next is 8, Prev is C
MACRO MACRO
InsertAsPrev &el, &next, &scratch==r18 InsertAsPrev &el, &next, &scratch==r18
stw &next, LLL.Next(&el) stw &next, LLL.Next(&el)
lwz &scratch, LLL.Prev(&next) lwz &scratch, LLL.Prev(&next)
stw &scratch, LLL.Prev(&el) stw &scratch, LLL.Prev(&el)
stw &el, LLL.Next(&scratch) stw &el, LLL.Next(&scratch)
stw &el, LLL.Prev(&next) stw &el, LLL.Prev(&next)
ENDM ENDM
MACRO MACRO
InsertAsNext &el, &prev, &scratch==r18 InsertAsNext &el, &prev, &scratch==r18
stw &prev, LLL.Prev(&el) stw &prev, LLL.Prev(&el)
lwz &scratch, LLL.Next(&prev) lwz &scratch, LLL.Next(&prev)
stw &scratch, LLL.Next(&el) stw &scratch, LLL.Next(&el)
stw &el, LLL.Prev(&scratch) stw &el, LLL.Prev(&scratch)
stw &el, LLL.Next(&prev) stw &el, LLL.Next(&prev)
ENDM ENDM
MACRO MACRO
RemoveFromList &el, &scratch1==r17, &scratch2==r18 RemoveFromList &el, &scratch1==r17, &scratch2==r18
; Point neighbours of el up and down at each other ; Point neighbours of el up and down at each other
lwz &scratch1, 8(&el) lwz &scratch1, 8(&el)
lwz &scratch2, 12(&el) lwz &scratch2, 12(&el)
stw &scratch1, 8(&scratch2) stw &scratch1, 8(&scratch2)
stw &scratch2, 12(&scratch1) stw &scratch2, 12(&scratch1)
; Zero out the pointers in el ; Zero out the pointers in el
li &scratch1, 0 li &scratch1, 0
stw &scratch1, 8(&el) stw &scratch1, 8(&el)
stw &scratch1, 12(&el) stw &scratch1, 12(&el)
ENDM ENDM
MACRO MACRO
_Lock &lockoffset, &scratch1==r17, &scratch2==r18 _Lock &lockoffset, &scratch1==r17, &scratch2==r18
mr &scratch1, r8 mr &scratch1, r8
mr &scratch2, r9 mr &scratch2, r9
addi r8, r1, &lockoffset addi r8, r1, &lockoffset
bl AcquireLock bl AcquireLock
mr r8, &scratch1 mr r8, &scratch1
mr r9, &scratch2 mr r9, &scratch2
ENDM ENDM
MACRO MACRO
_AssertAndRelease &lockoffset, &scratch==r18 _AssertAndRelease &lockoffset, &scratch==r18
sync sync
lwz &scratch, &lockoffset(r1) lwz &scratch, &lockoffset(r1)
cmpwi cr1, &scratch, 0 cmpwi cr1, &scratch, 0
li &scratch, 0 li &scratch, 0
bne+ cr1, @okay bne+ cr1, @okay
mflr &scratch mflr &scratch
bl panic bl panic
@okay stw &scratch, &lockoffset(r1) @okay stw &scratch, &lockoffset(r1)
ENDM ENDM
MACRO MACRO
_set &dest, &src, &bit _set &dest, &src, &bit
IF &bit < 16 IF &bit < 16
oris&dot &dest, &src, 1 << (15 - (&bit)) oris&dot &dest, &src, 1 << (15 - (&bit))
ELSE ELSE
ori&dot &dest, &src, 1 << (31 - (&bit)) ori&dot &dest, &src, 1 << (31 - (&bit))
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_clear &dest, &src, &bit _clear &dest, &src, &bit
_clear_rbit set &bit+1 _clear_rbit set &bit+1
if _clear_rbit > 31 if _clear_rbit > 31
_clear_rbit set 0 _clear_rbit set 0
endif endif
_clear_lbit set &bit-1 _clear_lbit set &bit-1
if _clear_lbit < 0 if _clear_lbit < 0
_clear_lbit set 31 _clear_lbit set 31
endif endif
rlwinm&dot &dest, &src, 0, _clear_rbit, _clear_lbit rlwinm&dot &dest, &src, 0, _clear_rbit, _clear_lbit
ENDM ENDM
MACRO MACRO
_band &dest, &src, &bit _band &dest, &src, &bit
IF &bit < 16 IF &bit < 16
andis&dot &dest, &src, 1 << (15 - (&bit)) andis&dot &dest, &src, 1 << (15 - (&bit))
ELSE ELSE
andi&dot &dest, &src, 1 << (31 - (&bit)) andi&dot &dest, &src, 1 << (31 - (&bit))
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_b_if_time_gt &lhi, &rhi, &targ _b_if_time_gt &lhi, &rhi, &targ
cmpw &lhi, &rhi cmpw &lhi, &rhi
cmplw cr1, &lhi + 1, &rhi + 1 cmplw cr1, &lhi + 1, &rhi + 1
bgt &targ bgt &targ
blt @fallthru blt @fallthru
bgt cr1, &targ bgt cr1, &targ
@fallthru @fallthru
ENDM ENDM
MACRO MACRO
_b_if_time_le &lhi, &rhi, &targ _b_if_time_le &lhi, &rhi, &targ
cmpw &lhi, &rhi cmpw &lhi, &rhi
cmplw cr1, &lhi + 1, &rhi + 1 cmplw cr1, &lhi + 1, &rhi + 1
blt &targ blt &targ
bgt @fallthru bgt @fallthru
ble cr1, &targ ble cr1, &targ
@fallthru @fallthru
ENDM ENDM
MACRO MACRO
_RegRangeToContextBlock &first, &last _RegRangeToContextBlock &first, &last
stw &first, $104+8*(&first)(r6) stw &first, $104+8*(&first)(r6)
IF &first != &last IF &first != &last
_RegRangeToContextBlock &first+1, &last _RegRangeToContextBlock &first+1, &last
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_RegRangeFromContextBlock &first, &last _RegRangeFromContextBlock &first, &last
lwz &first, $104+8*(&first)(r6) lwz &first, $104+8*(&first)(r6)
IF &first != &last IF &first != &last
_RegRangeFromContextBlock &first+1, &last _RegRangeFromContextBlock &first+1, &last
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_FloatRangeToContextBlock &first, &last _FloatRangeToContextBlock &first, &last
stfd &first, CB.FloatRegisters+8*(&first)(r6) stfd &first, CB.FloatRegisters+8*(&first)(r6)
IF &first != &last IF &first != &last
_FloatRangeToContextBlock &first+1, &last _FloatRangeToContextBlock &first+1, &last
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_FloatRangeFromContextBlock &first, &last _FloatRangeFromContextBlock &first, &last
lfd &first, CB.FloatRegisters+8*(&first)(r6) lfd &first, CB.FloatRegisters+8*(&first)(r6)
IF &first != &last IF &first != &last
_FloatRangeFromContextBlock &first+1, &last _FloatRangeFromContextBlock &first+1, &last
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_InvalNCBPointerCache &scratch==r0, &offset==0 _InvalNCBPointerCache &scratch==r0, &offset==0
IF &offset = 0 IF &offset = 0
li &scratch, -1 li &scratch, -1
ENDIF ENDIF
IF KDP.NCBPointerCache + &offset < KDP.NCBPointerCacheEnd IF KDP.NCBPointerCache + &offset < KDP.NCBPointerCacheEnd
stw &scratch, KDP.NCBPointerCache + &offset(r1) stw &scratch, KDP.NCBPointerCache + &offset(r1)
_InvalNCBPointerCache scratch=&scratch, offset=(&offset+8) _InvalNCBPointerCache scratch=&scratch, offset=(&offset+8)
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_kaddr &rd, &rs, &label _kaddr &rd, &rs, &label
addi &rd, &rs, (&label-CodeBase) addi &rd, &rs, (&label-CodeBase)
ENDM ENDM
MACRO MACRO
_alignToCacheBlock _alignToCacheBlock
IF (*-CodeBase) & 0x1f IF (*-CodeBase) & 0x1f
b * + 4 b * + 4
_alignToCacheBlock _alignToCacheBlock
ENDIF ENDIF
ENDM ENDM
MACRO MACRO
_align &arg _align &arg
my_align set 1 << (&arg) my_align set 1 << (&arg)
my_mask set my_align - 1 my_mask set my_align - 1
my_offset set * - CodeBase my_offset set * - CodeBase
my_pad set (my_align - (my_offset & my_mask)) & my_mask my_pad set (my_align - (my_offset & my_mask)) & my_mask
IF my_pad IF my_pad
dcb.l my_pad>>2, 0x48000004 dcb.l my_pad>>2, 0x48000004
ENDIF ENDIF
ENDM ENDM

44
NanoKernel/NKMakeFile
View File

@ -2,27 +2,27 @@
# NKDir, NKIncDir, NKBin # NKDir, NKIncDir, NKBin
NKFiles = ¶ NKFiles = ¶
{NKDir}NanoKernel.s {NKDir}NanoKernel.s
{NKDir}NKStructs.s {NKDir}NKStructs.s
{NKDir}NKEquates.s {NKDir}NKEquates.s
{NKDir}NKMacros.s {NKDir}NKMacros.s
{NKDir}NKInit.s {NKDir}NKInit.s
{NKDir}NKSystemCrash.s {NKDir}NKSystemCrash.s
{NKDir}NKHotInts.s {NKDir}NKHotInts.s
{NKDir}NKColdInts.s {NKDir}NKColdInts.s
{NKDir}MROptabCode.s {NKDir}MROptabCode.s
{NKDir}MRMemtabCode.s {NKDir}MRMemtabCode.s
{NKDir}MRInterrupts.s {NKDir}MRInterrupts.s
{NKDir}MROptab.s {NKDir}MROptab.s
{NKDir}MRMemtab.s {NKDir}MRMemtab.s
{NKDir}MRRestab.s {NKDir}MRRestab.s
{NKDir}NKMemory.s {NKDir}NKMemory.s
{NKDir}NKExceptions.s {NKDir}NKExceptions.s
{NKDir}NKFloatingPt.s {NKDir}NKFloatingPt.s
{NKDir}NKSoftInts.s {NKDir}NKSoftInts.s
{NKDir}NKReset.s {NKDir}NKReset.s
{NKDir}NKLegacyVM.s {NKDir}NKLegacyVM.s
# We get warning 3202 from ALIGN directives -- kill it # We get warning 3202 from ALIGN directives -- kill it
{NKBin} Ä {NKDir}NanoKernel.s {NKFiles} {NKBin} Ä {NKDir}NanoKernel.s {NKFiles}
PPCAsm -o {Targ} -w 3202 -i {NKIncDir} -i "{AIncludes}" {NKDir}NanoKernel.s PPCAsm -o {Targ} -w 3202 -i {NKIncDir} -i "{AIncludes}" {NKDir}NanoKernel.s

890
NanoKernel/NKMemory.s
View File

@ -1,541 +1,549 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; NKSystemCrash
; SystemCrash
; EXPORTS:
; FlushTLB (=> NKReset)
; GetPhysical (=> MRInterrupts, NKSoftInts)
; PutPTE (=> MRInterrupts, NKColdInts, NKLegacyVM, NKReset)
; SetMap (=> NKReset)
######################################################################## ########################################################################
######################################################################## ########################################################################
PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault PutPTE ; EA r27 // PTE r30/r31, EQ=Success, GT=Invalid, LT=Fault
lwz r29, KDP.CurMap.SegMapPtr(r1) ; late addition: r29 used to be an argument lwz r29, KDP.CurMap.SegMapPtr(r1)
rlwinm r28, r27, 7, 0x0000000F << 3 ; convert segment of passed ptr to offset into SegMap rlwinm r28, r27, 7, 0x0000000F << 3 ; convert segment of passed ptr to offset into SegMap
lwzx r29, r29, r28 ; r29 = ptr to start of segment in PageMap lwzx r29, r29, r28 ; r29 = ptr to start of segment in PageMap
rlwinm r28, r27, 20, 0x0000FFFF ; r27 = page index within SegMap rlwinm r28, r27, 20, 0x0000FFFF ; r27 = page index within SegMap
lhz r30, PME.LBase(r29) lhz r30, PME.LBase(r29)
b @find_pme b @find_pme
@try_next_pme ; Point r29 to the PageMapEntry that concerns this page @try_next_pme ; Point r29 to the PageMapEntry that concerns this page
lhzu r30, 8(r29) ; get another PME.LBase lhzu r30, 8(r29) ; get another PME.LBase
@find_pme @find_pme
lhz r31, PME.PageCount(r29) lhz r31, PME.PageCount(r29)
subf r30, r30, r28 ; r30 = page index within area subf r30, r30, r28 ; r30 = page index within area
cmplw cr7, r30, r31 cmplw cr7, r30, r31
bgt cr7, @try_next_pme bgt cr7, @try_next_pme
lwz r28, KDP.HtabTempEntryPtr(r1) ; (remove temp PTE if present) lwz r28, KDP.HtabTempEntryPtr(r1) ; (remove temp PTE if present)
lwz r31, PME.PBaseAndFlags(r29) lwz r31, PME.PBaseAndFlags(r29)
cmpwi cr7, r28, 0 ; (remove temp PTE if present) cmpwi cr7, r28, 0 ; (remove temp PTE if present)
extlwi. r26, r31, 2, 20 ; DaddyFlag and CountingFlag in top bits extlwi. r26, r31, 2, 20 ; DaddyFlag and CountingFlag in top bits
bne cr7, @remove_temp_pte ; (remove temp PTE if present) bne cr7, @remove_temp_pte ; (remove temp PTE if present)
blt @daddy_flag ; >>>>> DaddyFlag = 1 blt @daddy_flag ; >>>>> DaddyFlag = 1
@return_remove_temp_pte ; (optimized: if LT then to jumps to @daddy_flag) @return_remove_temp_pte ; (optimized: if LT then to jumps to @daddy_flag)
bgt @create_temp_pte ; >>>>> DaddyFlag = 0, CountingFlag = 1 bgt @create_temp_pte ; >>>>> DaddyFlag = 0, CountingFlag = 1
; fallthru ; >>>>> DaddyFlag = 0, CountingFlag = 0 ; fallthru ; >>>>> DaddyFlag = 0, CountingFlag = 0
######################################################################## ########################################################################
; CODE TO CREATE A PAGE TABLE ENTRY ; CODE TO CREATE A PAGE TABLE ENTRY
; <<<<< Fallthru from main entry point (top two flags of PME are zero) ; <<<<< Fallthru from main entry point (top two flags of PME are zero)
slwi r28, r30, 12 slwi r28, r30, 12
add r31, r31, r28 ; r31 = physical page ptr plus 12 bits of PageMapEntry flags add r31, r31, r28 ; r31 = physical page ptr plus 12 bits of PageMapEntry flags
@return_daddy_flag ; <<<<< @daddy_flag comes here @return_daddy_flag ; <<<<< @daddy_flag comes here
@return_create_temp_pte ; <<<<< @create_temp_pte comes here (r31=pageptr, r26=0x5A5A) @return_create_temp_pte ; <<<<< @create_temp_pte comes here (r31=pageptr, r26=0x5A5A)
mfsrin r30, r27 ; HASH FUNCTION: get address of PTEG mfsrin r30, r27 ; HASH FUNCTION: get address of PTEG
rlwinm r28, r27, 26, 10, 25 ; r28 = (1st arg of XOR) * 64b rlwinm r28, r27, 26, 10, 25 ; r28 = (1st arg of XOR) * 64b
rlwinm r30, r30, 6, 7, 25 ; r30 = (2nd arg of XOR) * 64b rlwinm r30, r30, 6, 7, 25 ; r30 = (2nd arg of XOR) * 64b
xor r28, r28, r30 ; r28 (hash output * 64b) = r28 ^ r30 xor r28, r28, r30 ; r28 (hash output * 64b) = r28 ^ r30
lwz r30, KDP.PTEGMask(r1) lwz r30, KDP.PTEGMask(r1)
lwz r29, KDP.HTABORG(r1) lwz r29, KDP.HTABORG(r1)
and r28, r28, r30 and r28, r28, r30
or. r29, r29, r28 ; result (PTEG address) into r29 or. r29, r29, r28 ; result (PTEG address) into r29
@retry_other_pteg ; <<<<< @no_blanks_in_pteg can return here after doing sec'dary hash @retry_other_pteg ; <<<<< @no_blanks_in_pteg can return here after doing sec'dary hash
lwz r30, 0(r29) ; Take address of PTEG in r29, find empty/"invalid" PTE within (optimized!) lwz r30, 0(r29) ; Take address of PTEG in r29, find empty/"invalid" PTE within (optimized!)
lwz r28, 8(r29) lwz r28, 8(r29)
cmpwi cr6, r30, 0 cmpwi cr6, r30, 0
lwz r30, 16(r29) lwz r30, 16(r29)
cmpwi cr7, r28, 0 cmpwi cr7, r28, 0
lwzu r28, 24(r29) lwzu r28, 24(r29)
bge cr6, @found_blank_pte bge cr6, @found_blank_pte
cmpwi cr6, r30, 0 cmpwi cr6, r30, 0
lwzu r30, 8(r29) lwzu r30, 8(r29)
bge cr7, @found_blank_pte bge cr7, @found_blank_pte
cmpwi cr7, r28, 0 cmpwi cr7, r28, 0
lwzu r28, 8(r29) lwzu r28, 8(r29)
bge cr6, @found_blank_pte bge cr6, @found_blank_pte
cmpwi cr6, r30, 0 cmpwi cr6, r30, 0
lwzu r30, 8(r29) lwzu r30, 8(r29)
bge cr7, @found_blank_pte bge cr7, @found_blank_pte
cmpwi cr7, r28, 0 cmpwi cr7, r28, 0
lwzu r28, 8(r29) lwzu r28, 8(r29)
bge cr6, @found_blank_pte bge cr6, @found_blank_pte
cmpwi cr6, r30, 0 cmpwi cr6, r30, 0
addi r29, r29, 8 addi r29, r29, 8
bge cr7, @found_blank_pte bge cr7, @found_blank_pte
cmpwi cr7, r28, 0 cmpwi cr7, r28, 0
addi r29, r29, 8 addi r29, r29, 8
bge cr6, @found_blank_pte bge cr6, @found_blank_pte
rlwinm r28, r31, 0, 26, 26 ; wImg bit in PTE??? rlwinm r28, r31, 0, 26, 26 ; wImg bit in PTE???
addi r29, r29, 8 ; Leave PTE + 24 in r29 addi r29, r29, 8 ; Leave PTE + 24 in r29
blt cr7, @no_blanks_in_pteg ; >>>>> This might cause PutPTE to return an error (BNE) blt cr7, @no_blanks_in_pteg ; >>>>> This might cause PutPTE to return an error (BNE)
@found_blank_pte ; Take PTE address (plus 24) in r29, draft PTE[lo] in r31 @found_blank_pte ; Take PTE address (plus 24) in r29, draft PTE[lo] in r31
cmpwi r26, 0 ; NOTE: top bit of r31 will be set if sec'dary hash func was used cmpwi r26, 0 ; NOTE: top bit of r31 will be set if sec'dary hash func was used
mfsrin r28, r27 mfsrin r28, r27
extrwi r30, r27, 6, 4 ; PTE[API/26-31] taken from upper 6 bits of offset-within-segment extrwi r30, r27, 6, 4 ; PTE[API/26-31] taken from upper 6 bits of offset-within-segment
stw r27, KDP.HtabLastEA(r1) stw r27, KDP.HtabLastEA(r1)
ori r31, r31, 0x100 ; set PTE[R(eference)] ori r31, r31, 0x100 ; set PTE[R(eference)]
rlwimi r30, r31, 27, 25, 25 ; set PTE[H(ash func ID)] to cheeky topmost bit of the phys addr in r31 rlwimi r30, r31, 27, 25, 25 ; set PTE[H(ash func ID)] to cheeky topmost bit of the phys addr in r31
rlwinm r31, r31, 0, 21, 19 ; unset upper reserved bit in PTE[lo] rlwinm r31, r31, 0, 21, 19 ; unset upper reserved bit in PTE[lo]
insrwi r30, r28, 24, 1 ; get PTE[VSID] from segment register insrwi r30, r28, 24, 1 ; get PTE[VSID] from segment register
stw r31, -20(r29) ; PTE[lo] = r31 stw r31, -20(r29) ; PTE[lo] = r31
oris r30, r30, 0x8000 ; set PTE[V(alid)] oris r30, r30, 0x8000 ; set PTE[V(alid)]
sync ; because we just wanged the page table sync ; because we just wanged the page table
stwu r30, -24(r29) ; PTE[hi] = r30 stwu r30, -24(r29) ; PTE[hi] = r30
lwz r28, KDP.NKInfo.HashTableCreateCount(r1) lwz r28, KDP.NKInfo.HashTableCreateCount(r1)
stw r29, KDP.ApproxCurrentPTEG(r1) stw r29, KDP.ApproxCurrentPTEG(r1)
addi r28, r28, 1 addi r28, r28, 1
stw r28, KDP.NKInfo.HashTableCreateCount(r1) stw r28, KDP.NKInfo.HashTableCreateCount(r1)
beqlr ; >>>>> RETURN "BEQ" if we got to "Case 1" directly beqlr ; >>>>> RETURN "BEQ" if we got to "Case 1" directly
cmpwi r26, 0x5A5A ; Special value set so that we take note of this new temporary PTE? cmpwi r26, 0x5A5A ; Special value set so that we take note of this new temporary PTE?
bne @notemp bne @notemp
stw r29, KDP.HtabTempEntryPtr(r1) stw r29, KDP.HtabTempEntryPtr(r1)
cmpw r29, r29 ; >>>>> RETURN "BEQ" if we got to "Case 1" via @create_temp_pte cmpw r29, r29 ; >>>>> RETURN "BEQ" if we got to "Case 1" via @create_temp_pte
blr blr
@notemp @notemp
lwz r28, 0(r26) ; Otherwise, we got here via @daddy_flag? Looks nonsensical. lwz r28, 0(r26) ; Otherwise, we got here via @daddy_flag? Looks nonsensical.
lwz r30, KDP.HTABORG(r1) lwz r30, KDP.HTABORG(r1)
ori r28, r28, 0x801 ori r28, r28, 0x801
subf r30, r30, r29 subf r30, r30, r29
cmpw r29, r29 cmpw r29, r29
rlwimi r28, r30, 9, 0, 19 rlwimi r28, r30, 9, 0, 19
stw r28, 0(r26) stw r28, 0(r26)
blr ; >>>>> RETURN "BEQ" otherwise blr ; >>>>> RETURN "BEQ" otherwise
######################################################################## ########################################################################
; Helpful code that jumps back to roughly where it started ; Helpful code that jumps back to roughly where it started
@remove_temp_pte @remove_temp_pte
lwz r28, KDP.NKInfo.HashTableDeleteCount(r1) lwz r28, KDP.NKInfo.HashTableDeleteCount(r1)
lwz r29, KDP.HtabTempEntryPtr(r1) lwz r29, KDP.HtabTempEntryPtr(r1)
addi r28, r28, 1 addi r28, r28, 1
stw r28, KDP.NKInfo.HashTableDeleteCount(r1) stw r28, KDP.NKInfo.HashTableDeleteCount(r1)
li r28, 0 li r28, 0
stw r28, 0(r29) stw r28, 0(r29)
lwz r29, KDP.HtabTempPage(r1) lwz r29, KDP.HtabTempPage(r1)
stw r28, KDP.HtabTempPage(r1) stw r28, KDP.HtabTempPage(r1)
stw r28, KDP.HtabTempEntryPtr(r1) stw r28, KDP.HtabTempEntryPtr(r1)
sync sync
tlbie r29 tlbie r29
sync sync
bge @return_remove_temp_pte ; Optimization: would otherwise branch to a "blt @daddy_flag" bge @return_remove_temp_pte ; Optimization: would otherwise branch to a "blt @daddy_flag"
######################################################################## ########################################################################
; r30 = page index within area, r31 = PBaseAndFlags ; r30 = page index within area, r31 = PBaseAndFlags
@daddy_flag @daddy_flag
extlwi. r28, r31, 2, 21 ; top bits of r28 = CountingFlag, PhysicalIsRelativeFlag extlwi. r28, r31, 2, 21 ; top bits of r28 = CountingFlag, PhysicalIsRelativeFlag
bge @return_via_pf2 ; if !CountingFlag: return (if !PIRFlag: via PF2) bge @return_via_pf2 ; if !CountingFlag: return (if !PIRFlag: via PF2)
rlwinm r28, r30, 2, 0xFFFFFFFC ; r28 = pageIdxInArea * 4 rlwinm r28, r30, 2, 0xFFFFFFFC ; r28 = pageIdxInArea * 4
rlwinm r26, r31, 22, 0xFFFFFFFC ; r26 = PIRFlag << 31 | BtmBit << 22 | physBase * 4 rlwinm r26, r31, 22, 0xFFFFFFFC ; r26 = PIRFlag << 31 | BtmBit << 22 | physBase * 4
lwzux r28, r26, r28 ; this makes no sense!! lwzux r28, r26, r28 ; this makes no sense!!
lwz r31, KDP.PageAttributeInit(r1) lwz r31, KDP.PageAttributeInit(r1)
andi. r30, r28, 0x881 andi. r30, r28, 0x881
rlwimi r31, r28, 0, 0xFFFFF000 rlwimi r31, r28, 0, 0xFFFFF000
cmplwi r30, 1 cmplwi r30, 1
cmplwi cr7, r30, 0x81 cmplwi cr7, r30, 0x81
ori r31, r31, 0x100 ori r31, r31, 0x100
rlwimi r31, r28, 3, 24, 24 rlwimi r31, r28, 3, 24, 24
rlwimi r31, r28, 31, 26, 26 rlwimi r31, r28, 31, 26, 26
rlwimi r31, r28, 1, 25, 25 rlwimi r31, r28, 1, 25, 25
xori r31, r31, 0x40 xori r31, r31, 0x40
rlwimi r31, r28, 30, 31, 31 rlwimi r31, r28, 30, 31, 31
beq @return_daddy_flag beq @return_daddy_flag
bltlr cr7 bltlr cr7
bl SystemCrash bl SystemCrash
######################################################################## ########################################################################
; Helpful code that jumps back to roughly where it started ; Helpful code that jumps back to roughly where it started
@create_temp_pte ; Make "temp" PageMapEntry, when flags look like 0x800 @create_temp_pte ; Make "temp" PageMapEntry, when flags look like 0x800
ori r28, r27, 0xfff ; r27 = passed ptr, r31 = PBaseAndFlags ori r28, r27, 0xfff ; r27 = passed ptr, r31 = PBaseAndFlags
stw r28, KDP.HtabTempPage(r1) stw r28, KDP.HtabTempPage(r1)
rlwinm r31, r31, 0, 22, 19 ; clear CountingFlag in r31 rlwinm r31, r31, 0, 22, 19 ; clear CountingFlag in r31
li r26, 0x5A5A ; set magic number in r26 so that KDP.HtabTempEntryPtr gets set li r26, 0x5A5A ; set magic number in r26 so that KDP.HtabTempEntryPtr gets set
b @return_create_temp_pte b @return_create_temp_pte
######################################################################## ########################################################################
; Helpful return code for @daddy_flag ; Helpful return code for @daddy_flag
@return_via_pf2 @return_via_pf2
bgtlr bgtlr
addi r29, r1, KDP.SupervisorMap addi r29, r1, KDP.SupervisorMap
b SetMap b SetMap
######################################################################## ########################################################################
; So try the secondary hashing function, if we haven't already ; So try the secondary hashing function, if we haven't already
@no_blanks_in_pteg @no_blanks_in_pteg
cmplw cr6, r28, r26 cmplw cr6, r28, r26
subi r29, r29, 64 + 16 subi r29, r29, 64 + 16
ble cr6, @search_for_matching_pte ble cr6, @search_for_matching_pte
crnot cr0_eq, cr0_eq crnot cr0_eq, cr0_eq
lwz r30, KDP.PTEGMask(r1) lwz r30, KDP.PTEGMask(r1)
xori r31, r31, 0x800 xori r31, r31, 0x800
xor r29, r29, r30 xor r29, r29, r30
beq @retry_other_pteg beq @retry_other_pteg
######################################################################## ########################################################################
@search_for_matching_pte ; r29 = full PTEG @search_for_matching_pte ; r29 = full PTEG
lwz r26, KDP.OverflowingPTEG(r1) ; this could be zero lwz r26, KDP.OverflowingPTEG(r1) ; this could be zero
crclr cr6_eq ; prepare to return "failure" crclr cr6_eq ; prepare to return "failure"
rlwimi r26, r29, 0, -64 rlwimi r26, r29, 0, -64
addi r29, r26, 8 addi r29, r26, 8
b @first_pte b @first_pte
@rethink_pte_search @rethink_pte_search
bne cr6, @next_pte bne cr6, @next_pte
mr r26, r29 mr r26, r29
@next_pte @next_pte
cmpw cr6, r29, r26 cmpw cr6, r29, r26
addi r29, r29, 8 addi r29, r29, 8
@first_pte @first_pte
rlwimi r29, r26, 0, 0, 25 rlwimi r29, r26, 0, 0, 25
lwz r31, 4(r29) lwz r31, 4(r29)
lwz r30, 0(r29) lwz r30, 0(r29)
beq cr6, @got_pte beq cr6, @got_pte
rlwinm r28, r31, 30, 25, 25 rlwinm r28, r31, 30, 25, 25
andc. r28, r28, r30 ; R && !H (i.e. page has been read and is not in "secondary hash" PTEG) andc. r28, r28, r30 ; R && !H (i.e. page has been read and is not in "secondary hash" PTEG)
bne @next_pte ; if so, bne @next_pte ; if so,
@got_pte @got_pte
######################################################################## ########################################################################
clrlwi r28, r31, 30 clrlwi r28, r31, 30
cmpwi cr7, r28, 0 cmpwi cr7, r28, 0
clrrwi r28, r31, 12 clrrwi r28, r31, 12
cmpw r28, r1 cmpw r28, r1
lwz r30, KDP.ContextPtr(r1) lwz r30, KDP.ContextPtr(r1)
beq cr7, @rethink_pte_search beq cr7, @rethink_pte_search
addi r31, r30, 768-1 addi r31, r30, 768-1
beq @rethink_pte_search beq @rethink_pte_search
rlwinm r30, r30, 0, 0xFFFFF000 rlwinm r30, r30, 0, 0xFFFFF000
cmpwi cr7, r28, 30 cmpwi cr7, r28, 30
lwz r30, 0(r29) lwz r30, 0(r29)
rlwinm r31, r31, 0, 0xFFFFF000 rlwinm r31, r31, 0, 0xFFFFF000
cmpwi r28, 31 cmpwi r28, 31
rlwinm r31, r30, 0, 0x00000040 rlwinm r31, r30, 0, 0x00000040
beq cr7, @rethink_pte_search beq cr7, @rethink_pte_search
extlwi r28, r30, 4, 1 extlwi r28, r30, 4, 1
beq @rethink_pte_search beq @rethink_pte_search
neg r31, r31 neg r31, r31
insrwi r28, r30, 6, 4 insrwi r28, r30, 6, 4
xor r31, r31, r29 xor r31, r31, r29
rlwimi r28, r30, 5, 10, 19 rlwimi r28, r30, 5, 10, 19
rlwinm r31, r31, 6, 10, 19 rlwinm r31, r31, 6, 10, 19
xor r28, r28, r31 xor r28, r28, r31
lwz r26, KDP.CurMap.SegMapPtr(r1) lwz r26, KDP.CurMap.SegMapPtr(r1)
rlwinm r30, r28, (32-25), 0x00000078 rlwinm r30, r28, (32-25), 0x00000078
lwzx r26, r26, r30 ; r26 pts into PageMap @ current segment lwzx r26, r26, r30 ; r26 pts into PageMap @ current segment
@tinyloop ; find the last non-blank PME in the segment @tinyloop ; find the last non-blank PME in the segment
lhz r30, PME.LBase(r26) lhz r30, PME.LBase(r26)
rlwinm r31, r28, 20, 0x0000FFFF rlwinm r31, r28, 20, 0x0000FFFF
subf r30, r30, r31 subf r30, r30, r31
lhz r31, PME.PageCount(r26) lhz r31, PME.PageCount(r26)
addi r26, r26, 8 addi r26, r26, 8
cmplw cr7, r30, r31 cmplw cr7, r30, r31
lwz r31, PME.PBaseAndFlags - 8(r26) lwz r31, PME.PBaseAndFlags - 8(r26)
andi. r31, r31, 0xe01 andi. r31, r31, 0xe01
cmpwi r31, 0xa01 cmpwi r31, 0xa01
bgt cr7, @tinyloop bgt cr7, @tinyloop
beq @tinyloop beq @tinyloop
lwz r26, PME.PBaseAndFlags - 8(r26) ; got that PME (26) lwz r26, PME.PBaseAndFlags - 8(r26) ; got that PME (26)
slwi r30, r30, 2 slwi r30, r30, 2
extrwi r31, r26, 2, 20 extrwi r31, r26, 2, 20
cmpwi cr7, r31, 3 ; not a DaddyFlag + CountingFlag? Try again! cmpwi cr7, r31, 3 ; not a DaddyFlag + CountingFlag? Try again!
lwz r31, KDP.NKInfo.HashTableOverflowCount(r1) lwz r31, KDP.NKInfo.HashTableOverflowCount(r1)
stw r29, KDP.OverflowingPTEG(r1) stw r29, KDP.OverflowingPTEG(r1)
addi r31, r31, 1 addi r31, r31, 1
stw r31, KDP.NKInfo.HashTableOverflowCount(r1) stw r31, KDP.NKInfo.HashTableOverflowCount(r1)
lwz r31, KDP.NKInfo.HashTableDeleteCount(r1) lwz r31, KDP.NKInfo.HashTableDeleteCount(r1)
stw r30, 0(r29) stw r30, 0(r29)
addi r31, r31, 1 addi r31, r31, 1
stw r31, KDP.NKInfo.HashTableDeleteCount(r1) stw r31, KDP.NKInfo.HashTableDeleteCount(r1)
sync sync
tlbie r28 tlbie r28
sync sync
_InvalNCBPointerCache scratch=r28 _InvalNCBPointerCache scratch=r28
bne cr7, PutPTE ; not a DaddyFlag + CountingFlag? Retriable... bne cr7, PutPTE ; not a DaddyFlag + CountingFlag? Retriable...
rlwinm r26, r26, 22, 0xFFFFFFFC ; PIRFlag << 31 | BtmBit << 22 | physBase * 4 rlwinm r26, r26, 22, 0xFFFFFFFC ; PIRFlag << 31 | BtmBit << 22 | physBase * 4
lwzux r28, r26, r30 lwzux r28, r26, r30
lwz r31, 4(r29) lwz r31, 4(r29)
andi. r30, r28, 0x800 andi. r30, r28, 0x800
rlwinm r30, r28, (32-9), 0x007FFFF8 rlwinm r30, r28, (32-9), 0x007FFFF8
xor r30, r30, r29 xor r30, r30, r29
beq SystemCrash beq SystemCrash
andi. r30, r30, 0xffff andi. r30, r30, 0xffff
xori r28, r28, 0x800 xori r28, r28, 0x800
bne SystemCrash bne SystemCrash
rlwimi r28, r31, 0, 0, 19 ; r28 = EA of victim of overflow rlwimi r28, r31, 0, 0, 19 ; r28 = EA of victim of overflow
rlwimi r28, r31, 29, 27, 27 rlwimi r28, r31, 29, 27, 27
rlwimi r28, r31, 27, 28, 28 rlwimi r28, r31, 27, 28, 28
stw r28, 0(r26) stw r28, 0(r26)
b PutPTE b PutPTE
######################################################################## ########################################################################
######################################################################## ########################################################################
SetMap ; MemMap r29 SetMap ; MemMap r29
lwz r28, MemMap.SegMapPtr(r29) lwz r28, MemMap.SegMapPtr(r29)
stw r28, KDP.CurMap.SegMapPtr(r1) stw r28, KDP.CurMap.SegMapPtr(r1)
addi r28, r28, 16*8 + 4 addi r28, r28, 16*8 + 4
lis r31, 0 lis r31, 0
@next_seg ; SEGMENT REGISTERS @next_seg ; SEGMENT REGISTERS
lwzu r30, -8(r28) lwzu r30, -8(r28)
subis r31, r31, 0x1000 subis r31, r31, 0x1000
mr. r31, r31 mr. r31, r31
mtsrin r30, r31 mtsrin r30, r31
bne @next_seg bne @next_seg
mfpvr r31 mfpvr r31
lwz r28, MemMap.BatMap(r29) lwz r28, MemMap.BatMap(r29)
andis. r31, r31, 0xFFFE andis. r31, r31, 0xFFFE
addi r29, r1, 0 addi r29, r1, 0
stw r28, KDP.CurMap.BatMap(r1) stw r28, KDP.CurMap.BatMap(r1)
beq @601 beq @601
rlwimi r29, r28, 7, 0x00000078 ; BATS, non-601 rlwimi r29, r28, 7, 0x00000078 ; BATS, non-601
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr ibat0u, r30 mtspr ibat0u, r30
mtspr ibat0l, r31 mtspr ibat0l, r31
stw r30, KDP.CurIBAT0.U(r1) stw r30, KDP.CurIBAT0.U(r1)
stw r31, KDP.CurIBAT0.L(r1) stw r31, KDP.CurIBAT0.L(r1)
rlwimi r29, r28, 11, 0x00000078 rlwimi r29, r28, 11, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr ibat1u, r30 mtspr ibat1u, r30
mtspr ibat1l, r31 mtspr ibat1l, r31
stw r30, KDP.CurIBAT1.U(r1) stw r30, KDP.CurIBAT1.U(r1)
stw r31, KDP.CurIBAT1.L(r1) stw r31, KDP.CurIBAT1.L(r1)
rlwimi r29, r28, 15, 0x00000078 rlwimi r29, r28, 15, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr ibat2u, r30 mtspr ibat2u, r30
mtspr ibat2l, r31 mtspr ibat2l, r31
stw r30, KDP.CurIBAT2.U(r1) stw r30, KDP.CurIBAT2.U(r1)
stw r31, KDP.CurIBAT2.L(r1) stw r31, KDP.CurIBAT2.L(r1)
rlwimi r29, r28, 19, 0x00000078 rlwimi r29, r28, 19, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr ibat3u, r30 mtspr ibat3u, r30
mtspr ibat3l, r31 mtspr ibat3l, r31
stw r30, KDP.CurIBAT3.U(r1) stw r30, KDP.CurIBAT3.U(r1)
stw r31, KDP.CurIBAT3.L(r1) stw r31, KDP.CurIBAT3.L(r1)
rlwimi r29, r28, 23, 0x00000078 rlwimi r29, r28, 23, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr dbat0u, r30 mtspr dbat0u, r30
mtspr dbat0l, r31 mtspr dbat0l, r31
stw r30, KDP.CurDBAT0.U(r1) stw r30, KDP.CurDBAT0.U(r1)
stw r31, KDP.CurDBAT0.L(r1) stw r31, KDP.CurDBAT0.L(r1)
rlwimi r29, r28, 27, 0x00000078 rlwimi r29, r28, 27, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr dbat1u, r30 mtspr dbat1u, r30
mtspr dbat1l, r31 mtspr dbat1l, r31
stw r30, KDP.CurDBAT1.U(r1) stw r30, KDP.CurDBAT1.U(r1)
stw r31, KDP.CurDBAT1.L(r1) stw r31, KDP.CurDBAT1.L(r1)
rlwimi r29, r28, 31, 0x00000078 rlwimi r29, r28, 31, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr dbat2u, r30 mtspr dbat2u, r30
mtspr dbat2l, r31 mtspr dbat2l, r31
stw r30, KDP.CurDBAT2.U(r1) stw r30, KDP.CurDBAT2.U(r1)
stw r31, KDP.CurDBAT2.L(r1) stw r31, KDP.CurDBAT2.L(r1)
rlwimi r29, r28, 3, 0x00000078 rlwimi r29, r28, 3, 0x00000078
lwz r30, KDP.BATs + BAT.U(r29) lwz r30, KDP.BATs + BAT.U(r29)
lwz r31, KDP.BATs + BAT.L(r29) lwz r31, KDP.BATs + BAT.L(r29)
mtspr dbat3u, r30 mtspr dbat3u, r30
mtspr dbat3l, r31 mtspr dbat3l, r31
stw r30, KDP.CurDBAT3.U(r1) stw r30, KDP.CurDBAT3.U(r1)
stw r31, KDP.CurDBAT3.L(r1) stw r31, KDP.CurDBAT3.L(r1)
cmpw r29, r29 cmpw r29, r29
blr blr
@601 @601
rlwimi r29, r28, 7, 25, 28 rlwimi r29, r28, 7, 25, 28
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29) lwz r31, KDP.BATs + 4(r29)
stw r30, 0x0300(r1) stw r30, 0x0300(r1)
stw r31, 0x0304(r1) stw r31, 0x0304(r1)
stw r30, 0x0320(r1) stw r30, 0x0320(r1)
stw r31, 0x0324(r1) stw r31, 0x0324(r1)
rlwimi r30, r31, 0, 25, 31 rlwimi r30, r31, 0, 25, 31
mtspr ibat0u, r30 mtspr ibat0u, r30
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
rlwimi r31, r30, 30, 26, 31 rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25 rlwimi r31, r30, 6, 25, 25
mtspr ibat0l, r31 mtspr ibat0l, r31
rlwimi r29, r28, 11, 25, 28 rlwimi r29, r28, 11, 25, 28
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29) lwz r31, KDP.BATs + 4(r29)
stw r30, 0x0308(r1) stw r30, 0x0308(r1)
stw r31, 0x030c(r1) stw r31, 0x030c(r1)
stw r30, 0x0328(r1) stw r30, 0x0328(r1)
stw r31, 0x032c(r1) stw r31, 0x032c(r1)
rlwimi r30, r31, 0, 25, 31 rlwimi r30, r31, 0, 25, 31
mtspr ibat1u, r30 mtspr ibat1u, r30
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
rlwimi r31, r30, 30, 26, 31 rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25 rlwimi r31, r30, 6, 25, 25
mtspr ibat1l, r31 mtspr ibat1l, r31
rlwimi r29, r28, 15, 25, 28 rlwimi r29, r28, 15, 25, 28
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29) lwz r31, KDP.BATs + 4(r29)
stw r30, 0x0310(r1) stw r30, 0x0310(r1)
stw r31, 0x0314(r1) stw r31, 0x0314(r1)
stw r30, 0x0330(r1) stw r30, 0x0330(r1)
stw r31, 0x0334(r1) stw r31, 0x0334(r1)
rlwimi r30, r31, 0, 25, 31 rlwimi r30, r31, 0, 25, 31
mtspr ibat2u, r30 mtspr ibat2u, r30
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
rlwimi r31, r30, 30, 26, 31 rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25 rlwimi r31, r30, 6, 25, 25
mtspr ibat2l, r31 mtspr ibat2l, r31
rlwimi r29, r28, 19, 25, 28 rlwimi r29, r28, 19, 25, 28
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
lwz r31, KDP.BATs + 4(r29) lwz r31, KDP.BATs + 4(r29)
stw r30, 0x0318(r1) stw r30, 0x0318(r1)
stw r31, 0x031c(r1) stw r31, 0x031c(r1)
stw r30, 0x0338(r1) stw r30, 0x0338(r1)
stw r31, 0x033c(r1) stw r31, 0x033c(r1)
rlwimi r30, r31, 0, 25, 31 rlwimi r30, r31, 0, 25, 31
mtspr ibat3u, r30 mtspr ibat3u, r30
lwz r30, KDP.BATs + 0(r29) lwz r30, KDP.BATs + 0(r29)
rlwimi r31, r30, 30, 26, 31 rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25 rlwimi r31, r30, 6, 25, 25
mtspr ibat3l, r31 mtspr ibat3l, r31
cmpw r29, r29 cmpw r29, r29
blr blr
######################################################################## ########################################################################
######################################################################## ########################################################################
GetPhysical ; EA r27, batPtr r29 // PA r31, EQ=Fail GetPhysical ; EA r27, batPtr r29 // PA r31, EQ=Fail
lwz r30, 0(r29) lwz r30, 0(r29)
li r28, -1 li r28, -1
rlwimi r28, r30, 15, 0, 14 rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30 xor r31, r27, r30
andc. r31, r31, r28 andc. r31, r31, r28
beq @_54 beq @_54
lwzu r30, 8(r29) lwzu r30, 8(r29)
rlwimi r28, r30, 15, 0, 14 rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30 xor r31, r27, r30
andc. r31, r31, r28 andc. r31, r31, r28
beq @_54 beq @_54
lwzu r30, 8(r29) lwzu r30, 8(r29)
rlwimi r28, r30, 15, 0, 14 rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30 xor r31, r27, r30
andc. r31, r31, r28 andc. r31, r31, r28
beq @_54 beq @_54
lwzu r30, 8(r29) lwzu r30, 8(r29)
rlwimi r28, r30, 15, 0, 14 rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30 xor r31, r27, r30
andc. r31, r31, r28 andc. r31, r31, r28
bne GetPhysicalFromHTAB bne GetPhysicalFromHTAB
@_54 @_54
andi. r31, r30, 1 andi. r31, r30, 1
rlwinm r28, r28, 0, 8, 19 rlwinm r28, r28, 0, 8, 19
lwzu r31, 4(r29) lwzu r31, 4(r29)
and r28, r27, r28 and r28, r27, r28
or r31, r31, r28 or r31, r31, r28
bnelr bnelr
GetPhysicalFromHTAB ; EA r27 // PA r31, EQ=Fail GetPhysicalFromHTAB ; EA r27 // PA r31, EQ=Fail
mfsrin r31, r27 mfsrin r31, r27
rlwinm r30, r27, 10, 26, 31 rlwinm r30, r27, 10, 26, 31
rlwimi r30, r31, 7, 1, 24 rlwimi r30, r31, 7, 1, 24
rlwinm r28, r27, 26, 10, 25 rlwinm r28, r27, 26, 10, 25
oris r30, r30, 0x8000 oris r30, r30, 0x8000
rlwinm r31, r31, 6, 7, 25 rlwinm r31, r31, 6, 7, 25
xor r28, r28, r31 xor r28, r28, r31
lwz r31, KDP.PTEGMask(r1) lwz r31, KDP.PTEGMask(r1)
lwz r29, KDP.HTABORG(r1) lwz r29, KDP.HTABORG(r1)
and r28, r28, r31 and r28, r28, r31
or. r29, r29, r28 or. r29, r29, r28
@_2c @_2c
lwz r31, 0(r29) lwz r31, 0(r29)
lwz r28, 8(r29) lwz r28, 8(r29)
cmpw cr6, r30, r31 cmpw cr6, r30, r31
lwz r31, 16(r29) lwz r31, 16(r29)
cmpw cr7, r30, r28 cmpw cr7, r30, r28
lwzu r28, 24(r29) lwzu r28, 24(r29)
bne cr6, @_50 bne cr6, @_50
@_48 @_48
lwzu r31, -0x0014(r29) lwzu r31, -0x0014(r29)
blr blr
@_50 @_50
cmpw cr6, r30, r31 cmpw cr6, r30, r31
lwzu r31, 8(r29) lwzu r31, 8(r29)
beq cr7, @_48 beq cr7, @_48
cmpw cr7, r30, r28 cmpw cr7, r30, r28
lwzu r28, 8(r29) lwzu r28, 8(r29)
beq cr6, @_48 beq cr6, @_48
cmpw cr6, r30, r31 cmpw cr6, r30, r31
lwzu r31, 8(r29) lwzu r31, 8(r29)
beq cr7, @_48 beq cr7, @_48
cmpw cr7, r30, r28 cmpw cr7, r30, r28
lwzu r28, 8(r29) lwzu r28, 8(r29)
beq cr6, @_48 beq cr6, @_48
cmpw cr6, r30, r31 cmpw cr6, r30, r31
lwzu r31, -0x000c(r29) lwzu r31, -0x000c(r29)
beqlr cr7 beqlr cr7
cmpw cr7, r30, r28 cmpw cr7, r30, r28
lwzu r31, 8(r29) lwzu r31, 8(r29)
beqlr cr6 beqlr cr6
lwzu r31, 8(r29) lwzu r31, 8(r29)
beqlr cr7 beqlr cr7
lwz r31, KDP.PTEGMask(r1) lwz r31, KDP.PTEGMask(r1)
xori r30, r30, 0x40 xori r30, r30, 0x40
andi. r28, r30, 0x40 andi. r28, r30, 0x40
addi r29, r29, -0x3c addi r29, r29, -0x3c
xor r29, r29, r31 xor r29, r29, r31
bne @_2c bne @_2c
blr blr
######################################################################## ########################################################################
######################################################################## ########################################################################
FlushTLB FlushTLB
lhz r29, KDP.ProcInfo.TransCacheTotalSize(r1) lhz r29, KDP.ProcInfo.TransCacheTotalSize(r1)
slwi r29, r29, 11 slwi r29, r29, 11
@loop @loop
subi r29, r29, 4096 subi r29, r29, 4096
cmpwi r29, 0 cmpwi r29, 0
tlbie r29 tlbie r29
bgt @loop bgt @loop
sync sync
blr blr

587
NanoKernel/NKReset.s
View File

@ -1,434 +1,469 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MRInterrupts
; MRDataStorageInt
; MRMachineCheckInt
; NKColdInts
; InstStorageInt
; MachineCheckInt
; NKExceptions
; KCallReturnFromException
; NKFloatingPt
; FPUnavailInt
; NKHotInts
; AlignmentInt
; DataStorageInt
; DecrementerIntAlt
; DecrementerIntSys
; ExternalInt0
; ExternalInt1
; ExternalInt2
; NKLegacyVM
; KCallVMDispatch
; NKMemory
; FlushTLB
; PutPTE
; SetMap
; NKSoftInts
; KCallPrioritizeInterrupts
; KCallResetSystem
; KCallRunAlternateContext
; KCallSystemCrash
; ProgramInt
; SyscallInt
; TraceInt
; NKSystemCrash
; SystemCrash
######################################################################## ########################################################################
; These registers will be used throughout ; These registers will be used throughout
rCI set r26 rCI set r26
lwz rCI, KDP.ConfigInfoPtr(r1) lwz rCI, KDP.ConfigInfoPtr(r1)
rNK set r25 rNK set r25
lwz rNK, KDP.CodeBase(r1) lwz rNK, KDP.CodeBase(r1)
rPgMap set r18 rPgMap set r18
lwz rPgMap, KDP.PageMapStartPtr(r1) lwz rPgMap, KDP.PageMapStartPtr(r1)
rXER set r17 rXER set r17
mfxer rXER mfxer rXER
######################################################################## ########################################################################
InitVectorTables InitVectorTables
; System/Alternate Context tables ; System/Alternate Context tables
_kaddr r23, rNK, SystemCrash _kaddr r23, rNK, SystemCrash
addi r8, r1, KDP.VecTblSystem addi r8, r1, KDP.VecTblSystem
li r22, 3 * VecTbl.Size li r22, 3 * VecTbl.Size
@vectab_initnext_segment @vectab_initnext_segment
subic. r22, r22, 4 subic. r22, r22, 4
stwx r23, r8, r22 stwx r23, r8, r22
bne @vectab_initnext_segment bne @vectab_initnext_segment
rSys set r9 ; to clarify which table is which rSys set r9 ; to clarify which table is which
rAlt set r8 rAlt set r8
addi rSys, r1, KDP.VecTblSystem addi rSys, r1, KDP.VecTblSystem
mtsprg 3, rSys mtsprg 3, rSys
addi rAlt, r1, KDP.VecTblAlternate addi rAlt, r1, KDP.VecTblAlternate
_kaddr r23, rNK, SystemCrash _kaddr r23, rNK, SystemCrash
stw r23, VecTbl.SystemReset(rSys) stw r23, VecTbl.SystemReset(rSys)
stw r23, VecTbl.SystemReset(rAlt) stw r23, VecTbl.SystemReset(rAlt)
_kaddr r23, rNK, MachineCheckInt _kaddr r23, rNK, MachineCheckInt
stw r23, VecTbl.MachineCheck(rSys) stw r23, VecTbl.MachineCheck(rSys)
stw r23, VecTbl.MachineCheck(rAlt) stw r23, VecTbl.MachineCheck(rAlt)
_kaddr r23, rNK, DataStorageInt _kaddr r23, rNK, DataStorageInt
stw r23, VecTbl.DSI(rSys) stw r23, VecTbl.DSI(rSys)
stw r23, VecTbl.DSI(rAlt) stw r23, VecTbl.DSI(rAlt)
_kaddr r23, rNK, InstStorageInt _kaddr r23, rNK, InstStorageInt
stw r23, VecTbl.ISI(rSys) stw r23, VecTbl.ISI(rSys)
stw r23, VecTbl.ISI(rAlt) stw r23, VecTbl.ISI(rAlt)
lbz r22, NKConfigurationInfo.InterruptHandlerKind(rCI) lbz r22, NKConfigurationInfo.InterruptHandlerKind(rCI)
cmpwi r22, 0 cmpwi r22, 0
_kaddr r23, rNK, ExternalInt0 _kaddr r23, rNK, ExternalInt0
beq @chosenIntHandler beq @chosenIntHandler
cmpwi r22, 1 cmpwi r22, 1
_kaddr r23, rNK, ExternalInt1 _kaddr r23, rNK, ExternalInt1
beq @chosenIntHandler beq @chosenIntHandler
cmpwi r22, 2 cmpwi r22, 2
_kaddr r23, rNK, ExternalInt2 _kaddr r23, rNK, ExternalInt2
beq @chosenIntHandler beq @chosenIntHandler
@chosenIntHandler @chosenIntHandler
stw r23, VecTbl.External(rSys) stw r23, VecTbl.External(rSys)
_kaddr r23, rNK, ProgramInt _kaddr r23, rNK, ProgramInt
stw r23, VecTbl.External(rAlt) stw r23, VecTbl.External(rAlt)
_kaddr r23, rNK, AlignmentInt _kaddr r23, rNK, AlignmentInt
stw r23, VecTbl.Alignment(rSys) stw r23, VecTbl.Alignment(rSys)
stw r23, VecTbl.Alignment(rAlt) stw r23, VecTbl.Alignment(rAlt)
_kaddr r23, rNK, ProgramInt _kaddr r23, rNK, ProgramInt
stw r23, VecTbl.Program(rSys) stw r23, VecTbl.Program(rSys)
stw r23, VecTbl.Program(rAlt) stw r23, VecTbl.Program(rAlt)
_kaddr r23, rNK, FPUnavailInt _kaddr r23, rNK, FPUnavailInt
stw r23, VecTbl.FPUnavail(rSys) stw r23, VecTbl.FPUnavail(rSys)
stw r23, VecTbl.FPUnavail(rAlt) stw r23, VecTbl.FPUnavail(rAlt)
_kaddr r23, rNK, DecrementerIntSys _kaddr r23, rNK, DecrementerIntSys
stw r23, VecTbl.Decrementer(rSys) stw r23, VecTbl.Decrementer(rSys)
_kaddr r23, rNK, DecrementerIntAlt _kaddr r23, rNK, DecrementerIntAlt
stw r23, VecTbl.Decrementer(rAlt) stw r23, VecTbl.Decrementer(rAlt)
_kaddr r23, rNK, SyscallInt _kaddr r23, rNK, SyscallInt
stw r23, VecTbl.Syscall(rSys) stw r23, VecTbl.Syscall(rSys)
stw r23, VecTbl.Syscall(rAlt) stw r23, VecTbl.Syscall(rAlt)
_kaddr r23, rNK, TraceInt _kaddr r23, rNK, TraceInt
stw r23, VecTbl.Trace(rSys) stw r23, VecTbl.Trace(rSys)
stw r23, VecTbl.Trace(rAlt) stw r23, VecTbl.Trace(rAlt)
stw r23, VecTbl.OtherTrace(rSys) stw r23, VecTbl.OtherTrace(rSys)
stw r23, VecTbl.OtherTrace(rAlt) stw r23, VecTbl.OtherTrace(rAlt)
; MemRetry vector table ; MemRetry vector table
addi r8, r1, KDP.VecTblMemRetry addi r8, r1, KDP.VecTblMemRetry
_kaddr r23, rNK, MRMachineCheckInt _kaddr r23, rNK, MRMachineCheckInt
stw r23, VecTbl.MachineCheck(r8) stw r23, VecTbl.MachineCheck(r8)
_kaddr r23, rNK, MRDataStorageInt _kaddr r23, rNK, MRDataStorageInt
stw r23, VecTbl.DSI(r8) stw r23, VecTbl.DSI(r8)
######################################################################## ########################################################################
; Fill the KCallTbl, the ProgramInt interface to the NanoKernel ; Fill the KCallTbl, the ProgramInt interface to the NanoKernel
InitKCalls InitKCalls
_kaddr r23, rNK, KCallSystemCrash ; Uninited call -> crash _kaddr r23, rNK, KCallSystemCrash ; Uninited call -> crash
addi r8, r1, KDP.KCallTbl addi r8, r1, KDP.KCallTbl
li r22, KCallTbl.Size li r22, KCallTbl.Size
@loop @loop
subic. r22, r22, 4 subic. r22, r22, 4
stwx r23, r8, r22 stwx r23, r8, r22
bne @loop bne @loop
_kaddr r23, rNK, KCallReturnFromException _kaddr r23, rNK, KCallReturnFromException
stw r23, KCallTbl.ReturnFromException(r8) stw r23, KCallTbl.ReturnFromException(r8)
_kaddr r23, rNK, KCallRunAlternateContext _kaddr r23, rNK, KCallRunAlternateContext
stw r23, KCallTbl.RunAlternateContext(r8) stw r23, KCallTbl.RunAlternateContext(r8)
_kaddr r23, rNK, KCallResetSystem _kaddr r23, rNK, KCallResetSystem
stw r23, KCallTbl.ResetSystem(r8) stw r23, KCallTbl.ResetSystem(r8)
_kaddr r23, rNK, KCallVMDispatch _kaddr r23, rNK, KCallVMDispatch
stw r23, KCallTbl.VMDispatch(r8) stw r23, KCallTbl.VMDispatch(r8)
_kaddr r23, rNK, KCallPrioritizeInterrupts _kaddr r23, rNK, KCallPrioritizeInterrupts
stw r23, KCallTbl.PrioritizeInterrupts(r8) stw r23, KCallTbl.PrioritizeInterrupts(r8)
_kaddr r23, rNK, KCallSystemCrash _kaddr r23, rNK, KCallSystemCrash
stw r23, KCallTbl.SystemCrash(r8) stw r23, KCallTbl.SystemCrash(r8)
######################################################################## ########################################################################
; Init the NCB Pointer Cache ; Init the NCB Pointer Cache
_InvalNCBPointerCache scratch=r23 _InvalNCBPointerCache scratch=r23
######################################################################## ########################################################################
; Put HTABORG and PTEGMask in KDP, and zero out the last PTEG ; Put HTABORG and PTEGMask in KDP, and zero out the last PTEG
InitHTAB InitHTAB
mfspr r8, sdr1 mfspr r8, sdr1
rlwinm r22, r8, 16, 7, 15 ; Get settable HTABMASK bits rlwinm r22, r8, 16, 7, 15 ; Get settable HTABMASK bits
rlwinm r8, r8, 0, 0, 15 ; and HTABORG rlwinm r8, r8, 0, 0, 15 ; and HTABORG
ori r22, r22, (-64) & 0xffff; "PTEGMask" from upper half of HTABMASK ori r22, r22, (-64) & 0xffff; "PTEGMask" from upper half of HTABMASK
stw r8, KDP.HTABORG(r1) ; Save stw r8, KDP.HTABORG(r1) ; Save
stw r22, KDP.PTEGMask(r1) stw r22, KDP.PTEGMask(r1)
li r23, 0 ; Zero out the last PTEG in the HTAB li r23, 0 ; Zero out the last PTEG in the HTAB
addi r22, r22, 64 addi r22, r22, 64
@next_segment @next_segment
subic. r22, r22, 4 subic. r22, r22, 4
stwx r23, r8, r22 stwx r23, r8, r22
bgt @next_segment bgt @next_segment
@skip_zeroing_pteg @skip_zeroing_pteg
bl FlushTLB ; Flush the TLB after touching the HTAB bl FlushTLB ; Flush the TLB after touching the HTAB
######################################################################## ########################################################################
; Get a copy of the PageMap (and the SegMaps required to interpret it) ; Get a copy of the PageMap (and the SegMaps required to interpret it)
; Each entry in the PageMap specifies a contiguous part of the MacOS ; Each entry in the PageMap specifies a contiguous part of the MacOS
; address space (or it has a special value). The four SegMaps (supervisor, ; address space (or it has a special value). The four SegMaps (supervisor,
; user, CPU, overlay) contain pointers that tell us which entries belong ; user, CPU, overlay) contain pointers that tell us which entries belong
; in which 256 MB "segments". ; in which 256 MB "segments".
CopyPageMap CopyPageMap
; r9 = PageMap ptr, r22 = PageMap size ; r9 = PageMap ptr, r22 = PageMap size
lwz r9, NKConfigurationInfo.PageMapInitOffset(rCI) lwz r9, NKConfigurationInfo.PageMapInitOffset(rCI)
lwz r22, NKConfigurationInfo.PageMapInitSize(rCI) lwz r22, NKConfigurationInfo.PageMapInitSize(rCI)
add r9, r9, rCI add r9, r9, rCI
@copynext_segment_pagemap @copynext_segment_pagemap
subi r22, r22, 4 ; load a word from the CI pagemap (top first) subi r22, r22, 4 ; load a word from the CI pagemap (top first)
lwzx r21, r9, r22 lwzx r21, r9, r22
andi. r23, r21, PME.DaddyFlag | PME.PhysicalIsRelativeFlag andi. r23, r21, PME.DaddyFlag | PME.PhysicalIsRelativeFlag
cmpwi r23, PME.PhysicalIsRelativeFlag cmpwi r23, PME.PhysicalIsRelativeFlag
bne @physical_address_not_relative_to_config_info bne @physical_address_not_relative_to_config_info
; if the physical address of the area is relative to the ConfigInfo struct: ; if the physical address of the area is relative to the ConfigInfo struct:
rlwinm r21, r21, 0, ~PME.PhysicalIsRelativeFlag rlwinm r21, r21, 0, ~PME.PhysicalIsRelativeFlag
add r21, r21, rCI add r21, r21, rCI
@physical_address_not_relative_to_config_info @physical_address_not_relative_to_config_info
stwx r21, rPgMap, r22 ; save in the KDP pagemap stwx r21, rPgMap, r22 ; save in the KDP pagemap
subic. r22, r22, 4 subic. r22, r22, 4
lwzx r20, r9, r22 ; load another word, but no be cray lwzx r20, r9, r22 ; load another word, but no be cray
stwx r20, rPgMap, r22 ; just save it in KDP stwx r20, rPgMap, r22 ; just save it in KDP
bgt @copynext_segment_pagemap bgt @copynext_segment_pagemap
@skip_copying_pagemap @skip_copying_pagemap
; Edit three entries in the PageMap that the kernel "owns" ; Edit three entries in the PageMap that the kernel "owns"
lwz r8, NKConfigurationInfo.PageMapIRPOffset(rCI) lwz r8, NKConfigurationInfo.PageMapIRPOffset(rCI)
add r8, rPgMap, r8 add r8, rPgMap, r8
lwz r23, PME.PBaseAndFlags(r8) lwz r23, PME.PBaseAndFlags(r8)
rlwimi r23, r1, 0, 0xFFFFF000 rlwimi r23, r1, 0, 0xFFFFF000
stw r23, PME.PBaseAndFlags(r8) stw r23, PME.PBaseAndFlags(r8)
lwz r8, NKConfigurationInfo.PageMapKDPOffset(rCI) lwz r8, NKConfigurationInfo.PageMapKDPOffset(rCI)
add r8, rPgMap, r8 add r8, rPgMap, r8
lwz r23, PME.PBaseAndFlags(r8) lwz r23, PME.PBaseAndFlags(r8)
rlwimi r23, r1, 0, 0xFFFFF000 rlwimi r23, r1, 0, 0xFFFFF000
stw r23, PME.PBaseAndFlags(r8) stw r23, PME.PBaseAndFlags(r8)
lwz r19, KDP.EDPPtr(r1) lwz r19, KDP.EDPPtr(r1)
lwz r8, NKConfigurationInfo.PageMapEDPOffset(rCI) lwz r8, NKConfigurationInfo.PageMapEDPOffset(rCI)
add r8, rPgMap, r8 add r8, rPgMap, r8
lwz r23, PME.PBaseAndFlags(r8) lwz r23, PME.PBaseAndFlags(r8)
rlwimi r23, r19, 0, 0xFFFFF000 rlwimi r23, r19, 0, 0xFFFFF000
stw r23, PME.PBaseAndFlags(r8) stw r23, PME.PBaseAndFlags(r8)
; Copy the SegMap ; Copy the SegMap
addi r9, rCI, NKConfigurationInfo.SegMaps - 4 addi r9, rCI, NKConfigurationInfo.SegMaps - 4
addi r8, r1, KDP.SegMaps - 4 addi r8, r1, KDP.SegMaps - 4
li r22, 4*16*8 ; 4 maps * 16 segments * (ptr+flags=8b) li r22, 4*16*8 ; 4 maps * 16 segments * (ptr+flags=8b)
@segmap_copynext_segment @segmap_copynext_segment
lwzu r23, 4(r9) lwzu r23, 4(r9)
subic. r22, r22, 8 subic. r22, r22, 8
add r23, rPgMap, r23 ; even-indexed words are PMDT offsets in PageMap add r23, rPgMap, r23 ; even-indexed words are PMDT offsets in PageMap
stwu r23, 4(r8) stwu r23, 4(r8)
lwzu r23, 4(r9) lwzu r23, 4(r9)
stwu r23, 4(r8) stwu r23, 4(r8)
bgt @segmap_copynext_segment bgt @segmap_copynext_segment
######################################################################## ########################################################################
; Copy "BATRangeInit" array ; Copy "BATRangeInit" array
CopyBATRangeInit CopyBATRangeInit
addi r9, rCI, NKConfigurationInfo.BATRangeInit - 4 addi r9, rCI, NKConfigurationInfo.BATRangeInit - 4
addi r8, r1, KDP.BATs - 4 addi r8, r1, KDP.BATs - 4
li r22, 4*4*8 ; 4 maps * 4 BATs * (UBAT+LBAT=8b) li r22, 4*4*8 ; 4 maps * 4 BATs * (UBAT+LBAT=8b)
@bat_copynext_segment @bat_copynext_segment
lwzu r20, 4(r9) ; grab UBAT lwzu r20, 4(r9) ; grab UBAT
lwzu r21, 4(r9) ; grab LBAT lwzu r21, 4(r9) ; grab LBAT
stwu r20, 4(r8) ; store UBAT stwu r20, 4(r8) ; store UBAT
_clear r23, r21, 22 ; if LBAT[22] (reserved) is set: _clear r23, r21, 22 ; if LBAT[22] (reserved) is set:
cmpw r21, r23 cmpw r21, r23
beq @bitnotset beq @bitnotset
add r21, r23, rCI ; then LBAT[BRPN] is relative to ConfigInfo struct add r21, r23, rCI ; then LBAT[BRPN] is relative to ConfigInfo struct
@bitnotset @bitnotset
subic. r22, r22, 8 subic. r22, r22, 8
stwu r21, 4(r8) ; store LBAT stwu r21, 4(r8) ; store LBAT
bgt @bat_copynext_segment bgt @bat_copynext_segment
######################################################################## ########################################################################
; Save some ptrs that allow us to enable Overlay mode, etc ; Save some ptrs that allow us to enable Overlay mode, etc
addi r23, r1, KDP.SegMap32SupInit addi r23, r1, KDP.SegMap32SupInit
stw r23, KDP.SupervisorMap.SegMapPtr(r1) stw r23, KDP.SupervisorMap.SegMapPtr(r1)
lwz r23, NKConfigurationInfo.BatMap32SupInit(rCI) lwz r23, NKConfigurationInfo.BatMap32SupInit(rCI)
stw r23, KDP.SupervisorMap.BatMap(r1) stw r23, KDP.SupervisorMap.BatMap(r1)
addi r23, r1, KDP.SegMap32UsrInit addi r23, r1, KDP.SegMap32UsrInit
stw r23, KDP.UserMap.SegMapPtr(r1) stw r23, KDP.UserMap.SegMapPtr(r1)
lwz r23, NKConfigurationInfo.BatMap32UsrInit(rCI) lwz r23, NKConfigurationInfo.BatMap32UsrInit(rCI)
stw r23, KDP.UserMap.BatMap(r1) stw r23, KDP.UserMap.BatMap(r1)
addi r23, r1, KDP.SegMap32CPUInit addi r23, r1, KDP.SegMap32CPUInit
stw r23, KDP.CpuMap.SegMapPtr(r1) stw r23, KDP.CpuMap.SegMapPtr(r1)
lwz r23, NKConfigurationInfo.BatMap32CPUInit(rCI) lwz r23, NKConfigurationInfo.BatMap32CPUInit(rCI)
stw r23, KDP.CpuMap.BatMap(r1) stw r23, KDP.CpuMap.BatMap(r1)
addi r23, r1, KDP.SegMap32OvlInit addi r23, r1, KDP.SegMap32OvlInit
stw r23, KDP.OverlayMap.SegMapPtr(r1) stw r23, KDP.OverlayMap.SegMapPtr(r1)
lwz r23, NKConfigurationInfo.BatMap32OvlInit(rCI) lwz r23, NKConfigurationInfo.BatMap32OvlInit(rCI)
stw r23, KDP.OverlayMap.BatMap(r1) stw r23, KDP.OverlayMap.BatMap(r1)
######################################################################## ########################################################################
; Create a PageList for the Primary Address Range ; Create a PageList for the Primary Address Range
; Usable physical pages are: ; Usable physical pages are:
; Inside a RAM bank, and ; Inside a RAM bank, and
; NOT inside the kernel's reserved physical memory ; NOT inside the kernel's reserved physical memory
; By 'draft PTE', I mean these parts of the second word of a PTE: ; By 'draft PTE', I mean these parts of the second word of a PTE:
; physical page number (base & 0xfffff000) ; physical page number (base & 0xfffff000)
; WIMG bits (from oddly formatted ConfigInfo.PageAttributeInit) ; WIMG bits (from oddly formatted ConfigInfo.PageAttributeInit)
; bottom PP bit always set ; bottom PP bit always set
; And all this goes at the bottom of the kernel reserved area. ; And all this goes at the bottom of the kernel reserved area.
; Leave ptr to kernel reserved area in r21 ; Leave ptr to kernel reserved area in r21
; Leave ptr to topmost entry in r29. ; Leave ptr to topmost entry in r29.
CreatePageList CreatePageList
lwz r21, KDP.KernelMemoryBase(r1) ; "KernelMemory" is forbidden lwz r21, KDP.KernelMemoryBase(r1) ; "KernelMemory" is forbidden
lwz r20, KDP.KernelMemoryEnd(r1) lwz r20, KDP.KernelMemoryEnd(r1)
subi r29, r21, 4 ; ptr to last added entry subi r29, r21, 4 ; ptr to last added entry
addi r19, r1, KDP.SysInfo.Bank0Start - 8 addi r19, r1, KDP.SysInfo.Bank0Start - 8
lwz r23, KDP.PageAttributeInit(r1) ; default WIMG/PP settings in PTEs lwz r23, KDP.PageAttributeInit(r1) ; default WIMG/PP settings in PTEs
; Pull WIMG bits out of PageAttributeInit ; Pull WIMG bits out of PageAttributeInit
li r30, 1 li r30, 1
rlwimi r30, r23, 1, 25, 25 rlwimi r30, r23, 1, 25, 25
rlwimi r30, r23, 31, 26, 26 rlwimi r30, r23, 31, 26, 26
xori r30, r30, 0x20 xori r30, r30, 0x20
rlwimi r30, r23, 29, 27, 27 rlwimi r30, r23, 29, 27, 27
rlwimi r30, r23, 27, 28, 28 rlwimi r30, r23, 27, 28, 28
li r23, NKSystemInfo.MaxBanks li r23, NKSystemInfo.MaxBanks
@nextbank @nextbank
subic. r23, r23, 1 subic. r23, r23, 1
blt @done blt @done
lwzu r31, 8(r19) ; bank start address lwzu r31, 8(r19) ; bank start address
lwz r22, 4(r19) ; bank size lwz r22, 4(r19) ; bank size
or r31, r31, r30 ; looks a lot like the second word of a PTE or r31, r31, r30 ; looks a lot like the second word of a PTE
@nextpage @nextpage
cmplwi r22, 4096 cmplwi r22, 4096
cmplw cr6, r31, r21 cmplw cr6, r31, r21
cmplw cr7, r31, r20 cmplw cr7, r31, r20
subi r22, r22, 4096 subi r22, r22, 4096
blt @nextbank blt @nextbank
; Check that this page is outside the kernel's reserved area ; Check that this page is outside the kernel's reserved area
blt cr6, @below_reserved blt cr6, @below_reserved
blt cr7, @in_reserved blt cr7, @in_reserved
@below_reserved @below_reserved
stwu r31, 4(r29) ; write that part-PTE at the base of kernel memory stwu r31, 4(r29) ; write that part-PTE at the base of kernel memory
@in_reserved @in_reserved
addi r31, r31, 4096 addi r31, r31, 4096
b @nextpage b @nextpage
@done @done
######################################################################## ########################################################################
; In the PageMap, create a Primary Address Range matching the size of PageList ; In the PageMap, create a Primary Address Range matching the size of PageList
; For every segment that contains part of the PAR, the first PME will be rewritten ; For every segment that contains part of the PAR, the first PME will be rewritten
; Going in, r21/r29 point to first/last element of PageList ; Going in, r21/r29 point to first/last element of PageList
CreatePARInPageMap CreatePARInPageMap
; r19 = size of RAM represented in PageList ("Usable" and initial "Logical" RAM) ; r19 = size of RAM represented in PageList ("Usable" and initial "Logical" RAM)
; r22 = number of 4096b pages, minus one page (counter) ; r22 = number of 4096b pages, minus one page (counter)
subf r22, r21, r29 subf r22, r21, r29
li r30, 0 li r30, 0
addi r19, r22, 4 addi r19, r22, 4
slwi r19, r19, 10 slwi r19, r19, 10
ori r30, r30, 0xffff ori r30, r30, 0xffff
stw r19, KDP.SysInfo.UsableMemorySize(r1) stw r19, KDP.SysInfo.UsableMemorySize(r1)
srwi r22, r22, 2 srwi r22, r22, 2
stw r19, KDP.SysInfo.LogicalMemorySize(r1) stw r19, KDP.SysInfo.LogicalMemorySize(r1)
; convert r19 to pages, and save in some places ; convert r19 to pages, and save in some places
srwi r19, r19, 12 srwi r19, r19, 12
stw r19, KDP.VMLogicalPages(r1) stw r19, KDP.VMLogicalPages(r1)
stw r19, KDP.TotalPhysicalPages(r1) stw r19, KDP.TotalPhysicalPages(r1)
addi r29, r1, KDP.PARPerSegmentPLEPtrs - 4 ; where to save per-segment PLE ptr addi r29, r1, KDP.PARPerSegmentPLEPtrs - 4 ; where to save per-segment PLE ptr
addi r19, r1, KDP.SegMap32SupInit - 8 ; which part of PageMap to update addi r19, r1, KDP.SegMap32SupInit - 8 ; which part of PageMap to update
stw r21, KDP.PARPageListPtr(r1) stw r21, KDP.PARPageListPtr(r1)
@next_segment @next_segment
cmplwi r22, 0xffff ; continue (bgt) while there are still pages left cmplwi r22, 0xffff ; continue (bgt) while there are still pages left
; Rewrite the first PME in this segment ; Rewrite the first PME in this segment
lwzu r8, 8(r19) ; find PME using SegMap32SupInit lwzu r8, 8(r19) ; find PME using SegMap32SupInit
rotlwi r31, r21, 10 rotlwi r31, r21, 10
ori r31, r31, 0xC00 ori r31, r31, 0xC00
stw r30, 0(r8) ; LBase = 0, PageCount = 0xFFFF stw r30, 0(r8) ; LBase = 0, PageCount = 0xFFFF
stw r31, 4(r8) ; PBase = PLE ptr, Flags = DaddyFlag + CountingFlag stw r31, 4(r8) ; PBase = PLE ptr, Flags = DaddyFlag + CountingFlag
stwu r21, 4(r29) ; point PARPerSegmentPLEPtrs to segments's first PLE stwu r21, 4(r29) ; point PARPerSegmentPLEPtrs to segments's first PLE
addis r21, r21, 4 ; increment pointer into PLE (64k pages/segment * 4b/PLE) addis r21, r21, 4 ; increment pointer into PLE (64k pages/segment * 4b/PLE)
subis r22, r22, 1 ; decrement number of pending pages (64k pages/segment) subis r22, r22, 1 ; decrement number of pending pages (64k pages/segment)
bgt @next_segment bgt @next_segment
; Reduce the number of pages in the last segment ; Reduce the number of pages in the last segment
sth r22, PME.PageCount(r8) sth r22, PME.PageCount(r8)
######################################################################## ########################################################################
; Enable the ROM Overlay ; Enable the ROM Overlay
addi r29, r1, KDP.OverlayMap addi r29, r1, KDP.OverlayMap
bl SetMap bl SetMap
######################################################################## ########################################################################
; Make sure some important areas of RAM are in the HTAB ; Make sure some important areas of RAM are in the HTAB
lwz r27, KDP.ConfigInfoPtr(r1) lwz r27, KDP.ConfigInfoPtr(r1)
lwz r27, NKConfigurationInfo.LA_InterruptCtl(r27) lwz r27, NKConfigurationInfo.LA_InterruptCtl(r27)
bl PutPTE bl PutPTE
lwz r27, KDP.ConfigInfoPtr(r1) lwz r27, KDP.ConfigInfoPtr(r1)
lwz r27, NKConfigurationInfo.LA_KernelData(r27) lwz r27, NKConfigurationInfo.LA_KernelData(r27)
bl PutPTE bl PutPTE
lwz r27, KDP.ConfigInfoPtr(r1) lwz r27, KDP.ConfigInfoPtr(r1)
lwz r27, NKConfigurationInfo.LA_EmulatorData(r27) lwz r27, NKConfigurationInfo.LA_EmulatorData(r27)
bl PutPTE bl PutPTE
######################################################################## ########################################################################
; Restore the fixedpt exception register (clobbered by addic) ; Restore the fixedpt exception register (clobbered by addic)
mtxer rXER mtxer rXER

649
NanoKernel/NKSoftInts.s
View File

@ -1,437 +1,460 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; IMPORTS:
; MROptabCode
; MRSecDone
; NKExceptions
; Exception
; KCallReturnFromExceptionFastPath
; LoadInterruptRegisters
; ReturnFromInt
; SwitchContext
; NKHotInts
; EmulateDataAccess
; NKMemory
; GetPhysical
; NKSystemCrash
; SystemCrash
; EXPORTS:
; KCallPrioritizeInterrupts (=> NKReset)
; KCallResetSystem (=> NKReset)
; KCallRunAlternateContext (=> NKReset)
; KCallSystemCrash (=> NKReset)
; ProgramInt (=> NKReset)
; SyscallInt (=> NKReset)
; TraceInt (=> NKReset)
######################################################################## ########################################################################
IllegalInstruction IllegalInstruction
mfmsr r9 mfmsr r9
_set r8, r9, bitMsrDR _set r8, r9, bitMsrDR
mtmsr r8 mtmsr r8
lwz r8, 0(r10) lwz r8, 0(r10)
mtmsr r9 mtmsr r9
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r2, KDP.r2(r1) stw r2, KDP.r2(r1)
stw r3, KDP.r3(r1) stw r3, KDP.r3(r1)
stw r4, KDP.r4(r1) stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1) stw r5, KDP.r5(r1)
lwz r9, CB.r7+4(r6) lwz r9, CB.r7+4(r6)
stw r9, KDP.r7(r1) stw r9, KDP.r7(r1)
lwz r9, CB.r8+4(r6) lwz r9, CB.r8+4(r6)
stw r9, KDP.r8(r1) stw r9, KDP.r8(r1)
lwz r9, CB.r9+4(r6) lwz r9, CB.r9+4(r6)
stw r9, KDP.r9(r1) stw r9, KDP.r9(r1)
lwz r9, CB.r10+4(r6) lwz r9, CB.r10+4(r6)
stw r9, KDP.r10(r1) stw r9, KDP.r10(r1)
lwz r9, CB.r11+4(r6) lwz r9, CB.r11+4(r6)
stw r9, KDP.r11(r1) stw r9, KDP.r11(r1)
lwz r9, CB.r12+4(r6) lwz r9, CB.r12+4(r6)
stw r9, KDP.r12(r1) stw r9, KDP.r12(r1)
lwz r9, CB.r13+4(r6) lwz r9, CB.r13+4(r6)
stw r9, KDP.r13(r1) stw r9, KDP.r13(r1)
stmw r14, KDP.r14(r1) stmw r14, KDP.r14(r1)
rlwinm r9, r8, 6, 15, 31 rlwinm r9, r8, 6, 15, 31
cmplwi r9, 0xB99F cmplwi r9, 0xB99F
beq @MFTB beq @MFTB
rlwinm r9, r8, 17, 15, 20 rlwinm r9, r8, 17, 15, 20
insrwi r9, r8, 11, 21 insrwi r9, r8, 11, 21
cmplwi r9, 0xFFAE cmplwi r9, 0xFFAE
beq @STFIWX beq @STFIWX
@FAIL @FAIL
li r8, ecInvalidInstr li r8, ecInvalidInstr
b Exception b Exception
@MFTB @MFTB
extrwi r9, r8, 10, 11 ; r9 = tbr field extrwi r9, r8, 10, 11 ; r9 = tbr field
cmplwi cr7, r9, 0x188 ; TBL=268, mangled cmplwi cr7, r9, 0x188 ; TBL=268, mangled
cmplwi cr6, r9, 0x1A8 ; TBU=269, mangled cmplwi cr6, r9, 0x1A8 ; TBU=269, mangled
cror 15, cr6_eq, cr7_eq cror 15, cr6_eq, cr7_eq
bc BO_IF_NOT, 15, @FAIL bc BO_IF_NOT, 15, @FAIL
@retry_rtc @retry_rtc
mfspr r20, rtcu mfspr r20, rtcu
mfspr r21, rtcl mfspr r21, rtcl
mfspr r23, rtcu mfspr r23, rtcu
xor. r23, r23, r20 xor. r23, r23, r20
lis r23, 1000000000 >> 16 lis r23, 1000000000 >> 16
rlwinm r28, r8, 13, 25, 29 ; r28 = dest register number * 4 rlwinm r28, r8, 13, 25, 29 ; r28 = dest register number * 4
ori r23, r23, 1000000000 & 0xFFFF ori r23, r23, 1000000000 & 0xFFFF
bne @retry_rtc bne @retry_rtc
mullw r8, r20, r23 mullw r8, r20, r23
mulhwu r20, r20, r23 mulhwu r20, r20, r23
mfxer r23 mfxer r23
addc r21, r21, r8 addc r21, r21, r8
addze r20, r20 addze r20, r20
mtxer r23 mtxer r23
lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1) lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
rlwimi r7, r7, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE rlwimi r7, r7, 27, 26, 26 ; ContextFlagTraceWhenDone = MsrSE
addi r23, r23, 1 addi r23, r23, 1
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1) stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
stwx r21, r1, r28 ; save register into EWA stwx r21, r1, r28 ; save register into EWA
mr r16, r7 mr r16, r7
beq cr7, MRSecDone ; TBL beq cr7, MRSecDone ; TBL
stwx r20, r1, r28 stwx r20, r1, r28
b MRSecDone ; TBU b MRSecDone ; TBU
@STFIWX @STFIWX
lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1) lwz r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
mr r27, r8 mr r27, r8
addi r23, r23, 1 addi r23, r23, 1
stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1) stw r23, KDP.NKInfo.EmulatedUnimpInstCount(r1)
mfmsr r14 mfmsr r14
_set r15, r14, bitMsrDR _set r15, r14, bitMsrDR
b EmulateDataAccess b EmulateDataAccess
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
KCallRunAlternateContext KCallRunAlternateContext
; ARG ContextBlock *r3, flags r4 ; ARG ContextBlock *r3, flags r4
; We accept a logical NCB ptr but the kernel needs a physical one. ; We accept a logical NCB ptr but the kernel needs a physical one.
; So we keep a four-entry cache in KDP, mapping logical NCB ptrs ; So we keep a four-entry cache in KDP, mapping logical NCB ptrs
; to physical ones. Never seen multiple contexts used before though. ; to physical ones. Never seen multiple contexts used before though.
and. r8, r4, r13 and. r8, r4, r13
lwz r9, KDP.NCBCacheLA0(r1) lwz r9, KDP.NCBCacheLA0(r1)
rlwinm r8, r3, 0, 0, 25 rlwinm r8, r3, 0, 0, 25
cmpw cr1, r8, r9 cmpw cr1, r8, r9
bne ReturnFromInt bne ReturnFromInt
lwz r9, KDP.NCBCachePA0(r1) lwz r9, KDP.NCBCachePA0(r1)
bne cr1, @search_cache bne cr1, @search_cache
@found_physical_in_cache ; can come here from below after a more thorough search @found_physical_in_cache ; can come here from below after a more thorough search
addi r8, r1, KDP.VecTblAlternate ; the only use of this vector table? addi r8, r1, KDP.VecTblAlternate ; the only use of this vector table?
mtsprg 3, r8 mtsprg 3, r8
lwz r8, KDP.EmuKCallTblPtrLogical(r1) lwz r8, KDP.EmuKCallTblPtrLogical(r1)
mtcrf crMaskFlags, r7 mtcrf crMaskFlags, r7
clrlwi r7, r7, 8 clrlwi r7, r7, 8
stw r8, CB.IntraState.HandlerReturn+4(r9) stw r8, CB.IntraState.HandlerReturn+4(r9)
stw r9, KDP.ContextPtr(r1) stw r9, KDP.ContextPtr(r1)
b SwitchContext ; OldCB *r6, NewCB *r9 b SwitchContext ; OldCB *r6, NewCB *r9
@search_cache @search_cache
lwz r9, KDP.NCBCacheLA1(r1) lwz r9, KDP.NCBCacheLA1(r1)
cmpw cr1, r8, r9 cmpw cr1, r8, r9
beq cr1, @found_in_slot_1 beq cr1, @found_in_slot_1
lwz r9, KDP.NCBCacheLA2(r1) lwz r9, KDP.NCBCacheLA2(r1)
cmpw cr1, r8, r9 cmpw cr1, r8, r9
beq cr1, @found_in_slot_2 beq cr1, @found_in_slot_2
lwz r9, KDP.NCBCacheLA3(r1) lwz r9, KDP.NCBCacheLA3(r1)
cmpw cr1, r8, r9 cmpw cr1, r8, r9
beq cr1, @found_in_slot_3 beq cr1, @found_in_slot_3
; No luck with the cache ; No luck with the cache
stmw r14, KDP.r14(r1) stmw r14, KDP.r14(r1)
cmpw cr1, r8, r6 cmpw cr1, r8, r6
beq cr1, @fail beq cr1, @fail
mr r27, r8 mr r27, r8
addi r29, r1, KDP.BATs + 0xa0 addi r29, r1, KDP.BATs + 0xa0
bl GetPhysical bl GetPhysical
clrlwi r23, r8, 20 clrlwi r23, r8, 20
beq @fail beq @fail
cmplwi r23, 0x0d00 cmplwi r23, 0x0d00
mr r9, r8 mr r9, r8
mr r8, r31 mr r8, r31
ble @not_straddling_pages ble @not_straddling_pages
addi r27, r27, 0x1000 addi r27, r27, 0x1000
addi r29, r1, KDP.BATs + 0xa0 addi r29, r1, KDP.BATs + 0xa0
bl GetPhysical bl GetPhysical
beq @fail beq @fail
subi r31, r31, 0x1000 subi r31, r31, 0x1000
xor r23, r8, r31 xor r23, r8, r31
rlwinm. r23, r23, 0, 25, 22 rlwinm. r23, r23, 0, 25, 22
bne @fail ; because physical pages are discontiguous bne @fail ; because physical pages are discontiguous
@not_straddling_pages @not_straddling_pages
clrlwi r23, r31, 30 clrlwi r23, r31, 30
cmpwi r23, 3 cmpwi r23, 3
rlwimi r8, r9, 0, 20, 31 rlwimi r8, r9, 0, 20, 31
beq @fail beq @fail
; Found a non-cached physical address for this NCB! ; Found a non-cached physical address for this NCB!
lwz r23, KDP.NKInfo.NCBPtrCacheMissCount(r1) lwz r23, KDP.NKInfo.NCBPtrCacheMissCount(r1)
addi r23, r23, 1 addi r23, r23, 1
stw r23, KDP.NKInfo.NCBPtrCacheMissCount(r1) stw r23, KDP.NKInfo.NCBPtrCacheMissCount(r1)
; Stick it in cache slot 3 ; Stick it in cache slot 3
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
stw r8, KDP.NCBCachePA3(r1) stw r8, KDP.NCBCachePA3(r1)
@found_in_slot_3 ; so promote to slot 2 @found_in_slot_3 ; so promote to slot 2
lwz r8, KDP.NCBCacheLA2(r1) lwz r8, KDP.NCBCacheLA2(r1)
stw r9, KDP.NCBCacheLA2(r1) stw r9, KDP.NCBCacheLA2(r1)
stw r8, KDP.NCBCacheLA3(r1) stw r8, KDP.NCBCacheLA3(r1)
lwz r9, KDP.NCBCachePA3(r1) lwz r9, KDP.NCBCachePA3(r1)
lwz r8, KDP.NCBCachePA2(r1) lwz r8, KDP.NCBCachePA2(r1)
stw r9, KDP.NCBCachePA2(r1) stw r9, KDP.NCBCachePA2(r1)
stw r8, KDP.NCBCachePA3(r1) stw r8, KDP.NCBCachePA3(r1)
lwz r9, KDP.NCBCacheLA2(r1) lwz r9, KDP.NCBCacheLA2(r1)
@found_in_slot_2 ; so promote to slot 1 @found_in_slot_2 ; so promote to slot 1
lwz r8, KDP.NCBCacheLA1(r1) lwz r8, KDP.NCBCacheLA1(r1)
stw r9, KDP.NCBCacheLA1(r1) stw r9, KDP.NCBCacheLA1(r1)
stw r8, KDP.NCBCacheLA2(r1) stw r8, KDP.NCBCacheLA2(r1)
lwz r9, KDP.NCBCachePA2(r1) lwz r9, KDP.NCBCachePA2(r1)
lwz r8, KDP.NCBCachePA1(r1) lwz r8, KDP.NCBCachePA1(r1)
stw r9, KDP.NCBCachePA1(r1) stw r9, KDP.NCBCachePA1(r1)
stw r8, KDP.NCBCachePA2(r1) stw r8, KDP.NCBCachePA2(r1)
lwz r9, KDP.NCBCacheLA1(r1) lwz r9, KDP.NCBCacheLA1(r1)
@found_in_slot_1 ; so promote to slot 0, save elsewhere, and push on @found_in_slot_1 ; so promote to slot 0, save elsewhere, and push on
lwz r8, KDP.NCBCacheLA0(r1) lwz r8, KDP.NCBCacheLA0(r1)
stw r9, KDP.NCBCacheLA0(r1) stw r9, KDP.NCBCacheLA0(r1)
; stw r9, KDP.LA_NCB(r1) ; stw r9, KDP.LA_NCB(r1)
stw r8, KDP.NCBCacheLA1(r1) stw r8, KDP.NCBCacheLA1(r1)
lwz r9, KDP.NCBCachePA1(r1) lwz r9, KDP.NCBCachePA1(r1)
lwz r8, KDP.NCBCachePA0(r1) lwz r8, KDP.NCBCachePA0(r1)
stw r9, KDP.NCBCachePA0(r1) stw r9, KDP.NCBCachePA0(r1)
stw r8, KDP.NCBCachePA1(r1) stw r8, KDP.NCBCachePA1(r1)
b @found_physical_in_cache b @found_physical_in_cache
@fail @fail
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
li r8, ecTrapInstr li r8, ecTrapInstr
b Exception b Exception
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
KCallResetSystem KCallResetSystem
; PPC trap 1, or indirectly, 68k RESET ; PPC trap 1, or indirectly, 68k RESET
stmw r14, KDP.r14(r1) stmw r14, KDP.r14(r1)
xoris r8, r3, 'Ga' xoris r8, r3, 'Ga'
cmplwi r8, 'ry' cmplwi r8, 'ry'
bne Reset bne Reset
xoris r8, r4, 0x0505 xoris r8, r4, 0x0505
cmplwi r8, 0x1956 cmplwi r8, 0x1956
bne Reset bne Reset
; Gary Davidian skeleton key: r5/D0 = MSR bits to unset, r7/D2 = MSR bits to set ; Gary Davidian skeleton key: r5/D0 = MSR bits to unset, r7/D2 = MSR bits to set
andc r11, r11, r5 andc r11, r11, r5
lwz r8, CB.r7+4(r6) lwz r8, CB.r7+4(r6)
or r11, r11, r8 or r11, r11, r8
b ReturnFromInt b ReturnFromInt
Reset Reset
include 'NKReset.s' include 'NKReset.s'
lmw r14, KDP.r14(r1) lmw r14, KDP.r14(r1)
b KCallPrioritizeInterrupts b KCallPrioritizeInterrupts
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
KCallPrioritizeInterrupts KCallPrioritizeInterrupts
; Left side: roll back the interrupt preparation before the int handler repeats is ; Left side: roll back the interrupt preparation before the int handler repeats is
; Right side: jump to the external interrupt handler (PIH or ProgramInt) ; Right side: jump to the external interrupt handler (PIH or ProgramInt)
mtsprg 2, r12 mtsprg 2, r12
mtsrr0 r10 mtsrr0 r10
mtsrr1 r11 mtsrr1 r11
mtcr r13 mtcr r13
lwz r10, CB.r10+4(r6) lwz r10, CB.r10+4(r6)
lwz r11, CB.r11+4(r6) lwz r11, CB.r11+4(r6)
lwz r12, CB.r12+4(r6) lwz r12, CB.r12+4(r6)
lwz r13, CB.r13+4(r6) lwz r13, CB.r13+4(r6)
lwz r7, CB.r7+4(r6) lwz r7, CB.r7+4(r6)
lwz r8, KDP.r1(r1) lwz r8, KDP.r1(r1)
mfsprg r9, 3 mfsprg r9, 3
lwz r9, VecTbl.External(r9) lwz r9, VecTbl.External(r9)
mtsprg 1, r8 mtsprg 1, r8
mtlr r9 mtlr r9
lwz r8, CB.r8+4(r6) lwz r8, CB.r8+4(r6)
lwz r9, CB.r9+4(r6) lwz r9, CB.r9+4(r6)
lwz r6, KDP.r6(r1) lwz r6, KDP.r6(r1)
blrl ; (could this ever fall though to KCallSystemCrash?) blrl ; (could this ever fall though to KCallSystemCrash?)
######################################################################## ########################################################################
KCallSystemCrash KCallSystemCrash
stw r0, KDP.r0(r1) stw r0, KDP.r0(r1)
stw r2, KDP.r2(r1) stw r2, KDP.r2(r1)
stw r3, KDP.r3(r1) stw r3, KDP.r3(r1)
stw r4, KDP.r4(r1) stw r4, KDP.r4(r1)
stw r5, KDP.r5(r1) stw r5, KDP.r5(r1)
lwz r8, CB.r7+4(r6) lwz r8, CB.r7+4(r6)
lwz r9, CB.r8+4(r6) lwz r9, CB.r8+4(r6)
stw r8, KDP.r7(r1) stw r8, KDP.r7(r1)
stw r9, KDP.r8(r1) stw r9, KDP.r8(r1)
lwz r8, CB.r9+4(r6) lwz r8, CB.r9+4(r6)
lwz r9, CB.r10+4(r6) lwz r9, CB.r10+4(r6)
stw r8, KDP.r9(r1) stw r8, KDP.r9(r1)
stw r9, KDP.r10(r1) stw r9, KDP.r10(r1)
lwz r8, CB.r11+4(r6) lwz r8, CB.r11+4(r6)
lwz r9, CB.r12+4(r6) lwz r9, CB.r12+4(r6)
stw r8, KDP.r11(r1) stw r8, KDP.r11(r1)
stw r9, KDP.r12(r1) stw r9, KDP.r12(r1)
lwz r8, CB.r13+4(r6) lwz r8, CB.r13+4(r6)
stw r8, KDP.r13(r1) stw r8, KDP.r13(r1)
stmw r14, KDP.r14(r1) stmw r14, KDP.r14(r1)
bl SystemCrash bl SystemCrash
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
ProgramInt ProgramInt
; (also called when the Alternate Context gets an External Int => Exception) ; (also called when the Alternate Context gets an External Int => Exception)
; Standard interrupt palaver ; Standard interrupt palaver
mfsprg r1, 0 mfsprg r1, 0
stw r6, KDP.r6(r1) stw r6, KDP.r6(r1)
mfsprg r6, 1 mfsprg r6, 1
stw r6, KDP.r1(r1) stw r6, KDP.r1(r1)
lwz r6, KDP.ContextPtr(r1) lwz r6, KDP.ContextPtr(r1)
stw r7, CB.r7+4(r6) stw r7, CB.r7+4(r6)
stw r8, CB.r8+4(r6) stw r8, CB.r8+4(r6)
stw r9, CB.r9+4(r6) stw r9, CB.r9+4(r6)
stw r10, CB.r10+4(r6) stw r10, CB.r10+4(r6)
stw r11, CB.r11+4(r6) stw r11, CB.r11+4(r6)
stw r12, CB.r12+4(r6) stw r12, CB.r12+4(r6)
stw r13, CB.r13+4(r6) stw r13, CB.r13+4(r6)
; Compare SRR0 with address of Emulator's KCall trap table ; Compare SRR0 with address of Emulator's KCall trap table
lwz r8, KDP.EmuKCallTblPtrLogical(r1) lwz r8, KDP.EmuKCallTblPtrLogical(r1)
mfsrr0 r10 mfsrr0 r10
mfcr r13 mfcr r13
xor. r8, r10, r8 xor. r8, r10, r8
lwz r7, KDP.Flags(r1) lwz r7, KDP.Flags(r1)
mfsprg r12, 2 mfsprg r12, 2
beq KCallReturnFromExceptionFastPath ; KCall in Emulator table => fast path beq KCallReturnFromExceptionFastPath ; KCall in Emulator table => fast path
rlwimi. r7, r7, bitGlobalFlagSystem, 0, 0 rlwimi. r7, r7, bitGlobalFlagSystem, 0, 0
cmplwi cr7, r8, 16 * 4 cmplwi cr7, r8, 16 * 4
bge cr0, @fromAltContext ; Alt Context cannot make KCalls; this might be an External Int bge cr0, @fromAltContext ; Alt Context cannot make KCalls; this might be an External Int
bge cr7, @notFromEmulatorTrapTable ; from Emulator but not from its KCall table => do more checks bge cr7, @notFromEmulatorTrapTable ; from Emulator but not from its KCall table => do more checks
; SUCCESSFUL TRAP from emulator KCall table ; SUCCESSFUL TRAP from emulator KCall table
; => Service call then return to link register ; => Service call then return to link register
add r8, r8, r1 add r8, r8, r1
lwz r11, KDP.NKInfo.NanoKernelCallCounts(r8) lwz r11, KDP.NKInfo.NanoKernelCallCounts(r8)
lwz r10, KDP.KCallTbl(r8) lwz r10, KDP.KCallTbl(r8)
addi r11, r11, 1 addi r11, r11, 1
stw r11, KDP.NKInfo.NanoKernelCallCounts(r8) stw r11, KDP.NKInfo.NanoKernelCallCounts(r8)
mtlr r10 mtlr r10
mr r10, r12 ; ret addr: LR was saved to SPRG2, SPRG2 to r12 above, r12 to r10 now, r10 to SRR0 to program ctr later mr r10, r12 ; ret addr: LR was saved to SPRG2, SPRG2 to r12 above, r12 to r10 now, r10 to SRR0 to program ctr later
mfsrr1 r11 mfsrr1 r11
rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE] rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE]
blr blr
@notFromEmulatorTrapTable ; so check if it is even a trap... @notFromEmulatorTrapTable ; so check if it is even a trap...
mfsrr1 r11 mfsrr1 r11
mtcrf 0x70, r11 mtcrf 0x70, r11
bc BO_IF_NOT, 14, @notTrap bc BO_IF_NOT, 14, @notTrap
mfmsr r9 ; fetch the instruction to get the "trap number" mfmsr r9 ; fetch the instruction to get the "trap number"
_set r8, r9, bitMsrDR _set r8, r9, bitMsrDR
mtmsr r8 mtmsr r8
lwz r8, 0(r10) lwz r8, 0(r10)
mtmsr r9 mtmsr r9
xoris r8, r8, 0xfff xoris r8, r8, 0xfff
cmplwi cr7, r8, 16 ; only traps 0-15 are allowed cmplwi cr7, r8, 16 ; only traps 0-15 are allowed
slwi r8, r8, 2 ; (for "success" case below) slwi r8, r8, 2 ; (for "success" case below)
bge cr7, @illegalTrap bge cr7, @illegalTrap
; SUCCESSFUL TRAP from outside emulator KCall table ; SUCCESSFUL TRAP from outside emulator KCall table
; => Service call then return to following instruction ; => Service call then return to following instruction
add r8, r8, r1 add r8, r8, r1
lwz r10, KDP.NKInfo.NanoKernelCallCounts(r8) lwz r10, KDP.NKInfo.NanoKernelCallCounts(r8)
addi r10, r10, 1 addi r10, r10, 1
stw r10, KDP.NKInfo.NanoKernelCallCounts(r8) stw r10, KDP.NKInfo.NanoKernelCallCounts(r8)
lwz r8, KDP.KCallTbl(r8) lwz r8, KDP.KCallTbl(r8)
mtlr r8 mtlr r8
addi r10, r10, 4 ; continue executing the next instruction addi r10, r10, 4 ; continue executing the next instruction
rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE] rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE]
blr blr
; Cannot service with a KCall => throw Exception ; Cannot service with a KCall => throw Exception
@fromAltContext ; external interrupt, or a (forbidden) KCall attempt @fromAltContext ; external interrupt, or a (forbidden) KCall attempt
mfsrr1 r11 mfsrr1 r11
mtcrf 0x70, r11 mtcrf 0x70, r11
@notTrap ; then it was some other software exception @notTrap ; then it was some other software exception
bc BO_IF, 12, IllegalInstruction bc BO_IF, 12, IllegalInstruction
bc BO_IF, 11, @floatingPointException bc BO_IF, 11, @floatingPointException
@illegalTrap ; because we only allow traps 0-15 @illegalTrap ; because we only allow traps 0-15
rlwinm r8, r11, 17, 28, 29 rlwinm r8, r11, 17, 28, 29
addi r8, r8, 0x4b3 addi r8, r8, 0x4b3
rlwnm r8, r8, r8, 28, 31 rlwnm r8, r8, r8, 28, 31
b Exception ; CLEVER BIT HACKING described below b Exception ; CLEVER BIT HACKING described below
; SRR1[13] SRR[14] Exception ; SRR1[13] SRR[14] Exception
; 0 0 ecNoException ; 0 0 ecNoException
; 0 1 ecTrapInstr ; 0 1 ecTrapInstr
; 1 0 ecPrivilegedInstr ; 1 0 ecPrivilegedInstr
; 1 1 9 (floating-point?) ; 1 1 9 (floating-point?)
@floatingPointException @floatingPointException
li r8, ecFloatException li r8, ecFloatException
bc BO_IF, 15, Exception ; SRR1[15] set => handler can retry bc BO_IF, 15, Exception ; SRR1[15] set => handler can retry
addi r10, r10, 4 addi r10, r10, 4
rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE] rlwimi r7, r7, 32-5, 26, 26 ; something about MSR[SE]
b Exception ; SRR1[15] unset => can't retry b Exception ; SRR1[15] unset => can't retry
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
SyscallInt SyscallInt
bl LoadInterruptRegisters bl LoadInterruptRegisters
mfmsr r8 mfmsr r8
subi r10, r10, 4 subi r10, r10, 4
rlwimi r11, r8, 0, 0xFFFF0000 rlwimi r11, r8, 0, 0xFFFF0000
li r8, ecSystemCall li r8, ecSystemCall
b Exception b Exception
######################################################################## ########################################################################
_alignToCacheBlock _alignToCacheBlock
TraceInt ; here because of MSR[SE/BE], possibly thanks to ContextFlagTraceWhenDone TraceInt ; here because of MSR[SE/BE], possibly thanks to ContextFlagTraceWhenDone
bl LoadInterruptRegisters bl LoadInterruptRegisters
li r8, ecInstTrace li r8, ecInstTrace
b Exception b Exception

796
NanoKernel/NKStructs.s
View File

@ -1,449 +1,449 @@
VecTbl RECORD 0, INCR ; SPRG3 vector table (looked up by ROM vectors) VecTbl RECORD 0, INCR ; SPRG3 vector table (looked up by ROM vectors)
ds.l 1 ; 00 ; scratch for IVT ds.l 1 ; 00 ; scratch for IVT
SystemReset ds.l 1 ; 04 ; from IVT+100 SystemReset ds.l 1 ; 04 ; from IVT+100
MachineCheck ds.l 1 ; 08 ; from IVT+200 MachineCheck ds.l 1 ; 08 ; from IVT+200
DSI ds.l 1 ; 0c ; from IVT+300 DSI ds.l 1 ; 0c ; from IVT+300
ISI ds.l 1 ; 10 ; from IVT+400 ISI ds.l 1 ; 10 ; from IVT+400
External ds.l 1 ; 14 ; from IVT+500 External ds.l 1 ; 14 ; from IVT+500
Alignment ds.l 1 ; 18 ; from IVT+600 Alignment ds.l 1 ; 18 ; from IVT+600
Program ds.l 1 ; 1c ; from IVT+700 Program ds.l 1 ; 1c ; from IVT+700
FPUnavail ds.l 1 ; 20 ; from IVT+800 FPUnavail ds.l 1 ; 20 ; from IVT+800
Decrementer ds.l 1 ; 24 ; from IVT+900 Decrementer ds.l 1 ; 24 ; from IVT+900
ReservedVector1 ds.l 1 ; 28 ; from IVT+a00 ReservedVector1 ds.l 1 ; 28 ; from IVT+a00
ReservedVector2 ds.l 1 ; 2c ; from IVT+b00 ReservedVector2 ds.l 1 ; 2c ; from IVT+b00
Syscall ds.l 1 ; 30 ; from IVT+c00 Syscall ds.l 1 ; 30 ; from IVT+c00
Trace ds.l 1 ; 34 ; from IVT+d00 Trace ds.l 1 ; 34 ; from IVT+d00
FPAssist ds.l 1 ; 38 ; from IVT+e00 FPAssist ds.l 1 ; 38 ; from IVT+e00
PerfMonitor ds.l 1 ; 3c ; from IVT+f00 PerfMonitor ds.l 1 ; 3c ; from IVT+f00
ds.l 1 ; 40 ds.l 1 ; 40
ds.l 1 ; 44 ds.l 1 ; 44
ds.l 1 ; 48 ds.l 1 ; 48
ds.l 1 ; 4c ; Vectors from here downwards are called from ds.l 1 ; 4c ; Vectors from here downwards are called from
ds.l 1 ; 50 ; odd places in the IVT ds.l 1 ; 50 ; odd places in the IVT
ds.l 1 ; 54 ds.l 1 ; 54
ds.l 1 ; 58 ; seems AltiVec-related ds.l 1 ; 58 ; seems AltiVec-related
ThermalEvent ds.l 1 ; 5c ThermalEvent ds.l 1 ; 5c
ds.l 1 ; 60 ds.l 1 ; 60
ds.l 1 ; 64 ds.l 1 ; 64
ds.l 1 ; 68 ds.l 1 ; 68
ds.l 1 ; 6c ds.l 1 ; 6c
ds.l 1 ; 70 ds.l 1 ; 70
ds.l 1 ; 74 ds.l 1 ; 74
ds.l 1 ; 78 ds.l 1 ; 78
ds.l 1 ; 7c ds.l 1 ; 7c
OtherTrace ds.l 1 ; 80 OtherTrace ds.l 1 ; 80
ds.l 1 ; 84 ds.l 1 ; 84
ds.l 1 ; 88 ds.l 1 ; 88
ds.l 1 ; 8c ds.l 1 ; 8c
ds.l 1 ; 90 ds.l 1 ; 90
ds.l 1 ; 94 ds.l 1 ; 94
ds.l 1 ; 98 ds.l 1 ; 98
ds.l 1 ; 9c ds.l 1 ; 9c
ds.l 1 ; a0 ds.l 1 ; a0
ds.l 1 ; a4 ds.l 1 ; a4
ds.l 1 ; a8 ds.l 1 ; a8
ds.l 1 ; ac ds.l 1 ; ac
ds.l 1 ; b0 ds.l 1 ; b0
ds.l 1 ; b4 ds.l 1 ; b4
ds.l 1 ; b8 ds.l 1 ; b8
ds.l 1 ; bc ; from IVT+0 ds.l 1 ; bc ; from IVT+0
Size equ * Size equ *
ENDR ENDR
######################################################################## ########################################################################
KCallTbl RECORD 0, INCR ; NanoKernel call table KCallTbl RECORD 0, INCR ; NanoKernel call table
ReturnFromException ds.l 1 ; 00, trap 0 ReturnFromException ds.l 1 ; 00, trap 0
RunAlternateContext ds.l 1 ; 04, trap 1 RunAlternateContext ds.l 1 ; 04, trap 1
ResetSystem ds.l 1 ; 08, trap 2 ; 68k RESET ResetSystem ds.l 1 ; 08, trap 2 ; 68k RESET
VMDispatch ds.l 1 ; 0c, trap 3 ; 68k $FE0A VMDispatch ds.l 1 ; 0c, trap 3 ; 68k $FE0A
PrioritizeInterrupts ds.l 1 ; 10, trap 4 PrioritizeInterrupts ds.l 1 ; 10, trap 4
PowerDispatch ds.l 1 ; 14, trap 5 ; 68k $FEOF PowerDispatch ds.l 1 ; 14, trap 5 ; 68k $FEOF
RTASDispatch ds.l 1 ; 18, trap 6 RTASDispatch ds.l 1 ; 18, trap 6
CacheDispatch ds.l 1 ; 1c, trap 7 CacheDispatch ds.l 1 ; 1c, trap 7
MPDispatch ds.l 1 ; 20, trap 8 MPDispatch ds.l 1 ; 20, trap 8
ds.l 1 ; 24, trap 9 ds.l 1 ; 24, trap 9
ds.l 1 ; 28, trap 10 ds.l 1 ; 28, trap 10
ds.l 1 ; 2c, trap 11 ds.l 1 ; 2c, trap 11
CallAdapterProcPPC ds.l 1 ; 30, trap 12 CallAdapterProcPPC ds.l 1 ; 30, trap 12
ds.l 1 ; 34, trap 13 ds.l 1 ; 34, trap 13
CallAdapterProc68k ds.l 1 ; 38, trap 14 CallAdapterProc68k ds.l 1 ; 38, trap 14
SystemCrash ds.l 1 ; 3c, trap 15 SystemCrash ds.l 1 ; 3c, trap 15
Size equ * Size equ *
ENDR ENDR
######################################################################## ########################################################################
PME RECORD 0, INCR ; PageMap Entry PME RECORD 0, INCR ; PageMap Entry
LBase ds.w 1 ; 0 ; (base - segment) >> 12 LBase ds.w 1 ; 0 ; (base - segment) >> 12
PageCount ds.w 1 ; 2 ; page count MINUS ONE PageCount ds.w 1 ; 2 ; page count MINUS ONE
PBaseAndFlags ds.l 1 ; 4 ; PBase page aligned PBaseAndFlags ds.l 1 ; 4 ; PBase page aligned
PBaseBits equ 20 PBaseBits equ 20
FirstFlagBit equ 20 FirstFlagBit equ 20
FirstFlag equ 0x800 FirstFlag equ 0x800
DaddyFlag equ 0x800 DaddyFlag equ 0x800
CountingFlag equ 0x400 CountingFlag equ 0x400
PhysicalIsRelativeFlag equ 0x200 PhysicalIsRelativeFlag equ 0x200
; try not to use the equates above; they are dicey ; try not to use the equates above; they are dicey
TopFieldMask equ 0xe00 TopFieldMask equ 0xe00
Size equ * Size equ *
ENDR ENDR
######################################################################## ########################################################################
BAT RECORD 0, INCR BAT RECORD 0, INCR
U ds.l 1 U ds.l 1
L ds.l 1 L ds.l 1
ENDR ENDR
######################################################################## ########################################################################
MemMap RECORD 0, INCR MemMap RECORD 0, INCR
SegMapPtr ds.l 1 SegMapPtr ds.l 1
BatMap ds.l 1 ; packed array of 4-bit indices into BATs BatMap ds.l 1 ; packed array of 4-bit indices into BATs
ENDR ENDR
######################################################################## ########################################################################
KDP RECORD 0, INCR ; Kernel Data Page KDP RECORD 0, INCR ; Kernel Data Page
r0 ds.l 1 ; 000 ; used for quick register saves at interrupt time r0 ds.l 1 ; 000 ; used for quick register saves at interrupt time
r1 ds.l 1 ; 004 r1 ds.l 1 ; 004
r2 ds.l 1 ; 008 r2 ds.l 1 ; 008
r3 ds.l 1 ; 00c r3 ds.l 1 ; 00c
r4 ds.l 1 ; 010 r4 ds.l 1 ; 010
r5 ds.l 1 ; 014 r5 ds.l 1 ; 014
r6 ds.l 1 ; 018 r6 ds.l 1 ; 018
r7 ds.l 1 ; 01c r7 ds.l 1 ; 01c
r8 ds.l 1 ; 020 r8 ds.l 1 ; 020
r9 ds.l 1 ; 024 r9 ds.l 1 ; 024
r10 ds.l 1 ; 028 r10 ds.l 1 ; 028
r11 ds.l 1 ; 02c r11 ds.l 1 ; 02c
r12 ds.l 1 ; 030 r12 ds.l 1 ; 030
r13 ds.l 1 ; 034 r13 ds.l 1 ; 034
r14 ds.l 1 ; 038 r14 ds.l 1 ; 038
r15 ds.l 1 ; 03c r15 ds.l 1 ; 03c
r16 ds.l 1 ; 040 r16 ds.l 1 ; 040
r17 ds.l 1 ; 044 r17 ds.l 1 ; 044
r18 ds.l 1 ; 048 r18 ds.l 1 ; 048
r19 ds.l 1 ; 04c r19 ds.l 1 ; 04c
r20 ds.l 1 ; 050 r20 ds.l 1 ; 050
r21 ds.l 1 ; 054 r21 ds.l 1 ; 054
r22 ds.l 1 ; 058 r22 ds.l 1 ; 058
r23 ds.l 1 ; 05c r23 ds.l 1 ; 05c
r24 ds.l 1 ; 060 r24 ds.l 1 ; 060
r25 ds.l 1 ; 064 r25 ds.l 1 ; 064
r26 ds.l 1 ; 068 r26 ds.l 1 ; 068
r27 ds.l 1 ; 06c r27 ds.l 1 ; 06c
r28 ds.l 1 ; 070 r28 ds.l 1 ; 070
r29 ds.l 1 ; 074 r29 ds.l 1 ; 074
r30 ds.l 1 ; 078 r30 ds.l 1 ; 078
r31 ds.l 1 ; 07c r31 ds.l 1 ; 07c
SegMaps SegMaps
SegMap32SupInit ds.l 32 ; 080:100 SegMap32SupInit ds.l 32 ; 080:100
SegMap32UsrInit ds.l 32 ; 100:180 SegMap32UsrInit ds.l 32 ; 100:180
SegMap32CPUInit ds.l 32 ; 180:200 SegMap32CPUInit ds.l 32 ; 180:200
SegMap32OvlInit ds.l 32 ; 200:280 SegMap32OvlInit ds.l 32 ; 200:280
BATs ds.l 32 ; 280:300 BATs ds.l 32 ; 280:300
CurIBAT0 ds BAT ; 300:308 CurIBAT0 ds BAT ; 300:308
CurIBAT1 ds BAT ; 308:310 CurIBAT1 ds BAT ; 308:310
CurIBAT2 ds BAT ; 310:318 CurIBAT2 ds BAT ; 310:318
CurIBAT3 ds BAT ; 318:320 CurIBAT3 ds BAT ; 318:320
CurDBAT0 ds BAT ; 320:328 CurDBAT0 ds BAT ; 320:328
CurDBAT1 ds BAT ; 328:330 CurDBAT1 ds BAT ; 328:330
CurDBAT2 ds BAT ; 330:338 CurDBAT2 ds BAT ; 330:338
CurDBAT3 ds BAT ; 338:340 CurDBAT3 ds BAT ; 338:340
NCBPointerCache NCBPointerCache
NCBCacheLA0 ds.l 1 ; 340 NCBCacheLA0 ds.l 1 ; 340
NCBCachePA0 ds.l 1 ; 344 NCBCachePA0 ds.l 1 ; 344
NCBCacheLA1 ds.l 1 ; 348 NCBCacheLA1 ds.l 1 ; 348
NCBCachePA1 ds.l 1 ; 34c NCBCachePA1 ds.l 1 ; 34c
NCBCacheLA2 ds.l 1 ; 350 NCBCacheLA2 ds.l 1 ; 350
NCBCachePA2 ds.l 1 ; 354 NCBCachePA2 ds.l 1 ; 354
NCBCacheLA3 ds.l 1 ; 358 NCBCacheLA3 ds.l 1 ; 358
NCBCachePA3 ds.l 1 ; 35c NCBCachePA3 ds.l 1 ; 35c
NCBPointerCacheEnd NCBPointerCacheEnd
VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTask VecTblSystem ds VecTbl ; 360:420 ; when 68k emulator is running, *or* any MTask
VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task VecTblAlternate ds VecTbl ; 420:4e0 ; native PowerPC in blue task
VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation VecTblMemRetry ds VecTbl ; 4e0:5a0 ; "FDP" instruction emulation
FloatScratch ds.d 1 ; 5a0:5a8 FloatScratch ds.d 1 ; 5a0:5a8
TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0 TopOfFreePages ds.l 1 ; 5a8 ; gotten from the old SPRG0
ds.l 1 ; 5ac ds.l 1 ; 5ac
PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList PARPerSegmentPLEPtrs ds.l 4 ; 5b0:5c0 ; for each PAR segment, a ptr into the PAR PageList
FloatingPtTemp1 ds.l 1 ; 5c0 FloatingPtTemp1 ds.l 1 ; 5c0
FloatingPtTemp2 ds.l 1 ; 5c4 FloatingPtTemp2 ds.l 1 ; 5c4
SupervisorMap ds MemMap ; 5c8:5d0 SupervisorMap ds MemMap ; 5c8:5d0
UserMap ds MemMap ; 5d0:5d8 UserMap ds MemMap ; 5d0:5d8
CpuMap ds MemMap ; 5d8:5e0 CpuMap ds MemMap ; 5d8:5e0
OverlayMap ds MemMap ; 5e0:5e8 OverlayMap ds MemMap ; 5e0:5e8
CurMap ds MemMap ; 5e8:5f0 CurMap ds MemMap ; 5e8:5f0
KCallTbl ds KCallTbl ; 5f0:630 KCallTbl ds KCallTbl ; 5f0:630
ConfigInfoPtr ds.l 1 ; 630 ConfigInfoPtr ds.l 1 ; 630
EDPPtr ds.l 1 ; 634 EDPPtr ds.l 1 ; 634
KernelMemoryBase ds.l 1 ; 638 KernelMemoryBase ds.l 1 ; 638
KernelMemoryEnd ds.l 1 ; 63c KernelMemoryEnd ds.l 1 ; 63c
LowMemPtr ds.l 1 ; 640 ; physical address of PAR Low Memory LowMemPtr ds.l 1 ; 640 ; physical address of PAR Low Memory
SharedMemoryAddr ds.l 1 ; 644 ; debug? SharedMemoryAddr ds.l 1 ; 644 ; debug?
EmuKCallTblPtrLogical ds.l 1 ; 648 EmuKCallTblPtrLogical ds.l 1 ; 648
CodeBase ds.l 1 ; 64c CodeBase ds.l 1 ; 64c
MRBase ds.l 1 ; 650 MRBase ds.l 1 ; 650
ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock ECBPtrLogical ds.l 1 ; 654 ; Emulator/System ContextBlock
ECBPtr ds.l 1 ; 658 ECBPtr ds.l 1 ; 658
ContextPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2 ContextPtr ds.l 1 ; 65c ; moved to EWA (per-CPU) in NKv2
Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2 Flags ds.l 1 ; 660 ; moved to EWA (per-CPU) in NKv2
Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2 Enables ds.l 1 ; 664 ; moved to EWA (per-CPU) in NKv2
OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s OtherContextDEC ds.l 1 ; 668 ; ticks that the *inactive* context has left out of 1s
PageMapEndPtr ds.l 1 ; 66c ; et at the same time as PageMapStartPtr below PageMapEndPtr ds.l 1 ; 66c ; et at the same time as PageMapStartPtr below
TestIntMaskInit ds.l 1 ; 670 TestIntMaskInit ds.l 1 ; 670
PostIntMaskInit ds.l 1 ; 674 ; CR flags to set when posting an interrupt to the Emulator PostIntMaskInit ds.l 1 ; 674 ; CR flags to set when posting an interrupt to the Emulator
ClearIntMaskInit ds.l 1 ; 678 ; CR flags to clear (as mask) when clearing an interrupt ClearIntMaskInit ds.l 1 ; 678 ; CR flags to clear (as mask) when clearing an interrupt
EmuIntLevelPtr ds.l 1 ; 67c ; physical ptr to an Emulator global EmuIntLevelPtr ds.l 1 ; 67c ; physical ptr to an Emulator global
DebugIntPtr ds.l 1 ; 680 ; within (debug?) shared memory DebugIntPtr ds.l 1 ; 680 ; within (debug?) shared memory
PageMapStartPtr ds.l 1 ; 684 PageMapStartPtr ds.l 1 ; 684
PageAttributeInit ds.l 1 ; 688 ; defaults for PLE/PTE? PageAttributeInit ds.l 1 ; 688 ; defaults for PLE/PTE?
HtabTempPage ds.l 1 ; 68c ; a page that lives temporarily in the HTAB (per its PME) HtabTempPage ds.l 1 ; 68c ; a page that lives temporarily in the HTAB (per its PME)
HtabTempEntryPtr ds.l 1 ; 690 ; ptr to that PME HtabTempEntryPtr ds.l 1 ; 690 ; ptr to that PME
HtabLastEA ds.l 1 ; 694 HtabLastEA ds.l 1 ; 694
ApproxCurrentPTEG ds.l 1 ; 698 ApproxCurrentPTEG ds.l 1 ; 698
OverflowingPTEG ds.l 1 ; 69c OverflowingPTEG ds.l 1 ; 69c
PTEGMask ds.l 1 ; 6a0 PTEGMask ds.l 1 ; 6a0
HTABORG ds.l 1 ; 6a4 HTABORG ds.l 1 ; 6a4
VMLogicalPages ds.l 1 ; 6a8 ; set at init and changed by VMInit VMLogicalPages ds.l 1 ; 6a8 ; set at init and changed by VMInit
TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory TotalPhysicalPages ds.l 1 ; 6ac ; does not take into acct maximum MacOS memory
PARPageListPtr ds.l 1 ; 6b0 ; VM puts this in system heap PARPageListPtr ds.l 1 ; 6b0 ; VM puts this in system heap
VMMaxVirtualPages ds.l 1 ; 6b4 ; always 5fffe000, even with VM on VMMaxVirtualPages ds.l 1 ; 6b4 ; always 5fffe000, even with VM on
org 0x700 org 0x700
CrashTop CrashTop
CrashR0 ds.l 1 ; 700 CrashR0 ds.l 1 ; 700
CrashR1 ds.l 1 ; 704 CrashR1 ds.l 1 ; 704
CrashR2 ds.l 1 ; 708 CrashR2 ds.l 1 ; 708
CrashR3 ds.l 1 ; 70c CrashR3 ds.l 1 ; 70c
CrashR4 ds.l 1 ; 710 CrashR4 ds.l 1 ; 710
CrashR5 ds.l 1 ; 714 CrashR5 ds.l 1 ; 714
CrashR6 ds.l 1 ; 718 CrashR6 ds.l 1 ; 718
CrashR7 ds.l 1 ; 71c CrashR7 ds.l 1 ; 71c
CrashR8 ds.l 1 ; 720 CrashR8 ds.l 1 ; 720
CrashR9 ds.l 1 ; 724 CrashR9 ds.l 1 ; 724
CrashR10 ds.l 1 ; 728 CrashR10 ds.l 1 ; 728
CrashR11 ds.l 1 ; 72c CrashR11 ds.l 1 ; 72c
CrashR12 ds.l 1 ; 730 CrashR12 ds.l 1 ; 730
CrashR13 ds.l 1 ; 734 CrashR13 ds.l 1 ; 734
CrashR14 ds.l 1 ; 738 CrashR14 ds.l 1 ; 738
CrashR15 ds.l 1 ; 73c CrashR15 ds.l 1 ; 73c
CrashR16 ds.l 1 ; 740 CrashR16 ds.l 1 ; 740
CrashR17 ds.l 1 ; 744 CrashR17 ds.l 1 ; 744
CrashR18 ds.l 1 ; 748 CrashR18 ds.l 1 ; 748
CrashR19 ds.l 1 ; 74c CrashR19 ds.l 1 ; 74c
CrashR20 ds.l 1 ; 750 CrashR20 ds.l 1 ; 750
CrashR21 ds.l 1 ; 754 CrashR21 ds.l 1 ; 754
CrashR22 ds.l 1 ; 758 CrashR22 ds.l 1 ; 758
CrashR23 ds.l 1 ; 75c CrashR23 ds.l 1 ; 75c
CrashR24 ds.l 1 ; 760 CrashR24 ds.l 1 ; 760
CrashR25 ds.l 1 ; 764 CrashR25 ds.l 1 ; 764
CrashR26 ds.l 1 ; 768 CrashR26 ds.l 1 ; 768
CrashR27 ds.l 1 ; 76c CrashR27 ds.l 1 ; 76c
CrashR28 ds.l 1 ; 770 CrashR28 ds.l 1 ; 770
CrashR29 ds.l 1 ; 774 CrashR29 ds.l 1 ; 774
CrashR30 ds.l 1 ; 778 CrashR30 ds.l 1 ; 778
CrashR31 ds.l 1 ; 77c CrashR31 ds.l 1 ; 77c
CrashCR ds.l 1 ; 780 CrashCR ds.l 1 ; 780
CrashMQ ds.l 1 ; 784 CrashMQ ds.l 1 ; 784
CrashXER ds.l 1 ; 788 CrashXER ds.l 1 ; 788
CrashLR ds.l 1 ; 78c CrashLR ds.l 1 ; 78c
CrashCTR ds.l 1 ; 790 CrashCTR ds.l 1 ; 790
CrashPVR ds.l 1 ; 794 CrashPVR ds.l 1 ; 794
CrashDSISR ds.l 1 ; 798 CrashDSISR ds.l 1 ; 798
CrashDAR ds.l 1 ; 79c CrashDAR ds.l 1 ; 79c
CrashRTCU ds.l 1 ; 7a0 CrashRTCU ds.l 1 ; 7a0
CrashRTCL ds.l 1 ; 7a4 CrashRTCL ds.l 1 ; 7a4
CrashDEC ds.l 1 ; 7a8 CrashDEC ds.l 1 ; 7a8
CrashHID0 ds.l 1 ; 7ac CrashHID0 ds.l 1 ; 7ac
CrashSDR1 ds.l 1 ; 7b0 CrashSDR1 ds.l 1 ; 7b0
CrashSRR0 ds.l 1 ; 7b4 CrashSRR0 ds.l 1 ; 7b4
CrashSRR1 ds.l 1 ; 7b8 CrashSRR1 ds.l 1 ; 7b8
CrashMSR ds.l 1 ; 7bc CrashMSR ds.l 1 ; 7bc
CrashSR0 ds.l 1 ; 7c0 CrashSR0 ds.l 1 ; 7c0
CrashSR1 ds.l 1 ; 7c4 CrashSR1 ds.l 1 ; 7c4
CrashSR2 ds.l 1 ; 7c8 CrashSR2 ds.l 1 ; 7c8
CrashSR3 ds.l 1 ; 7cc CrashSR3 ds.l 1 ; 7cc
CrashSR4 ds.l 1 ; 7d0 CrashSR4 ds.l 1 ; 7d0
CrashSR5 ds.l 1 ; 7d4 CrashSR5 ds.l 1 ; 7d4
CrashSR6 ds.l 1 ; 7d8 CrashSR6 ds.l 1 ; 7d8
CrashSR7 ds.l 1 ; 7dc CrashSR7 ds.l 1 ; 7dc
CrashSR8 ds.l 1 ; 7e0 CrashSR8 ds.l 1 ; 7e0
CrashSR9 ds.l 1 ; 7e4 CrashSR9 ds.l 1 ; 7e4
CrashSR10 ds.l 1 ; 7e8 CrashSR10 ds.l 1 ; 7e8
CrashSR11 ds.l 1 ; 7ec CrashSR11 ds.l 1 ; 7ec
CrashSR12 ds.l 1 ; 7f0 CrashSR12 ds.l 1 ; 7f0
CrashSR13 ds.l 1 ; 7f4 CrashSR13 ds.l 1 ; 7f4
CrashSR14 ds.l 1 ; 7f8 CrashSR14 ds.l 1 ; 7f8
CrashSR15 ds.l 1 ; 7fc CrashSR15 ds.l 1 ; 7fc
CrashF0 ds.d 1 ; 800 CrashF0 ds.d 1 ; 800
CrashF1 ds.d 1 ; 808 CrashF1 ds.d 1 ; 808
CrashF2 ds.d 1 ; 810 CrashF2 ds.d 1 ; 810
CrashF3 ds.d 1 ; 818 CrashF3 ds.d 1 ; 818
CrashF4 ds.d 1 ; 820 CrashF4 ds.d 1 ; 820
CrashF5 ds.d 1 ; 828 CrashF5 ds.d 1 ; 828
CrashF6 ds.d 1 ; 830 CrashF6 ds.d 1 ; 830
CrashF7 ds.d 1 ; 838 CrashF7 ds.d 1 ; 838
CrashF8 ds.d 1 ; 840 CrashF8 ds.d 1 ; 840
CrashF9 ds.d 1 ; 848 CrashF9 ds.d 1 ; 848
CrashF10 ds.d 1 ; 850 CrashF10 ds.d 1 ; 850
CrashF11 ds.d 1 ; 858 CrashF11 ds.d 1 ; 858
CrashF12 ds.d 1 ; 860 CrashF12 ds.d 1 ; 860
CrashF13 ds.d 1 ; 868 CrashF13 ds.d 1 ; 868
CrashF14 ds.d 1 ; 870 CrashF14 ds.d 1 ; 870
CrashF15 ds.d 1 ; 878 CrashF15 ds.d 1 ; 878
CrashF16 ds.d 1 ; 880 CrashF16 ds.d 1 ; 880
CrashF17 ds.d 1 ; 888 CrashF17 ds.d 1 ; 888
CrashF18 ds.d 1 ; 890 CrashF18 ds.d 1 ; 890
CrashF19 ds.d 1 ; 898 CrashF19 ds.d 1 ; 898
CrashF20 ds.d 1 ; 8a0 CrashF20 ds.d 1 ; 8a0
CrashF21 ds.d 1 ; 8a8 CrashF21 ds.d 1 ; 8a8
CrashF22 ds.d 1 ; 8b0 CrashF22 ds.d 1 ; 8b0
CrashF23 ds.d 1 ; 8b8 CrashF23 ds.d 1 ; 8b8
CrashF24 ds.d 1 ; 8c0 CrashF24 ds.d 1 ; 8c0
CrashF25 ds.d 1 ; 8c8 CrashF25 ds.d 1 ; 8c8
CrashF26 ds.d 1 ; 8d0 CrashF26 ds.d 1 ; 8d0
CrashF27 ds.d 1 ; 8d8 CrashF27 ds.d 1 ; 8d8
CrashF28 ds.d 1 ; 8e0 CrashF28 ds.d 1 ; 8e0
CrashF29 ds.d 1 ; 8e8 CrashF29 ds.d 1 ; 8e8
CrashF30 ds.d 1 ; 8f0 CrashF30 ds.d 1 ; 8f0
CrashF31 ds.d 1 ; 8f8 CrashF31 ds.d 1 ; 8f8
CrashFPSCR ds.l 1 ; 900 CrashFPSCR ds.l 1 ; 900
CrashKernReturn ds.l 1 ; 904 CrashKernReturn ds.l 1 ; 904
CrashUnknown1 ds.l 1 ; 908 CrashUnknown1 ds.l 1 ; 908
CrashUnknown2 ds.l 1 ; 90c CrashUnknown2 ds.l 1 ; 90c
CrashBtm CrashBtm
PageMap ds.b 0x1a8 ; 910:ab8 PageMap ds.b 0x1a8 ; 910:ab8
org 0xCC0 org 0xCC0
SysInfo ds NKSystemInfo ; cc0:d80 SysInfo ds NKSystemInfo ; cc0:d80
DiagInfo ds NKDiagInfo ; d80:e80 DiagInfo ds NKDiagInfo ; d80:e80
NKInfo ds NKNanoKernelInfo ; e80:f80 NKInfo ds NKNanoKernelInfo ; e80:f80
ProcInfo ds NKProcessorInfo ; f80:fc0 ProcInfo ds NKProcessorInfo ; f80:fc0
InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords InfoRecBlk ds.b 64 ; fc0:1000 ; Access using ptr equates in InfoRecords
ENDR ENDR
######################################################################## ########################################################################
KernelState RECORD 0,INCR KernelState RECORD 0,INCR
Flags ds.l 1 ; 00 Flags ds.l 1 ; 00
Enables ds.l 1 ; 04 Enables ds.l 1 ; 04
Handler ds.d 1 ; 08 Handler ds.d 1 ; 08
HandlerArg ds.d 1 ; 10 HandlerArg ds.d 1 ; 10
HandlerReturn ds.d 1 ; 18 HandlerReturn ds.d 1 ; 18
MemRet17 ds.d 1 ; 20 ; MemRetry state MemRet17 ds.d 1 ; 20 ; MemRetry state
MemRetData ds.d 1 ; 28 MemRetData ds.d 1 ; 28
MemRet19 ds.d 1 ; 30 MemRet19 ds.d 1 ; 30
MemRet18 ds.d 1 ; 38 MemRet18 ds.d 1 ; 38
ENDR ENDR
######################################################################## ########################################################################
CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate) CB RECORD 0,INCR ; ContextBlock (Emulator/System or Native/Alternate)
InterState ds KernelState ; 000:040 ; for switching between contexts InterState ds KernelState ; 000:040 ; for switching between contexts
IntraState ds KernelState ; 040:080 ; for raising/disposing exceptions within a context IntraState ds KernelState ; 040:080 ; for raising/disposing exceptions within a context
FaultSrcPC ds.d 1 ; 080 ; saved when starting an exception handler FaultSrcPC ds.d 1 ; 080 ; saved when starting an exception handler
FaultSrcLR ds.d 1 ; 088 FaultSrcLR ds.d 1 ; 088
FaultSrcR3 ds.d 1 ; 090 FaultSrcR3 ds.d 1 ; 090
FaultSrcR4 ds.d 1 ; 098 FaultSrcR4 ds.d 1 ; 098
MSR ds.d 1 ; 0a0 MSR ds.d 1 ; 0a0
ds.d 1 ; 0a8 ds.d 1 ; 0a8
ds.d 1 ; 0b0 ds.d 1 ; 0b0
ds.d 1 ; 0b8 ds.d 1 ; 0b8
MQ ds.d 1 ; 0c0 ; 601 only MQ ds.d 1 ; 0c0 ; 601 only
ds.d 1 ; 0c8 ds.d 1 ; 0c8
XER ds.d 1 ; 0d0 XER ds.d 1 ; 0d0
CR ds.d 1 ; 0d8 CR ds.d 1 ; 0d8
FPSCR ds.d 1 ; 0e0 ; unsure, mffs/mtfs? FPSCR ds.d 1 ; 0e0 ; unsure, mffs/mtfs?
LR ds.d 1 ; 0e8 LR ds.d 1 ; 0e8
CTR ds.d 1 ; 0f0 CTR ds.d 1 ; 0f0
PC ds.d 1 ; 0f8 PC ds.d 1 ; 0f8
r0 ds.d 1 ; 100 ; big-endian, so 32-bit value stored in second word r0 ds.d 1 ; 100 ; big-endian, so 32-bit value stored in second word
r1 ds.d 1 ; 108 r1 ds.d 1 ; 108
r2 ds.d 1 ; 110 r2 ds.d 1 ; 110
r3 ds.d 1 ; 118 r3 ds.d 1 ; 118
r4 ds.d 1 ; 120 r4 ds.d 1 ; 120
r5 ds.d 1 ; 128 r5 ds.d 1 ; 128
r6 ds.d 1 ; 130 r6 ds.d 1 ; 130
r7 ds.d 1 ; 138 r7 ds.d 1 ; 138
r8 ds.d 1 ; 140 r8 ds.d 1 ; 140
r9 ds.d 1 ; 148 r9 ds.d 1 ; 148
r10 ds.d 1 ; 150 r10 ds.d 1 ; 150
r11 ds.d 1 ; 158 r11 ds.d 1 ; 158
r12 ds.d 1 ; 160 r12 ds.d 1 ; 160
r13 ds.d 1 ; 168 r13 ds.d 1 ; 168
r14 ds.d 1 ; 170 r14 ds.d 1 ; 170
r15 ds.d 1 ; 178 r15 ds.d 1 ; 178
r16 ds.d 1 ; 180 r16 ds.d 1 ; 180
r17 ds.d 1 ; 188 r17 ds.d 1 ; 188
r18 ds.d 1 ; 190 r18 ds.d 1 ; 190
r19 ds.d 1 ; 198 r19 ds.d 1 ; 198
r20 ds.d 1 ; 1a0 r20 ds.d 1 ; 1a0
r21 ds.d 1 ; 1a8 r21 ds.d 1 ; 1a8
r22 ds.d 1 ; 1b0 r22 ds.d 1 ; 1b0
r23 ds.d 1 ; 1b8 r23 ds.d 1 ; 1b8
r24 ds.d 1 ; 1c0 r24 ds.d 1 ; 1c0
r25 ds.d 1 ; 1c8 r25 ds.d 1 ; 1c8
r26 ds.d 1 ; 1d0 r26 ds.d 1 ; 1d0
r27 ds.d 1 ; 1d8 r27 ds.d 1 ; 1d8
r28 ds.d 1 ; 1e0 r28 ds.d 1 ; 1e0
r29 ds.d 1 ; 1e8 r29 ds.d 1 ; 1e8
r30 ds.d 1 ; 1f0 r30 ds.d 1 ; 1f0
r31 ds.d 1 ; 1f8 r31 ds.d 1 ; 1f8
f0 ds.d 1 ; 200 f0 ds.d 1 ; 200
f1 ds.d 1 ; 208 f1 ds.d 1 ; 208
f2 ds.d 1 ; 210 f2 ds.d 1 ; 210
f3 ds.d 1 ; 218 f3 ds.d 1 ; 218
f4 ds.d 1 ; 220 f4 ds.d 1 ; 220
f5 ds.d 1 ; 228 f5 ds.d 1 ; 228
f6 ds.d 1 ; 230 f6 ds.d 1 ; 230
f7 ds.d 1 ; 238 f7 ds.d 1 ; 238
f8 ds.d 1 ; 240 f8 ds.d 1 ; 240
f9 ds.d 1 ; 248 f9 ds.d 1 ; 248
f10 ds.d 1 ; 250 f10 ds.d 1 ; 250
f11 ds.d 1 ; 258 f11 ds.d 1 ; 258
f12 ds.d 1 ; 260 f12 ds.d 1 ; 260
f13 ds.d 1 ; 268 f13 ds.d 1 ; 268
f14 ds.d 1 ; 270 f14 ds.d 1 ; 270
f15 ds.d 1 ; 278 f15 ds.d 1 ; 278
f16 ds.d 1 ; 280 f16 ds.d 1 ; 280
f17 ds.d 1 ; 288 f17 ds.d 1 ; 288
f18 ds.d 1 ; 290 f18 ds.d 1 ; 290
f19 ds.d 1 ; 298 f19 ds.d 1 ; 298
f20 ds.d 1 ; 2a0 f20 ds.d 1 ; 2a0
f21 ds.d 1 ; 2a8 f21 ds.d 1 ; 2a8
f22 ds.d 1 ; 2b0 f22 ds.d 1 ; 2b0
f23 ds.d 1 ; 2b8 f23 ds.d 1 ; 2b8
f24 ds.d 1 ; 2c0 f24 ds.d 1 ; 2c0
f25 ds.d 1 ; 2c8 f25 ds.d 1 ; 2c8
f26 ds.d 1 ; 2d0 f26 ds.d 1 ; 2d0
f27 ds.d 1 ; 2d8 f27 ds.d 1 ; 2d8
f28 ds.d 1 ; 2e0 f28 ds.d 1 ; 2e0
f29 ds.d 1 ; 2e8 f29 ds.d 1 ; 2e8
f30 ds.d 1 ; 2f0 f30 ds.d 1 ; 2f0
f31 ds.d 1 ; 2f8 f31 ds.d 1 ; 2f8
ENDR ENDR

268
NanoKernel/NKSystemCrash.s
View File

@ -1,163 +1,165 @@
; AUTO-GENERATED SYMBOL LIST ; AUTO-GENERATED SYMBOL LIST
; EXPORTS:
; SystemCrash (=> MRInterrupts, MROptabCode, NKExceptions, NKLegacyVM, NKMemory, NKReset, NKSoftInts)
######################################################################## ########################################################################
SystemCrash SystemCrash
mfsprg r1, 0 mfsprg r1, 0
stw r0, KDP.CrashR0(r1) stw r0, KDP.CrashR0(r1)
mfsprg r0, 1 mfsprg r0, 1
stw r0, KDP.CrashR1(r1) stw r0, KDP.CrashR1(r1)
stmw r2, KDP.CrashR2(r1) stmw r2, KDP.CrashR2(r1)
mfcr r0 mfcr r0
stw r0, KDP.CrashCR(r1) stw r0, KDP.CrashCR(r1)
mfspr r0, mq mfspr r0, mq
stw r0, KDP.CrashMQ(r1) stw r0, KDP.CrashMQ(r1)
mfxer r0 mfxer r0
stw r0, KDP.CrashXER(r1) stw r0, KDP.CrashXER(r1)
mfsprg r0, 2 mfsprg r0, 2
stw r0, KDP.CrashLR(r1) stw r0, KDP.CrashLR(r1)
mfctr r0 mfctr r0
stw r0, KDP.CrashCTR(r1) stw r0, KDP.CrashCTR(r1)
mfspr r0, pvr mfspr r0, pvr
stw r0, KDP.CrashPVR(r1) stw r0, KDP.CrashPVR(r1)
mfspr r0, dsisr mfspr r0, dsisr
stw r0, KDP.CrashDSISR(r1) stw r0, KDP.CrashDSISR(r1)
mfspr r0, dar mfspr r0, dar
stw r0, KDP.CrashDAR(r1) stw r0, KDP.CrashDAR(r1)
mfspr r0, rtcu mfspr r0, rtcu
stw r0, KDP.CrashRTCU(r1) stw r0, KDP.CrashRTCU(r1)
mfspr r0, rtcl mfspr r0, rtcl
stw r0, KDP.CrashRTCL(r1) stw r0, KDP.CrashRTCL(r1)
mfspr r0, dec mfspr r0, dec
stw r0, KDP.CrashDEC(r1) stw r0, KDP.CrashDEC(r1)
mfspr r0, hid0 mfspr r0, hid0
stw r0, KDP.CrashHID0(r1) stw r0, KDP.CrashHID0(r1)
mfspr r0, sdr1 mfspr r0, sdr1
stw r0, KDP.CrashSDR1(r1) stw r0, KDP.CrashSDR1(r1)
mfsrr0 r0 mfsrr0 r0
stw r0, KDP.CrashSRR0(r1) stw r0, KDP.CrashSRR0(r1)
mfsrr1 r0 mfsrr1 r0
stw r0, KDP.CrashSRR1(r1) stw r0, KDP.CrashSRR1(r1)
mfmsr r0 mfmsr r0
stw r0, KDP.CrashMSR(r1) stw r0, KDP.CrashMSR(r1)
mfsr r0, 0 mfsr r0, 0
stw r0, KDP.CrashSR0(r1) stw r0, KDP.CrashSR0(r1)
mfsr r0, 1 mfsr r0, 1
stw r0, KDP.CrashSR1(r1) stw r0, KDP.CrashSR1(r1)
mfsr r0, 2 mfsr r0, 2
stw r0, KDP.CrashSR2(r1) stw r0, KDP.CrashSR2(r1)
mfsr r0, 3 mfsr r0, 3
stw r0, KDP.CrashSR3(r1) stw r0, KDP.CrashSR3(r1)
mfsr r0, 4 mfsr r0, 4
stw r0, KDP.CrashSR4(r1) stw r0, KDP.CrashSR4(r1)
mfsr r0, 5 mfsr r0, 5
stw r0, KDP.CrashSR5(r1) stw r0, KDP.CrashSR5(r1)
mfsr r0, 6 mfsr r0, 6
stw r0, KDP.CrashSR6(r1) stw r0, KDP.CrashSR6(r1)
mfsr r0, 7 mfsr r0, 7
stw r0, KDP.CrashSR7(r1) stw r0, KDP.CrashSR7(r1)
mfsr r0, 8 mfsr r0, 8
stw r0, KDP.CrashSR8(r1) stw r0, KDP.CrashSR8(r1)
mfsr r0, 9 mfsr r0, 9
stw r0, KDP.CrashSR9(r1) stw r0, KDP.CrashSR9(r1)
mfsr r0, 10 mfsr r0, 10
stw r0, KDP.CrashSR10(r1) stw r0, KDP.CrashSR10(r1)
mfsr r0, 11 mfsr r0, 11
stw r0, KDP.CrashSR11(r1) stw r0, KDP.CrashSR11(r1)
mfsr r0, 12 mfsr r0, 12
stw r0, KDP.CrashSR12(r1) stw r0, KDP.CrashSR12(r1)
mfsr r0, 13 mfsr r0, 13
stw r0, KDP.CrashSR13(r1) stw r0, KDP.CrashSR13(r1)
mfsr r0, 14 mfsr r0, 14
stw r0, KDP.CrashSR14(r1) stw r0, KDP.CrashSR14(r1)
mfsr r0, 15 mfsr r0, 15
stw r0, KDP.CrashSR15(r1) stw r0, KDP.CrashSR15(r1)
mfmsr r0 mfmsr r0
_set r0, r0, bitMsrFP _set r0, r0, bitMsrFP
mtmsr r0 mtmsr r0
stfd f0, KDP.CrashF0(r1) stfd f0, KDP.CrashF0(r1)
stfd f1, KDP.CrashF1(r1) stfd f1, KDP.CrashF1(r1)
stfd f2, KDP.CrashF2(r1) stfd f2, KDP.CrashF2(r1)
stfd f3, KDP.CrashF3(r1) stfd f3, KDP.CrashF3(r1)
stfd f4, KDP.CrashF4(r1) stfd f4, KDP.CrashF4(r1)
stfd f5, KDP.CrashF5(r1) stfd f5, KDP.CrashF5(r1)
stfd f6, KDP.CrashF6(r1) stfd f6, KDP.CrashF6(r1)
stfd f7, KDP.CrashF7(r1) stfd f7, KDP.CrashF7(r1)
stfd f8, KDP.CrashF8(r1) stfd f8, KDP.CrashF8(r1)
stfd f9, KDP.CrashF9(r1) stfd f9, KDP.CrashF9(r1)
stfd f10, KDP.CrashF10(r1) stfd f10, KDP.CrashF10(r1)
stfd f11, KDP.CrashF11(r1) stfd f11, KDP.CrashF11(r1)
stfd f12, KDP.CrashF12(r1) stfd f12, KDP.CrashF12(r1)
stfd f13, KDP.CrashF13(r1) stfd f13, KDP.CrashF13(r1)
stfd f14, KDP.CrashF14(r1) stfd f14, KDP.CrashF14(r1)
stfd f15, KDP.CrashF15(r1) stfd f15, KDP.CrashF15(r1)
stfd f16, KDP.CrashF16(r1) stfd f16, KDP.CrashF16(r1)
stfd f17, KDP.CrashF17(r1) stfd f17, KDP.CrashF17(r1)
stfd f18, KDP.CrashF18(r1) stfd f18, KDP.CrashF18(r1)
stfd f19, KDP.CrashF19(r1) stfd f19, KDP.CrashF19(r1)
stfd f20, KDP.CrashF20(r1) stfd f20, KDP.CrashF20(r1)
stfd f21, KDP.CrashF21(r1) stfd f21, KDP.CrashF21(r1)
stfd f22, KDP.CrashF22(r1) stfd f22, KDP.CrashF22(r1)
stfd f23, KDP.CrashF23(r1) stfd f23, KDP.CrashF23(r1)
stfd f24, KDP.CrashF24(r1) stfd f24, KDP.CrashF24(r1)
stfd f25, KDP.CrashF25(r1) stfd f25, KDP.CrashF25(r1)
stfd f26, KDP.CrashF26(r1) stfd f26, KDP.CrashF26(r1)
stfd f27, KDP.CrashF27(r1) stfd f27, KDP.CrashF27(r1)
stfd f28, KDP.CrashF28(r1) stfd f28, KDP.CrashF28(r1)
stfd f29, KDP.CrashF29(r1) stfd f29, KDP.CrashF29(r1)
stfd f30, KDP.CrashF30(r1) stfd f30, KDP.CrashF30(r1)
stfd f31, KDP.CrashF31(r1) stfd f31, KDP.CrashF31(r1)
mffs f31 mffs f31
lwz r0, KDP.CrashF31+4(r1) lwz r0, KDP.CrashF31+4(r1)
stfd f31, KDP.CrashF31+4(r1) stfd f31, KDP.CrashF31+4(r1)
stw r0, KDP.CrashF31+4(r1) stw r0, KDP.CrashF31+4(r1)
mflr r0 mflr r0
stw r0, KDP.CrashKernReturn(r1) stw r0, KDP.CrashKernReturn(r1)
######################################################################## ########################################################################
lis r2, 2 ; Count down from 64k to find a zero lis r2, 2 ; Count down from 64k to find a zero
@nonzero @nonzero
lwzu r0, -4(r2) lwzu r0, -4(r2)
mr. r2, r2 mr. r2, r2
bne @nonzero bne @nonzero
@retryrtc ; Save RTC in "Mac/Smurf shared message mem" @retryrtc ; Save RTC in "Mac/Smurf shared message mem"
mfspr r2, rtcu mfspr r2, rtcu
mfspr r3, rtcl mfspr r3, rtcl
mfspr r0, rtcu mfspr r0, rtcu
xor. r0, r0, r2 xor. r0, r0, r2
bne @retryrtc bne @retryrtc
lwz r1, KDP.SharedMemoryAddr(r1) lwz r1, KDP.SharedMemoryAddr(r1)
stw r2, 0(r1) stw r2, 0(r1)
ori r3, r3, 1 ori r3, r3, 1
stw r3, 4(r1) stw r3, 4(r1)
dcbf 0, r1 dcbf 0, r1
sync sync
@loopforever @loopforever
lwz r1, 0(0) lwz r1, 0(0)
addi r1, r1, 1 addi r1, r1, 1
stw r1, 0(0) stw r1, 0(0)
li r1, 0 li r1, 0
dcbst r1, r1 dcbst r1, r1
b @loopforever b @loopforever

38
NanoKernel/NanoKernel.s
View File

@ -1,26 +1,26 @@
include 'InfoRecords.a' include 'InfoRecords.a'
include 'NKStructs.s' include 'NKStructs.s'
include 'NKEquates.s' include 'NKEquates.s'
include 'NKMacros.s' include 'NKMacros.s'
CodeBase CodeBase
include 'NKInit.s' include 'NKInit.s'
include 'NKSystemCrash.s' include 'NKSystemCrash.s'
include 'NKHotInts.s' include 'NKHotInts.s'
_align 10 _align 10
MRBase MRBase
include 'MROptabCode.s' ; c00:1154 include 'MROptabCode.s'
include 'MRMemtabCode.s' ; 1154:13f4 include 'MRMemtabCode.s'
include 'MRInterrupts.s' ; 13f4:14f4 include 'MRInterrupts.s'
include 'MROptab.s' ; 14f4:16f4 include 'MROptab.s'
include 'MRMemtab.s' ; 16f4:17f4 include 'MRMemtab.s'
include 'MRRestab.s' ; 17f4:1874 include 'MRRestab.s'
include 'NKColdInts.s' include 'NKColdInts.s'
include 'NKMemory.s' include 'NKMemory.s'
include 'NKExceptions.s' include 'NKExceptions.s'
include 'NKFloatingPt.s' include 'NKFloatingPt.s'
include 'NKSoftInts.s' include 'NKSoftInts.s'
include 'NKLegacyVM.s' include 'NKLegacyVM.s'