Initial commit

This commit is contained in:
Elliot Nunn 2017-11-19 12:11:07 +08:00
commit c5c5b784cb
47 changed files with 39524 additions and 0 deletions

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.DS_Store
BuildResults/
*.NJ
*.tool
RomMondo.bin.x
*.dmg

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; ROM version of NKConfigurationInfo struct, based on Mac OS ROM 8=9=10.
; Lives at ROM + 0x30d000 (and other addresses on OldWorld).
; From start of ConfigInfo to end of LoMemInit = 4k:
; Auto-align fields
aligning on
import RomTop, RomBtm
import Mac68kRomTop, Mac68kRomBtm
import ExTblTop
import NKTop
import EmTop, EmBtm, EmEntry, EmKernelTrapTable
import OpcodeTblTop, OpcodeTblBtm
ConfigInfo
; These sums are not checked on NewWorld, but :Tools:ToolSource:RiscLayout.c calcs them anyway
dcb.l 8, 0 ; 000 ; ROMByteCheckSums ; ROM Checksums - one word for each of 8 byte lanes
dcb.l 2, 0 ; 020 ; ROMCheckSum64 ; ROM Checksum - 64 bit sum of doublewords
dc.l RomTop-ConfigInfo ; 028 ; ROMImageBaseOffset ; Offset of Base of total ROM image
dc.l RomBtm-RomTop ; 02c ; ROMImageSize ; Number of bytes in ROM image
dc.l 0 ; 030 ; ROMImageVersion ; ROM Version number for entire ROM
; ROM component Info (offsets are from base of ConfigInfo page)
dc.l Mac68kRomTop-ConfigInfo ; 034 ; Mac68KROMOffset ; Offset of base of Macintosh 68K ROM
dc.l Mac68kRomBtm-Mac68kRomTop ; 038 ; Mac68KROMSize ; Number of bytes in Macintosh 68K ROM
dc.l ExTblTop-ConfigInfo ; 03c ; ExceptionTableOffset ; Offset of base of PowerPC Exception Table Code
dc.l 0xc000 ; 040 ; ExceptionTableSize ; Number of bytes in PowerPC Exception Table Code (generous)
dc.l RomTop+0x320000-ConfigInfo ; 044 ; HWInitCodeOffset ; Offset of base of Hardware Init Code (no longer exists)
dc.l 0x10000 ; 048 ; HWInitCodeSize ; Number of bytes in Hardware Init Code
dc.l NKTop-ConfigInfo ; 04c ; KernelCodeOffset ; Offset of base of NanoKernel Code
dc.l 0x10000 ; 050 ; KernelCodeSize ; Number of bytes in NanoKernel Code (too small)
dc.l EmTop-ConfigInfo ; 054 ; EmulatorCodeOffset ; Offset of base of Emulator Code
dc.l EmBtm-EmTop ; 058 ; EmulatorCodeSize ; Number of bytes in Emulator Code
dc.l OpcodeTblTop-ConfigInfo ; 05c ; OpcodeTableOffset ; Offset of base of Opcode Table
dc.l OpcodeTblBtm-OpcodeTblTop ; 060 ; OpcodeTableSize ; Number of bytes in Opcode Table
; Offsets within the Emulator Data Page.
string AsIs
@s dc.b 'NewWorld v1.0' ; 064 ; BootstrapVersion ; Bootstrap loader version info
org @s + 16
dc.l 0xf00 ; 074 ; BootVersionOffset ; offset within EmulatorData of BootstrapVersion
dc.l 0x100 ; 078 ; ECBOffset ; offset within EmulatorData of ECB
dc.l 0x070 ; 07c ; IplValueOffset ; offset within EmulatorData of IplValue
; Offsets within the Emulator Code.
dc.l EmEntry-EmTop ; 080 ; EmulatorEntryOffset ; offset within Emulator Code of entry point
dc.l EmKernelTrapTable-EmTop ; 084 ; KernelTrapTableOffset ; offset within Emulator Code of KernelTrapTable
; Interrupt Passing Masks.
dc.l 0x00200000 ; 088 ; TestIntMaskInit ; initial value for test interrupt mask
dc.l 0xff9fffff ; 08c ; ClearIntMaskInit ; initial value for clear interrupt mask
dc.l 0x00e00000 ; 090 ; PostIntMaskInit ; initial value for post interrupt mask
dc.l 0x808e0000 ; 094 ; LA_InterruptCtl ; logical address of Interrupt Control I/O page
dc.b 6 ; 098 ; InterruptHandlerKind ; kind of handler to use
dc.l 0x5fffe000 ; 09c ; LA_InfoRecord ; logical address of InfoRecord page
dc.l 0x68ffe000 ; 0a0 ; LA_KernelData ; logical address of KernelData page
dc.l 0x68fff000 ; 0a4 ; LA_EmulatorData ; logical address of EmulatorData page
dc.l 0x68080000 ; 0a8 ; LA_DispatchTable ; logical address of Dispatch Table
dc.l 0x68060000 ; 0ac ; LA_EmulatorCode ; logical address of Emulator Code
dc.l LowMemVals-ConfigInfo ; 0b0 ; MacLowMemInitOffset ; offset to list of LowMem addr/data values
;
; Then the pagemap init stuff is filled by the trampoline at boot
;
; Address Space Mapping
dc.l 0 ; 0b4 ; PageAttributeInit ; default WIMG, PP settings for PTE creation
dc.l 0 ; 0b8 ; PageMapInitSize ; size of page mapping info
dc.l 0 ; 0bc ; PageMapInitOffset ; offset to page mapping info (from base of ConfigInfo)
dc.l 0 ; 0c0 ; PageMapIRPOffset ; offset of InfoRecord map info (from base of PageMap)
dc.l 0 ; 0c4 ; PageMapKDPOffset ; offset of KernelData map info (from base of PageMap)
dc.l 0 ; 0c8 ; PageMapEDPOffset ; offset of EmulatorData map info (from base of PageMap)
dcb.l 32, 0 ; 0cc ; SegMap32SupInit ; 32 bit mode Segment Map Supervisor space
dcb.l 32, 0 ; 14c ; SegMap32UsrInit ; 32 bit mode Segment Map User space
dcb.l 32, 0 ; 1cc ; SegMap32CPUInit ; 32 bit mode Segment Map CPU space
dcb.l 32, 0 ; 24c ; SegMap32OvlInit ; 32 bit mode Segment Map Overlay mode
dcb.l 32, 0 ; 2cc ; BATRangeInit ; BAT mapping ranges
dc.l 0 ; 34c ; BatMap32SupInit ; 32 bit mode BAT Map Supervisor space
dc.l 0 ; 350 ; BatMap32UsrInit ; 32 bit mode BAT Map User space
dc.l 0 ; 354 ; BatMap32CPUInit ; 32 bit mode BAT Map CPU space
dc.l 0 ; 358 ; BatMap32OvlInit ; 32 bit mode BAT Map Overlay mode
; Only needed for Smurf
dc.l 0 ; 35c ; SharedMemoryAddr ; physical address of Mac/Smurf shared message mem
dc.l -1 ; 360 ; PA_RelocatedLowMemInit ; physical address of RelocatedLowMem
dc.l 0x330000 - 0x30d000 ; 364 ; OpenFWBundleOffset ; Offset of base of OpenFirmware PEF Bundle
dc.l 0x20000 ; 368 ; OpenFWBundleSize ; Number of bytes in OpenFirmware PEF Bundle
dc.l 0xff800000 ; 36c ; LA_OpenFirmware ; logical address of Open Firmware
dc.l 0x00400000 ; 370 ; PA_OpenFirmware ; physical address of Open Firmware
dc.l 0xfff0c000 ; 374 ; LA_HardwarePriv ; logical address of HardwarePriv callback
; There are still some fixed-location fields here that the Trampoline will populate,
; but the ROM we are building contains just zeros.
;
; Key/value pairs for initializing Low Memory Globals.
; (at the end of ConfigInfo's 4k max size)
;
; A wee little macro to write LoMem key/value pairs *below* the asm location counter
macro
LowMem &addr, &val
@b
org @b - 4
dc.l &val
org @b - 8
dc.l &addr
org @b - 8
endm
; Sentinel zero at end (late address) of list
org 4096 - 4
dc.l 0
org 4096 - 4
; The table (older RISC versions have more in here.)
; The 68k emulator's cold-start vector, points to a "JMP StartBoot"
; instruction in the 68k ROM header. (Normally this value would be
; read from the ROM while it was overlaid on RAM at cold start, but
; why emulate that on a PowerPC?)
; SheepShaver patches the 68k reset vector around this location,
; but assumed offset 0xfd8.
LowMem 0x00000004, 0xffc0002a
LowMemVals

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Set Parent "`Files -f "{0}" | StreamEdit -d -e '/((Å:)*)¨1([Â:]*)/ Print ¨1'`"
SetDirectory "{Parent}" # too easy
Make -w > :BuildResults:BuildOut
:BuildResults:BuildOut

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Emulator.x Normal file

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EDP record 0,INCR
org 0x70
IplValue ds.w 1 ; 070 ; 68k int level or -1
org 0x100
ContextBlock ds.b 768 ; 100:300 ; Emulator Context Block, ECB; NKv2 ties this to blue task
org 0xf00
BootstrapVersion ds.b 16 ; f00:f10 ; Bootstrap loader version info, from ConfigInfo
endr
; Lives in EDP. Keeping a separate record to EDP makes the code nicer.
; Gets called the "system context"
ContextBlock record 0,INCR
EmpiricalCpuFeatures ds.l 1 ; 000 ; (SPAC) copied from kdp by CreateTask
org 0x5c
LA_EmulatorKernelTrapTable ds.l 1
org 0x84
LA_EmulatorEntry ds.l 1 ; 084 ; Entry pt of emulator; set by NK Init.s
org 0x94
LA_EmulatorData ds.l 1
org 0x9c
LA_DispatchTable ds.l 1
org 0xa4
MSR ds.l 1 ; 0a4 ; (SPAC) copied from kdp by CreateTask
org 0xc4
MQ ds.l 1 ; 0c4 ; 601 only
ds.l 1
PriorityShifty ds.l 1 ; 0cc ; if low nybble is empty, InitRDYQs sets this to 2
org 0xd4
XER ds.l 1
VectorSaveArea ds.l 1 ; 0d8 ; AltiVec hack: vector registers don't fit in CB!
org 0xe0
PageInSystemHeap ds.l 1 ; 0e0 ; these are set by StartInit.a:FiddleWithEmulator
OtherPageInSystemHeap ds.l 1 ; 0e4
FE000000 ds.l 1 ; 0e8
Zero ds.l 1 ; 0ec
org 0xfc
CodePtr ds.l 1 ; 0fc ; probably goes in SRR0?
org 0x100
ds.l 1
r0 ds.l 1 ; 104
ds.l 1
r1 ds.l 1 ; 10c
ds.l 1
r2 ds.l 1 ; 114
ds.l 1
r3 ds.l 1 ; 11c
ds.l 1
r4 ds.l 1 ; 124
ds.l 1
r5 ds.l 1 ; 12c
ds.l 1
r6 ds.l 1 ; 134
ds.l 1
r7 ds.l 1 ; 13c
ds.l 1
r8 ds.l 1 ; 144
ds.l 1
r9 ds.l 1 ; 14c
ds.l 1
r10 ds.l 1 ; 154
ds.l 1
r11 ds.l 1 ; 15c
ds.l 1
r12 ds.l 1 ; 164
ds.l 1
r13 ds.l 1 ; 16c
ds.l 1
r14 ds.l 1 ; 174
ds.l 1
r15 ds.l 1 ; 17c
ds.l 1
r16 ds.l 1 ; 184
ds.l 1
r17 ds.l 1 ; 18c
ds.l 1
r18 ds.l 1 ; 194
ds.l 1
r19 ds.l 1 ; 19c
ds.l 1
r20 ds.l 1 ; 1a4
ds.l 1
r21 ds.l 1 ; 1ac
ds.l 1
r22 ds.l 1 ; 1b4
ds.l 1
r23 ds.l 1 ; 1bc
ds.l 1
r24 ds.l 1 ; 1c4
ds.l 1
r25 ds.l 1 ; 1cc
ds.l 1
r26 ds.l 1 ; 1d4
ds.l 1
r27 ds.l 1 ; 1dc
ds.l 1
r28 ds.l 1 ; 1e4
ds.l 1
r29 ds.l 1 ; 1ec
ds.l 1
r30 ds.l 1 ; 1f4
ds.l 1
r31 ds.l 1 ; 1fc
FloatRegisters ds.d 32 ; 200:300
endr

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;_______________________________________________________________________
; Configuration Info Record
; Used to pass Configuration information from the Boot Program to the
; NanoKernel for data structure and address mapping initialization.
;_______________________________________________________________________
NKConfigurationInfo record 0,increment
ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes
ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords
ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image
ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image
ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM
Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM
Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM
ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code
ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code
HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!)
HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code
KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code
KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code
EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code
EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code
OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table
OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table
BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info
BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion
ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB
IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue
EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point
KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable
TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask
ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask
PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask
LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page
InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use
ds.b 3 ; 099 ; filler
LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page
LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page
LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page
LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table
LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code
MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values
PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation
PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info
PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo)
PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap)
PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap)
PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap)
SegMaps
SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space
SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space
SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space
SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode
BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges
BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space
BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space
BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space
BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode
SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem
PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem
OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle
OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle
LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware
PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware
LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback
; Used to stop here, plus 8 bytes for cache block alignment (0x380 bytes).
; Now there be more!
Debug ds.w 1 ; 378 ; > 256 required for screen log
DebugThreshold equ 257
org 0x388
DebugFlags ds.l 1 ; 388 ; bit 1<< 1 required for screen log
NanodbgrFlagShift equ 0
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
LogFlagShift equ 1
LogFlagBit equ 31 - LogFlagShift
endr
;_______________________________________________________________________
; System Info Record
;
; Used to pass System information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record
NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record
NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record
NKSystemInfo record 0,increment
PhysicalMemorySize ds.l 1 ; 000, irp+dc0 ; Number of bytes in Physical RAM
UsableMemorySize ds.l 1 ; 004, irp+dc4 ; Number of bytes in Usable RAM
LogicalMemorySize ds.l 1 ; 008, irp+dc8 ; Number of bytes in Logical RAM
HashTableSize ds.l 1 ; 00c, irp+dcc ; Number of bytes in Memory Hash Table
L2DataCacheTotalSize ds.l 1 ; 010, irp+dd0 ; number of bytes in the L2 Data Cache
L2InstCacheTotalSize ds.l 1 ; 014, irp+dd4 ; number of bytes in the L2 Instruction Cache
L2CombinedCaches ds.w 1 ; 018, irp+dd8 ; 1 <- combined or no cache, 0 <- split cache
L2InstCacheBlockSize ds.w 1 ; 01a, irp+dda ; number of bytes in a Block of the L2 Instruction Cache
L2DataCacheBlockSize ds.w 1 ; 01c, irp+ddc ; number of bytes in a Block of the L2 Data Cache
L2InstCacheAssociativity ds.w 1 ; 01e, irp+dde ; Associativity of the L2 Instruction Cache
L2DataCacheAssociativity ds.w 1 ; 020, irp+de0 ; Associativity of the L2 Data Cache
ds.b 2 ; 022, irp+de2 ; unused
ds.b 2 ; 024, irp+de4 ; unused
FlashManufacturerCode ds.b 1 ; 026, irp+de6 ; Flash ROM Manufacturer code
FlashDeviceCode ds.b 1 ; 027, irp+de7 ; Flash ROM Device code
FlashStart ds.l 1 ; 028, irp+de8 ; Starting address of Flash ROM
FlashSize ds.l 1 ; 02c, irp+dec ; Number of bytes in Flash ROM
Bank0Start ds.l 1 ; 030, irp+df0 ; Starting address of RAM bank 0
Bank0Size ds.l 1 ; 034, irp+df4 ; Number of bytes in RAM bank 0
Bank1Start ds.l 1 ; 038, irp+df8 ; Starting address of RAM bank 1
Bank1Size ds.l 1 ; 03c, irp+dfc ; Number of bytes in RAM bank 1
Bank2Start ds.l 1 ; 040, irp+e00 ; Starting address of RAM bank 2
Bank2Size ds.l 1 ; 044, irp+e04 ; Number of bytes in RAM bank 2
Bank3Start ds.l 1 ; 048, irp+e08 ; Starting address of RAM bank 3
Bank3Size ds.l 1 ; 04c, irp+e0c ; Number of bytes in RAM bank 3
Bank4Start ds.l 1 ; 050, irp+e10 ; Starting address of RAM bank 4
Bank4Size ds.l 1 ; 054, irp+e14 ; Number of bytes in RAM bank 4
Bank5Start ds.l 1 ; 058, irp+e18 ; Starting address of RAM bank 5
Bank5Size ds.l 1 ; 05c, irp+e1c ; Number of bytes in RAM bank 5
Bank6Start ds.l 1 ; 060, irp+e20 ; Starting address of RAM bank 6
Bank6Size ds.l 1 ; 064, irp+e24 ; Number of bytes in RAM bank 6
Bank7Start ds.l 1 ; 068, irp+e28 ; Starting address of RAM bank 7
Bank7Size ds.l 1 ; 06c, irp+e2c ; Number of bytes in RAM bank 7
Bank8Start ds.l 1 ; 070, irp+e30 ; Starting address of RAM bank 8
Bank8Size ds.l 1 ; 074, irp+e34 ; Number of bytes in RAM bank 8
Bank9Start ds.l 1 ; 078, irp+e38 ; Starting address of RAM bank 9
Bank9Size ds.l 1 ; 07c, irp+e3c ; Number of bytes in RAM bank 9
Bank10Start ds.l 1 ; 080, irp+e40 ; Starting address of RAM bank 10
Bank10Size ds.l 1 ; 084, irp+e44 ; Number of bytes in RAM bank 10
Bank11Start ds.l 1 ; 088, irp+e48 ; Starting address of RAM bank 11
Bank11Size ds.l 1 ; 08c, irp+e4c ; Number of bytes in RAM bank 11
Bank12Start ds.l 1 ; 090, irp+e50 ; Starting address of RAM bank 12
Bank12Size ds.l 1 ; 094, irp+e54 ; Number of bytes in RAM bank 12
Bank13Start ds.l 1 ; 098, irp+e58 ; Starting address of RAM bank 13
Bank13Size ds.l 1 ; 09c, irp+e5c ; Number of bytes in RAM bank 13
Bank14Start ds.l 1 ; 0a0, irp+e60 ; Starting address of RAM bank 14
Bank14Size ds.l 1 ; 0a4, irp+e64 ; Number of bytes in RAM bank 14
Bank15Start ds.l 1 ; 0a8, irp+e68 ; Starting address of RAM bank 15
Bank15Size ds.l 1 ; 0ac, irp+e6c ; Number of bytes in RAM bank 15
Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16
Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16
Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17
Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17
Bank18Start ds.l 1 ; 0c0, irp+e80 ; Starting address of RAM bank 18
Bank18Size ds.l 1 ; 0c4, irp+e84 ; Number of bytes in RAM bank 18
Bank19Start ds.l 1 ; 0c8, irp+e88 ; Starting address of RAM bank 19
Bank19Size ds.l 1 ; 0cc, irp+e8c ; Number of bytes in RAM bank 19
Bank20Start ds.l 1 ; 0d0, irp+e90 ; Starting address of RAM bank 20
Bank20Size ds.l 1 ; 0d4, irp+e94 ; Number of bytes in RAM bank 20
Bank21Start ds.l 1 ; 0d8, irp+e98 ; Starting address of RAM bank 21
Bank21Size ds.l 1 ; 0dc, irp+e9c ; Number of bytes in RAM bank 21
Bank22Start ds.l 1 ; 0e0, irp+ea0 ; Starting address of RAM bank 22
Bank22Size ds.l 1 ; 0e4, irp+ea4 ; Number of bytes in RAM bank 22
Bank23Start ds.l 1 ; 0e8, irp+ea8 ; Starting address of RAM bank 23
Bank23Size ds.l 1 ; 0ec, irp+eac ; Number of bytes in RAM bank 23
Bank24Start ds.l 1 ; 0f0, irp+eb0 ; Starting address of RAM bank 24
Bank24Size ds.l 1 ; 0f4, irp+eb4 ; Number of bytes in RAM bank 24
Bank25Start ds.l 1 ; 0f8, irp+eb8 ; Starting address of RAM bank 25
Bank25Size ds.l 1 ; 0fc, irp+ebc ; Number of bytes in RAM bank 25
EndOfBanks
MaxBanks equ 26 ; Pads out to old struct len (cache block), more to come...
; Interrupt Support Data
IntCntrBaseAddr ds.l 1 ; 100, irp+ec0 ; Interrupt Controller Base Address (variable is used since this is a PCI Dev and address is relocatable)
IntPendingReg ds.l 2 ; 104, irp+ec4 ; Data of current interrupts pending register
; These fields were added to report information about tightly-coupled L2 caches.
; The inline L2 information should be used in situations where there is a CPU
; card L2 cache that can coexist with a motherboard L2.
InlineL2DSize ds.l 1 ; 10c, irp+ecc ; Size of in-line L2 Dcache
InlineL2ISize ds.l 1 ; 110, irp+ed0 ; Size of in-line L2 Icache
InlineL2Combined ds.w 1 ; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache
InlineL2IBlockSize ds.w 1 ; 116, irp+ed6 ; Block size of in-line I L2 cache
InlineL2DBlockSize ds.w 1 ; 118, irp+ed8 ; Block size of in-line D L2 cache
InlineL2IAssoc ds.w 1 ; 11a, irp+eda ; Associativity of L2 I
InlineL2DAssoc ds.w 1 ; 11c, irp+edc ; Associativity of L2 D
ds.w 1 ; 11e, irp+ede ; pad
; More Interrupt Support Data
IntsCompleted ds.l 2 ; 120, irp+ee0 ; completed interrupts
align 5 ; pad to nice cache block alignment
endr
;_______________________________________________________________________
; Diagnostic Info Record
;
; Used to pass Diagnostic information from the power on Diagnostics to
; the NanoKernel, and from the NanoKernel to user mode software.
;_______________________________________________________________________
NKDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record
NKDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record
NKDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record
NKDiagInfo record 0,increment
BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code
BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code
BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code
BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code
BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code
BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code
BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code
BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code
BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code
CacheFailOffset ds.l 1 ; 024 ; cache failure code
LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be
POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took
POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag
POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag
POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record
POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb
POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST
POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST
POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST
POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST
POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here
POSTError2Offset ds.l 1 ; 054 ; result codes from tests
POSTError3Offset ds.l 1 ; 058 ; result codes from tests
POSTError4Offset ds.l 1 ; 05c ; result codes from tests
RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size.
; Everything BEFORE here is new (hence the funny-sized register store)
DiagPOSTResult2 ds.l 1 ; 0ec ; POST results
DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results
DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag
DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) <SM44>
DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) <SM44>
align 5 ; pad to nice cache block alignment
endr
;_______________________________________________________________________
; NanoKernel Info Record
;
; Used to pass NanoKernel statistics from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record
NKNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record
NKNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record
NKNanoKernelInfo record 0,increment
ExceptionCauseCounts ds.l 32 ; 000, kdp+dc0 ; counters per exception cause
NanoKernelCallCounts ds.l 16 ; 080, kdp+e40 ; counters per NanoKernel call
ExternalIntCount ds.l 1 ; 0c0, kdp+e80 ; count of External Interrupts
MisalignmentCount ds.l 1 ; 0c4, kdp+e84 ; count of Misalignment Interrupts
FPUReloadCount ds.l 1 ; 0c8, kdp+e88 ; count of FPU reloads on demand
DecrementerIntCount ds.l 1 ; 0cc, kdp+e8c ; count of Decrementer Interrupts
QuietWriteCount ds.l 1 ; 0d0, kdp+e90 ; count of Writes to Quiet Read-Only memory
HashTableCreateCount ds.l 1 ; 0d4, kdp+e94 ; count of Hash Table Entry creations
HashTableDeleteCount ds.l 1 ; 0d8, kdp+e98 ; count of Hash Table Entry deletions
HashTableOverflowCount ds.l 1 ; 0dc, kdp+e9c ; count of Hash Table Entry overflows
EmulatedUnimpInstCount ds.l 1 ; 0e0, kdp+ea0 ; count of Emulated unimplemented instructions
NCBPtrCacheMissCount ds.l 1 ; 0e4, kdp+ea4 ; count of NCB Pointer cache misses
ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated to system
ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system
SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context
AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context
; This stuff is new (starts at 0x100)
blueProcessID ds.l 1 ; 100, kdp+ec0 ; ID of the blue process.
blueTaskID ds.l 1 ; 104, kdp+ec4 ; ID of the blue task.
pageQueueID ds.l 1 ; 108, kdp+ec8 ; ID of the page fault queue.
TaskCount ds.l 1 ; 10c, kdp+ecc ; Number of tasks.
FreePoolExtendCount ds.l 1 ; 110, kdp+ed0 ; Number of pages given to the nanokernel.
;rsrv1 ds.l 3 ; 114, kdp+ed4 ; reserved???
; My additions
org 0x11c
ConfigFlags ds.l 1 ; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here
NanodbgrFlagShift equ 1
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
LogFlagShift equ 3
LogFlagBit equ 31 - LogFlagShift
; bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later
org 0x128
VMDispatchCountTblPtr ds.l 1 ; 128, kdp+ee8
ds.l 1
ds.l 1
MPDispatchCountTblPtr ds.l 1 ; 134, kdp+ef4 ; ???????
AddrSpcSetCtr ds.l 1 ; 138, kdp+ef8 ; incremented by SetAddrSpcRegisters
IDCtr ds.l 1 ; 13c, kdp+efc
org 0x160
endr
;_______________________________________________________________________
; Processor Info Record
;
; Used to pass Processor information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record
NKProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record
NKProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record
NKProcessorInfo record 0,increment
ProcessorVersionReg ds.l 1 ; 000, kdp+f20 ; contents of the PVR special purpose register
CpuClockRateHz ds.l 1 ; 004, kdp+f24 ; CPU Clock frequency
BusClockRateHz ds.l 1 ; 008, kdp+f28 ; Bus Clock frequency
DecClockRateHz ds.l 1 ; 00c, kdp+f2c ; Decrementer Clock frequency
Ovr
PageSize ds.l 1 ; 010, kdp+f30 ; number of bytes in a memory page
DataCacheTotalSize ds.l 1 ; 014, kdp+f34 ; number of bytes in the Data Cache
InstCacheTotalSize ds.l 1 ; 018, kdp+f38 ; number of bytes in the Instruction Cache
CoherencyBlockSize ds.w 1 ; 01c, kdp+f3c ; number of bytes in a Coherency Block
ReservationGranuleSize ds.w 1 ; 01e, kdp+f3e ; number of bytes in a Reservation Granule
CombinedCaches ds.w 1 ; 020, kdp+f40 ; 1 <- combined or no cache, 0 <- split cache
InstCacheLineSize ds.w 1 ; 022, kdp+f42 ; number of bytes in a Line of the Instruction Cache
DataCacheLineSize ds.w 1 ; 024, kdp+f44 ; number of bytes in a Line of the Data Cache
DataCacheBlockSizeTouch ds.w 1 ; 026, kdp+f46 ; number of bytes in a Block for DCBT DCBTST
InstCacheBlockSize ds.w 1 ; 028, kdp+f48 ; number of bytes in a Block of the Instruction Cache
DataCacheBlockSize ds.w 1 ; 02a, kdp+f4a ; number of bytes in a Block of the Data Cache
InstCacheAssociativity ds.w 1 ; 02c, kdp+f4c ; Associativity of the Instruction Cache
DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache
TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache
TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache
OvrEnd
; These fields were added to report information about back-side L2 caches
ProcessorL2DSize ds.l 1 ; 034, kdp+f54 ; Size of back-side L2 Dcache
ProcessorL2ISize ds.l 1 ; 038, kdp+f58 ; Size of back-side L2 Icache
ProcessorL2Combined ds.w 1 ; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache
ProcessorL2IBlockSize ds.w 1 ; 03e, kdp+f5e ; Block size of back-side I L2 cache
ProcessorL2DBlockSize ds.w 1 ; 040, kdp+f60 ; Block size of back-side D L2 cache
ProcessorL2IAssoc ds.w 1 ; 042, kdp+f62 ; Associativity of L2 I
ProcessorL2DAssoc ds.w 1 ; 044, kdp+f64 ; Associativity of L2 D
filler1 ds.w 1 ; 046, kdp+f66 ; align to long
; ProcessorFlags - Definitions for the processor flags field. These are bit positions,
; as in 1 << hasVMX, and not masks.
hasL2CR equ 0
hasPLRUL1 equ 1
hasTAU equ 2
hasVMX equ 3
unknownFlag equ 4
hasExtraBATs equ 5
ProcessorFlags ds.l 1 ; 048, kdp+f68 ; flags to specify processor features
align 5 ; pad to nice cache block alignment
org 0x05e
SetToZero ds.w 1 ; 05e, kdp+f7e ; by same code that sets below
CpuClockRateHzCopy ds.l 1 ; 060, kdp+f80 ; copies by Init.s
BusClockRateHzCopy ds.l 1 ; 064, kdp+f84 ; copies by Init.s
DecClockRateHzCopy ds.l 1 ; 068, kdp+f88 ; copies by Init.s
endr
;_______________________________________________________________________
; Hardware Info Record
;
; Used to pass hardware information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKHWInfoPtr equ $5FFFEFD0 ; logical address of HWInfo record
NKHWInfoVer equ $5FFFEFD4 ; version number of HWInfo record
NKHWInfoLen equ $5FFFEFD6 ; length of HWInfo record
NKHWInfo record 0,increment
MacROM_Base ds.l 1 ; 000, irp+f00 ; base address (physical) of Mac ROM
DeviceTreeBase ds.l 1 ; 004, irp+f04 ; base address of the copied device tree properties
UniversalInfoTableBase ds.l 1 ; 008, irp+f08 ; base address of the Universal Info Table
ConfigInfoTableBase ds.l 1 ; 00c, irp+f0c ; base address of the Config Info Table
VectorLookupTable ds.l 1 ; 010, irp+f10 ; base address of the interrupt vector lookup table (short *)
VectorMaskTable ds.l 1 ; 014, irp+f14 ; base address of the interrupt vector mask table (long *)
OpenPICBaseAddr ds.l 1 ; 018, irp+f18 ; OpenPIC base address
ISAMaster8259 ds.l 1 ; 01c, irp+f1c ; ISA Master 8259 ports (char *)
ISASlave8259 ds.l 1 ; 020, irp+f20 ; ISA Slave 8259 ports (char *)
InterruptAck8259 ds.l 1 ; 024, irp+f24 ; address to read to ack 8259 interrupt (long *)
; interrupt pending bits (actively changing)
PendingInts ds.l 2 ; 028, irp+f28 ; 64 bits of pending interrupts
; some Mac I/O device base addresses
ADB_Base ds.l 1 ; 030, irp+f30 ; base address of ADB
SCSI_DMA_Base ds.l 1 ; 034, irp+f34 ; base address of SCSI DMA registers
; RTAS related stuff
RTAS_PrivDataArea ds.l 1 ; 038, irp+f38 ; RTAS private data area
MacOS_NVRAM_Offset ds.l 1 ; 03c, irp+f3c ; offset into nvram to MacOS data
RTAS_NVRAM_Fetch ds.l 1 ; 040, irp+f40 ; token for RTAS NVRAM fetch
RTAS_NVRAM_Store ds.l 1 ; 044, irp+f44 ; token for RTAS NVRAM store
RTAS_Get_Clock ds.l 1 ; 048, irp+f48 ; token for RTAS clock get
RTAS_Set_Clock ds.l 1 ; 04c, irp+f4c ; token for RTAS clock set
RTAS_Restart ds.l 1 ; 050, irp+f50 ; token for RTAS Restart
RTAS_Shutdown ds.l 1 ; 054, irp+f54 ; token for RTAS Shutdown
RTAS_Restart_At ds.l 1 ; 058, irp+f58 ; token for RTAS system startup at specified time
RTAS_EventScan ds.l 1 ; 05c, irp+f5c ; token for RTAS event scan
RTAS_Check_Exception ds.l 1 ; 060, irp+f60 ; token for RTAS check exception
RTAS_Read_PCI_Config ds.l 1 ; 064, irp+f64 ; token for RTAS read PCI config
RTAS_Write_PCI_Config ds.l 1 ; 068, irp+f68 ; token for RTAS write PCI config
; SIO interrupt source numbers for the MPIC
SIOIntVect ds.w 1 ; 06c, irp+f6c ; SIO (8259 cascade vector) vector number
SIOIntBit ds.w 1 ; 06e, irp+f6e ; SIO (8259 cascade vector) bit number
Signature ds.l 1 ; 070, irp+f70 ; signature for this record ('Hnfo')
; more interrupt source numbers
SpuriousIntVect ds.w 1 ; 074, irp+f74 ; spurious vector number
CPU_ID ds.w 1 ; 076, irp+f76 ; the ID of this CPU (universal-tables-related)
SCCAIntVect ds.w 1 ; 078, irp+f78 ; SCC A (non-DMA) vector number
SCCBIntVect ds.w 1 ; 07a, irp+f7a ; SCC B (non-DMA) vector number
SCSIIntVect ds.w 1 ; 07c, irp+f7c ; SCSI vector number
SCSIDMAIntVect ds.w 1 ; 07e, irp+f7e ; SCSI DMA vector number
VIAIntVect ds.w 1 ; 080, irp+f80 ; VIA vector number
VIAIntBit ds.w 1 ; 082, irp+f82 ; VIA bit number
ADBIntVect ds.w 1 ; 084, irp+f84 ; vector number
NMIIntVect ds.w 1 ; 086, irp+f86 ; NMI vector number
NMIIntBit ds.w 1 ; 088, irp+f88 ; NMI bit number
; current (actively changing) interrupt handling variables
ISAPendingInt ds.w 1 ; 08a, irp+f8a ; currently pending ISA/8259 interrupt
CompletedInts ds.b 8 ; 08c, irp+f8c ; completed interrupts
nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box
nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box
nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied
HardwareInfoFlags ds.l 1 ; 094, irp+f94 ; 32 bits of flags (see enum above)
RTAS_Get_PowerOn_Time ds.l 1 ; 098, irp+f98 ; token for RTAS getting time for system startup
align 5 ; pad to nice cache block alignment (did i get this right?)
endr
;_______________________________________________________________________
; Processor State Record
;
; Used to save the state of the processor across sleep.
;_______________________________________________________________________
NKProcessorStatePtr equ $5FFFEFC8 ; logical address of ProcessorState record
NKProcessorStateVer equ $5FFFEFCC ; version number of ProcessorState record
NKProcessorStateLen equ $5FFFEFCE ; length of ProcessorState record
NKProcessorState record 0,increment
saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U
saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L
saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U
saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L
saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U
saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L
saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U
saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L
saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U
saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L
saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U
saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L
saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U
saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L
saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U
saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L
saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0
saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1
saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2
saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3
saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR
saveSRR0 ds.l 1 ; 054 ; place to store SRR0
saveSRR1 ds.l 1 ; 058 ; place to store SRR1
saveTBU ds.l 1 ; 05c ; place to store TBU
saveTBL ds.l 1 ; 060 ; place to store TBL
saveHID0 ds.l 1 ; 064 ; place to store HID0
saveDEC ds.l 1 ; 068 ; place to store DEC
saveMSR ds.l 1 ; 06c ; place to store MSR
saveSDR1 ds.l 1 ; 070 ; place to store SDR1
; saveKernelDataPtr needs to always be right after saveReturnAddr
; because of how the code works. DO NOT CHANGE THIS ORDERING!
saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to.
saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr
saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr
endr

544
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; Opaque NanoKernel structures:
; - stored in the NanoKernel pool (not always)
; - associated with a class number and opaque ID (not always)
; - referenced by opaque ID (for MPLibrary's benefit)
;_______________________________________________________________________
; ID CLASS 1: PROCESS
; (size: 32b, thud command: id -p)
;
; The NanoKernel's internal representation of a cooperative process
; within the blue environment. Processes and tasks have a many-to-one
; relationship.
;
; There is a special 'blue' process that owns the blue task and all
; the CPU idle tasks.
;_______________________________________________________________________
Process record 0,INCR
kIDClass equ 1
kSignature equ 'PROC'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04 ; 'PROC'
Unused ds.l 1 ; 08 ; MPCall_5 does something here
SystemAddressSpaceID ds.l 1 ; 0c ; set by Init.s after addrspc creation
TaskCount ds.l 1 ; 10 ; incremented by CreateTask
SystemAddressSpacePtr ds.l 1 ; 14
AddressSpaceCount ds.l 1 ; 18 ; incremented by NKCreateAddressSpaceSub
ds.l 1 ; 1c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 2: TASK
; (size: 1k, thud command: id -t)
;
; What the MPLibrary and NanoKernel call the unit of multitasking.
; (Remember that 'Thread' and 'Process' were taken.)
;
; Contains space for a ContextBlock in the style of the ECB, but
; blue's ContextBlockPtr is redirected to the ECB.
;_______________________________________________________________________
Task record 0,INCR
kIDClass equ 2
kSignature equ 'TASK'
;_______________________
; Task priorities
;_______________________
kCriticalPriority equ 0
kLatencyProtectPriority equ 1
kNominalPriority equ 2
kIdlePriority equ 3
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 000
Signature ds.l 1 ; 004
QueueMember ds.l 4 ; 008:018 ; a task is always a member of a queue, e.g. the RDYQ
MysteryByte1 ds.b 1 ; 018 ; CreateTask sets 0 by default (blue = 2)
Priority ds.b 1 ; 019 ; CreateTask sets 2 by default
MysteryHalf ds.w 1 ; 01a
Weight ds.l 1 ; 01c ; default is 100, blue gets 200, idle gets 1
ds.l 1 ; 020
ds.l 1 ; 024
ds.l 1 ; 028
ds.l 1 ; 02c
ds.l 1 ; 030
ds.l 1 ; 034
ds.l 1 ; 038
ds.l 1 ; 03c
ds.l 1 ; 040
ds.l 1 ; 044
ds.l 1 ; 048
ds.l 1 ; 04c
ds.l 1 ; 050
ds.l 1 ; 054
ds.l 1 ; 058
ds.l 1 ; 05c
ProcessID ds.l 1 ; 060
ThingThatAlignVecHits ds.l 1 ; 064 ; IntAlignment is interested in bit 9, MPCall 116 in bit 15
ds.l 1 ; 068
OwningProcessPtr ds.l 1 ; 06c
AddressSpacePtr ds.l 1 ; 070 ; borrowed from PROC argument to CreateTask
Name ds.l 1 ; 074 ; 'blue', creator of owning cooperative process, etc
CpuID ds.l 1 ; 078
ds.l 1 ; 07c
CreateTime3 ds.d 1 ; 080
ContextBlockPtr ds.l 1 ; 088 ; points internally by default, and to EDP.ECB in blue
VectorSaveArea ds.l 1 ; 08c
ds.l 1 ; 090
ds.l 1 ; 094
ds.l 1 ; 098
NotificationPtr ds.l 1 ; 09c
SemaphoreLLL ds.l 4 ; 0a0:0b0
Zero ds.l 1 ; 0b0
One ds.l 1 ; 0b4
ds.l 1 ; 0b8
ds.l 1 ; 0bc
Zero1 ds.l 1 ; 0c0
Zero2 ds.l 1 ; 0c4
CreateTime1 ds.d 1 ; 0c8
CreateTime2 ds.d 1 ; 0d0
ds.l 1 ; 0d8
ds.l 1 ; 0dc
Zero3 ds.l 1 ; 0e0
Zero4 ds.l 1 ; 0e4
Zero5 ds.l 1 ; 0e8
ds.l 1 ; 0ec
YellowVecTblPtr ds.l 1 ; 0f0
ds.l 1 ; 0f4
ds.l 1 ; 0f8
ds.l 1 ; 0fc
ContextBlock ds.b 768 ; 100:400 ; like the EDP's Emulator Context Block -- unsure of size
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 3: TIMER
; (size: 64b, thud command: id -tm)
;
;_______________________________________________________________________
Timer record 0,INCR
kIDClass equ 3
kSignature equ 'TIME'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
ds.l 1 ; 08
ds.l 1 ; 0c
ProcessID ds.l 1 ; 10
ds.l 1 ; 14
ds.l 1 ; 18
ds.l 1 ; 1c
ds.l 1 ; 20
ds.l 1 ; 24
ds.l 1 ; 28
ds.l 1 ; 2c
ds.l 1 ; 30
ds.l 1 ; 34
ds.l 1 ; 38
ds.l 1 ; 3c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 4: QUEUE
; (size: 52b, thud command: id -q)
;
;_______________________________________________________________________
Queue record 0,INCR
kIDClass equ 4
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10
ds.l 4 ; 10:20
ProcessID ds.l 1 ; 20
ds.l 1 ; 24
ds.l 1 ; 28
ds.l 1 ; 2c
ds.l 1 ; 30
Size equ *
endr
ReadyQueue record 0,INCR
LLL ds.l 4 ; 00:10 ; nothing fancy
Counter ds.l 1 ; 10 ; InitRDYQs sets, TaskReadyAsNext bumps
TotalWeight ds.l 1 ; 14 ; divide available time by these
Timecake ds.d 1 ; 18 ; period of ~1ms, 8ms, 64ms, 512ms
org 0x20
; Constants
kSignature equ 'RDYQ'
endr
kTimerQueueSignature equ 'TMRQ'
kDelayQueueSignature equ 'DLYQ'
kDbugQueueSignature equ 'DBUG'
kPageQueueSignature equ 'PAGQ'
kNotQueueSignature equ 'NOTQ'
kSemaQueueSignature equ 'SEMQ'
;_______________________________________________________________________
; ID CLASS 5: SEMAPHORE
; (size: 32b, thud command: id -s)
;
;_______________________________________________________________________
Semaphore record 0,INCR
kIDClass equ 5
kSignature equ 'SEMA'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10
ds.l 1 ; 10
ds.l 1 ; 14
ProcessID ds.l 1 ; 18
ds.l 1 ; 1c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 6: CRITICAL REGION
; (size: 36b, thud command: id -r)
;
;_______________________________________________________________________
CriticalRegion record 0,INCR
kIDClass equ 6
kSignature equ 'CRGN'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10
ProcessID ds.l 4 ; 10:20 ; lll.freeform is the field?
ds.l 1 ; 20
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 7: CPU
; (size: 32+800+128 = 960b, thud command: id -c)
;
;_______________________________________________________________________
CPU record 0,INCR
kIDClass equ 7
kSignature equ 'CPU '
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
CgrpList ds.l 4 ; 08:18
Eff ds.l 1 ; 18 ; contains 0x0000000f
IdleTaskPtr ds.l 1 ; 1c
EWABase ds.b 800 ; negative-indexed parts of EWA
EWA ds.b 128 ; positive-indexed parts of EWA
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 8: ADDRESS SPACE
; (size: 192b, thud command: id -sp)
;
;_______________________________________________________________________
AddressSpace record 0,INCR
kIDClass equ 8
kSignature equ 'SPAC'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
ds.l 1 ; 08
TaskCount ds.l 1 ; 0c ; incremented by CreateTask
RsrvList ds.l 4 ; 10:20 ; LLL
AreaList ds.l 4 ; 20:30 ; LLL
SRs ds.l 16 ; 30:70 ; segment register values
ParentCoherenceSpecialPtr ds.l 1 ; 70 ; SpecialPtr of owning cgrp (in list owned by Cpu)
ProcessID ds.l 1 ; 74 ; ID of owning PROC
ds.l 1 ; 78
ds.l 1 ; 7c
BATs
BAT0U ds.l 1 ; 80
BAT0L ds.l 1 ; 84
BAT1U ds.l 1 ; 88
BAT1L ds.l 1 ; 8c
BAT2U ds.l 1 ; 90
BAT2L ds.l 1 ; 94
BAT3U ds.l 1 ; 98
BAT3L ds.l 1 ; 9c
ExtraBATs ; the flag that enables these is never set?
ExtraBAT0U ds.l 1 ; a0
ExtraBAT0L ds.l 1 ; a4
ExtraBAT1U ds.l 1 ; a8
ExtraBAT1L ds.l 1 ; ac
ExtraBAT2U ds.l 1 ; b0
ExtraBAT2L ds.l 1 ; b4
ExtraBAT3U ds.l 1 ; b8
ExtraBAT3L ds.l 1 ; bc
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 9: EVENT GROUP
; (size: 32b, thud command: id -e)
;
;_______________________________________________________________________
EventGroup record 0,INCR
kIDClass equ 9
kSignature equ 'EVNT'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10 ; first field is ID
ds.l 1 ; 10
ProcessID ds.l 1 ; 14
ds.l 1 ; 18 ; contains 1-8 +/- 16
ds.l 1 ; 1c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 10: COHERENCE GROUP
; (size: 88b, thud command: id -cg)
;
;_______________________________________________________________________
CoherenceGroup record 0,INCR
kIDClass equ 10
kSignature equ 'CGRP'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10 ; element in CpuStructs list of cgrps
GRPSList ds.l 4 ; 10:20 ; my own list of GRPSes (what are they?)
CpuCount ds.l 1 ; 20
ScheduledCpuCount ds.l 1 ; 24
ds.l 1 ; 28
ds.l 1 ; 2c
ds.l 1 ; 30
ds.l 1 ; 34
ds.l 1 ; 38
ds.l 1 ; 3c
ds.l 1 ; 40
ds.l 1 ; 44
Incrementer ds.l 1 ; 48 ; number of NKCreateAddressSpaceSub calls % 1M
ds.l 1 ; 4c
ds.l 1 ; 50
ds.l 1 ; 54
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 11: AREA
; (size: 160b, thud command: id -a)
;
; A contiguous region of effective addresses with similar properties.
;_______________________________________________________________________
Area record 0,INCR
kIDClass equ 11
kSignature equ 'AREA'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
TwoFiftySix ds.l 1 ; 08
ProcessID ds.l 1 ; 0c
AddressSpaceID ds.l 1 ; 10
ds.l 1 ; 14
ds.l 1 ; 18
ds.l 1 ; 1c
ds.l 1 ; 20
LogicalBase ds.l 1 ; 24
LogicalBase2 ds.l 1 ; 28
Length ds.l 1 ; 2c ; in actual bytes!
Zero ds.l 1 ; 30
ds.l 1 ; 34
Length2 ds.l 1 ; 38
ds.l 1 ; 3c
ds.l 1 ; 40
ds.l 1 ; 44
ds.l 1 ; 48
ds.l 1 ; 4c
ds.l 1 ; 50
LLL ds.l 4 ; 54:64 ; member of address space
ds.l 1 ; 64
ds.l 1 ; 68
AddressSpacePtr ds.l 1 ; 6c
ds.l 1 ; 70
ds.l 1 ; 74
ds.l 1 ; 78
ds.l 1 ; 7c
ds.l 1 ; 80
ds.l 1 ; 84
ds.l 1 ; 88
ds.l 1 ; 8c
ds.l 1 ; 90
ds.l 1 ; 94
ds.l 1 ; 98
ds.l 1 ; 9c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 12: NOTIFICATION
; (size: 40b, thud command: id -n)
;
;_______________________________________________________________________
Notification record 0,INCR
kIDClass equ 12
kSignature equ 'KNOT'
;_______________________
; Fields
;_______________________
ds.l 1 ; 00
Signature ds.l 1 ; 04
ProcessID ds.l 1 ; 08
ds.l 1 ; 0c
ds.l 1 ; 10
ds.l 1 ; 14
ds.l 1 ; 18
ds.l 1 ; 1c
ds.l 1 ; 20
ds.l 1 ; 24
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 13: CONSOLE LOG
; (size: 16b, thud command: id -nc)
;
; Never seen one in the wild -- must have been in debug builds.
;_______________________________________________________________________
ConsoleLog record 0,INCR
kIDClass equ 13
;_______________________
; Fields
;_______________________
ds.l 1 ; 00
ds.l 1 ; 04
ProcessID ds.l 1 ; 08
ds.l 1 ; 0c
Size equ *
endr

1001
Internal/NKPublic.a Normal file

File diff suppressed because it is too large Load Diff

151
Linker/LinkPowerROM Normal file
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Set Streamer " | StreamEdit -d -e '/?Å/ Pr ¶¶¶"1¶¶¶"'"
If {#} ¶< 2
Echo "USAGE: {0} DEST SRC ... > ShellScript"
Exit 1
End
Set DestFile "{1}"
Shift
Set TempPrepFile "{TempFolder}PPCROMLinkPrepCmds"
Set TempCmdFile "{TempFolder}PPCROMLinkCmds"
Echo -n "" > "{TempPrepFile}"
Echo -n "PPCLink -xm library -codestart 0 -warn -o " > "{TempCmdFile}"
Quote -n "{DestFile}.x" >> "{TempCmdFile}"
Set OffsetSoFar 0
Set NeedTool 1 # Always extract binary, so always need tool
Loop # over arguments
If !{#}
Break
End
If "{1}" =~ /[0-9]+/ || "{1}" =~ /0x[0-9a-f]+/
# Move-to-offset argument (hex or decimal literal)
If `Evaluate {1} ¶< {OffsetSoFar}`
Echo "{0} failed: cannot pad to offset {1} because we are already past it!"
Exit 1
End
Set Delta `Evaluate -h {1} - {OffsetSoFar}`
If {Delta}
Echo -n "Set F ¶"¶{TempFolder¶}Zeros_{Delta}.s¶";¶t" >> "{TempPrepFile}"
Echo -n 'If !`Exists "{F}"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '`; ' >> "{TempPrepFile}"
Echo -n "Echo ¶¶tDCB.B {Delta}, 0" '> "{F}"; ' >> "{TempPrepFile}"
Echo -n 'PPCAsm "{F}"; ' >> "{TempPrepFile}"
Echo "End" >> "{TempPrepFile}"
Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}"
Echo -n "¶"¶{TempFolder¶}Zeros_{Delta}.s.o¶"" >> "{TempCmdFile}"
Set OffsetSoFar {1}
End
Else If "{1}" =~ /([A-Za-z0-9]+)¨1:/
# Label argument
Echo -n "Set F ¶"¶{TempFolder¶}{¨1}.s¶";¶t" >> "{TempPrepFile}"
Echo -n 'If !`Exists "{F}"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '`; ' >> "{TempPrepFile}"
Echo -n "Echo ¶¶tEXPORT {¨1}¶¶n{¨1}" '> "{F}"; ' >> "{TempPrepFile}"
Echo -n 'PPCAsm "{F}"; ' >> "{TempPrepFile}"
Echo "End" >> "{TempPrepFile}"
Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}"
Echo -n "¶"¶{TempFolder¶}{¨1}.s.o¶"" >> "{TempCmdFile}"
Else
# Filename argument
If "{1}" !~ /Å.x/
Echo -n "Set F " >> "{TempPrepFile}"
Quote -n "{1}" >> "{TempPrepFile}"
Echo -n "; " >> "{TempPrepFile}"
Echo -n 'If !`Exists "{F}.x"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '` || `Newer "{F}" "{F}.x"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '`; ' >> "{TempPrepFile}"
Quote -n "{0}.tool" >> "{TempPrepFile}"
Echo -n ' tox "{F}" "{F}.x"; ' >> "{TempPrepFile}"
Echo "End" >> "{TempPrepFile}"
Set NeedTool 1
Set TheXCOFF "{1}.x"
Set TextLen `Files -x b -n "{1}" | StreamEdit -d -e '/([0-9]+)¨1b°/ Print ¨1'`
Else
Set TheXCOFF "{1}"
Set TextLen `DumpXCOFF -do h "{TheXCOFF}" | StreamEdit -d -e '/s_nameŶ".(Å)¨1¶"/ Set CurSec ¨1' -e '/s_sizeŶ((Å)¨1¶)/ Print CurSec " " ¨1' | StreamEdit -d -e '/text (Å)¨1/ Print ¨1'`
End
Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}"
Quote -n "{TheXCOFF}" >> "{TempCmdFile}"
Set OffsetSoFar `Evaluate {OffsetSoFar} + {TextLen}`
End
Shift
End
If {NeedTool}
Echo "# Compile a C program to create/extract basic XCOFFs"
Echo -n 'If !`Exists '
Quote -n "{0}.tool"
Echo -n "{Streamer}"
Echo '`'
Echo -n "¶tSC "
Echo -n '-o "{TempFolder}LinkPowerROM.o" '
Quote "{0}.c"
Echo -n "¶tILink -d -t MPST -c 'MPS ' -o "
Quote -n "{0}.tool"
Echo ' "{Libraries}Stubs.o" "{CLibraries}StdCLib.o" "{Libraries}MacRuntime.o" "{Libraries}IntEnv.o" "{Libraries}Interface.o" "{TempFolder}LinkPowerROM.o"'
Echo "End"
Echo
End
Echo "# Auto-generate some XCOFFs (padding and labels)"
Catenate "{TempPrepFile}"
Echo
Echo "# Link whole-ROM XCOFF"
Catenate "{TempCmdFile}"
Echo
Echo
Echo "# Extract raw ROM binary"
Quote -n "{0}.tool"
Echo -n " fromx "
Quote -n "{DestFile}.x"
Echo -n " "
Quote "{DestFile}"
Echo
Echo "# Checksum the ConfigInfo structure(s)"
Echo -n 'Set CksumOffsets "`DumpXCOFF -do s '
Quote -n "{DestFile}.x"
Echo ' | StreamEdit -d -e "/C_EXTÅAddrÅ(0x[A-Fa-f0-9]+)¨1ÅConfigInfoChecksum/ Print ¨1"`"'
Quote -n "{0}.tool"
Echo -n " cksum "
Quote -n "{DestFile}"
Echo ' {CksumOffsets}'

216
Linker/LinkPowerROM.c Normal file
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#include <stdio.h>
#include <XCOFF.h>
#include <stdlib.h>
#ifdef macintosh
typedef unsigned long uint32_t;
typedef long int32_t;
typedef unsigned short uint16_t;
typedef short int16_t;
typedef unsigned char uint8_t;
typedef char int8_t;
#endif
uint32_t narrow[8];
uint32_t wide[2];
int slurp(char *path, uint8_t **datap, unsigned long *sizep)
{
FILE *f;
long pos;
uint8_t *bytes;
f = fopen(path, "rb");
if(f == NULL) return 1;
fseek(f, 0, SEEK_END);
pos = ftell(f);
fseek(f, 0, SEEK_SET);
bytes = (uint8_t *)malloc(pos);
if(bytes == NULL) return 1;
fread(bytes, pos, 1, f);
fclose(f);
*datap = bytes;
*sizep = pos;
return 0; /* no error */
}
const uint16_t pretend_header[] = {
0x01df /*f_magic*/,
1 /*f_nscns*/,
0xd611, 0x2977 /*f_timdat*/,
0, 0 /*f_symptr*/,
0, 2 /*f_nsyms*/,
0 /*f_opthdr*/,
0 /*f_flags*/,
/* now for single .text symbol header */
0x2e74, 0x6578, 0x7400, 0x0000 /*s_name = .text*/,
0, 0 /*s_paddr*/,
0, 0 /*s_vaddr*/,
1234, 5678 /*s_size*/,
0, 0x3c /*s_scnptr = len of this header*/,
0, 0 /*s_relptr*/,
0, 0 /*s_lnnoptr*/,
0 /*s_nreloc*/,
0 /*s_nlnno*/,
0, 0x20 /*s_flags = text*/
};
const uint16_t pretend_footer[] = {
0, 0,
0, 0,
0, 0,
1, 0,
0x6b01,
1234, 5678,
0, 0, 0,
0x1100, 0, 0, 0
};
int main(int argc, char **argv)
{
FILE *fp;
uint8_t *buf, *sec, *dest;
unsigned long buflen, seclen, destlen;
unsigned long i;
if(argc < 2)
{
fprintf(stderr, "%s: No command specified -- use tox, fromx or cksum\n", argv[0]);
return 1;
}
if(!strcmp(argv[1], "cksum"))
{
unsigned long offset;
if(argc < 3)
{
fprintf(stderr, "%s: %s: Specify a file!\n", argv[0], argv[1]);
return 1;
}
if(argc < 4)
{
return 0; /* No offset specified -- fail silently */
}
if(slurp(argv[2], &buf, &buflen))
{
fprintf(stderr, "%s: %s: Could not open input\n", argv[0], argv[1]);
return 1;
}
offset = strtoul(argv[3], NULL, 0);
if(offset > buflen - 40) {
fprintf(stderr, "%s: Bad offset for ConfigInfo checksum: 0x%x\n", argv[0], offset);
return 1;
}
memset(buf + offset, 0, 40);
for(i=0; i<buflen; i++)
{
/* eight 4-byte sums, for each of eight byte lanes */
narrow[i & 7] += buf[i];
}
for(i=0; i<buflen; i+=8)
{
/* a single 64-bit sum */
uint32_t oldlow = wide[1];
wide[0] += *(uint32_t *)(buf + i);
wide[1] += *(uint32_t *)(buf + i + 4);
if(wide[1] < oldlow) wide[0]++;
}
fp = fopen(argv[2], "r+b");
if(!fp) {
fprintf(stderr, "%s: Could not open output\n", argv[0]);
return 1;
}
fseek(fp, offset, SEEK_SET);
fwrite(narrow, sizeof narrow, 1, fp);
fwrite(wide, sizeof wide, 1, fp);
fclose(fp);
}
else
{
/* XCOFF personality */
if(argc != 4) {
fprintf(stderr, "Usage: %s (tox | fromx) IN OUT\n", argv[0]);
return 1;
}
if(slurp(argv[2], &buf, &buflen))
{
fprintf(stderr, "%s: %s: Could not open input\n", argv[0], argv[1]);
return 1;
}
if(!strcmp(argv[1], "tox"))
{
sec = buf;
seclen = buflen;
}
else if(!strcmp(argv[1], "fromx"))
{
FileHdrPtr fhp;
SectionHdrEntryPtr shp;
fhp = (FileHdrPtr)buf;
shp = (SectionHdrEntryPtr)(buf + sizeof *fhp + fhp->f_opthdr);
sec = buf + shp->s_scnptr;
seclen = shp->s_size;
}
/* now to create my template XCOFF */
if(!strcmp(argv[1], "tox"))
{
destlen = sizeof pretend_header + seclen + sizeof pretend_footer;