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powermac-rom
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Elliot Nunn 2017-11-19 12:11:07 +08:00
commit c5c5b784cb
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.DS_Store
BuildResults/
*.NJ
*.tool
RomMondo.bin.x
*.dmg

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; ROM version of NKConfigurationInfo struct, based on Mac OS ROM 8=9=10.
; Lives at ROM + 0x30d000 (and other addresses on OldWorld).
; From start of ConfigInfo to end of LoMemInit = 4k:
; Auto-align fields
aligning on
import RomTop, RomBtm
import Mac68kRomTop, Mac68kRomBtm
import ExTblTop
import NKTop
import EmTop, EmBtm, EmEntry, EmKernelTrapTable
import OpcodeTblTop, OpcodeTblBtm
ConfigInfo
; These sums are not checked on NewWorld, but :Tools:ToolSource:RiscLayout.c calcs them anyway
dcb.l 8, 0 ; 000 ; ROMByteCheckSums ; ROM Checksums - one word for each of 8 byte lanes
dcb.l 2, 0 ; 020 ; ROMCheckSum64 ; ROM Checksum - 64 bit sum of doublewords
dc.l RomTop-ConfigInfo ; 028 ; ROMImageBaseOffset ; Offset of Base of total ROM image
dc.l RomBtm-RomTop ; 02c ; ROMImageSize ; Number of bytes in ROM image
dc.l 0 ; 030 ; ROMImageVersion ; ROM Version number for entire ROM
; ROM component Info (offsets are from base of ConfigInfo page)
dc.l Mac68kRomTop-ConfigInfo ; 034 ; Mac68KROMOffset ; Offset of base of Macintosh 68K ROM
dc.l Mac68kRomBtm-Mac68kRomTop ; 038 ; Mac68KROMSize ; Number of bytes in Macintosh 68K ROM
dc.l ExTblTop-ConfigInfo ; 03c ; ExceptionTableOffset ; Offset of base of PowerPC Exception Table Code
dc.l 0xc000 ; 040 ; ExceptionTableSize ; Number of bytes in PowerPC Exception Table Code (generous)
dc.l RomTop+0x320000-ConfigInfo ; 044 ; HWInitCodeOffset ; Offset of base of Hardware Init Code (no longer exists)
dc.l 0x10000 ; 048 ; HWInitCodeSize ; Number of bytes in Hardware Init Code
dc.l NKTop-ConfigInfo ; 04c ; KernelCodeOffset ; Offset of base of NanoKernel Code
dc.l 0x10000 ; 050 ; KernelCodeSize ; Number of bytes in NanoKernel Code (too small)
dc.l EmTop-ConfigInfo ; 054 ; EmulatorCodeOffset ; Offset of base of Emulator Code
dc.l EmBtm-EmTop ; 058 ; EmulatorCodeSize ; Number of bytes in Emulator Code
dc.l OpcodeTblTop-ConfigInfo ; 05c ; OpcodeTableOffset ; Offset of base of Opcode Table
dc.l OpcodeTblBtm-OpcodeTblTop ; 060 ; OpcodeTableSize ; Number of bytes in Opcode Table
; Offsets within the Emulator Data Page.
string AsIs
@s dc.b 'NewWorld v1.0' ; 064 ; BootstrapVersion ; Bootstrap loader version info
org @s + 16
dc.l 0xf00 ; 074 ; BootVersionOffset ; offset within EmulatorData of BootstrapVersion
dc.l 0x100 ; 078 ; ECBOffset ; offset within EmulatorData of ECB
dc.l 0x070 ; 07c ; IplValueOffset ; offset within EmulatorData of IplValue
; Offsets within the Emulator Code.
dc.l EmEntry-EmTop ; 080 ; EmulatorEntryOffset ; offset within Emulator Code of entry point
dc.l EmKernelTrapTable-EmTop ; 084 ; KernelTrapTableOffset ; offset within Emulator Code of KernelTrapTable
; Interrupt Passing Masks.
dc.l 0x00200000 ; 088 ; TestIntMaskInit ; initial value for test interrupt mask
dc.l 0xff9fffff ; 08c ; ClearIntMaskInit ; initial value for clear interrupt mask
dc.l 0x00e00000 ; 090 ; PostIntMaskInit ; initial value for post interrupt mask
dc.l 0x808e0000 ; 094 ; LA_InterruptCtl ; logical address of Interrupt Control I/O page
dc.b 6 ; 098 ; InterruptHandlerKind ; kind of handler to use
dc.l 0x5fffe000 ; 09c ; LA_InfoRecord ; logical address of InfoRecord page
dc.l 0x68ffe000 ; 0a0 ; LA_KernelData ; logical address of KernelData page
dc.l 0x68fff000 ; 0a4 ; LA_EmulatorData ; logical address of EmulatorData page
dc.l 0x68080000 ; 0a8 ; LA_DispatchTable ; logical address of Dispatch Table
dc.l 0x68060000 ; 0ac ; LA_EmulatorCode ; logical address of Emulator Code
dc.l LowMemVals-ConfigInfo ; 0b0 ; MacLowMemInitOffset ; offset to list of LowMem addr/data values
;
; Then the pagemap init stuff is filled by the trampoline at boot
;
; Address Space Mapping
dc.l 0 ; 0b4 ; PageAttributeInit ; default WIMG, PP settings for PTE creation
dc.l 0 ; 0b8 ; PageMapInitSize ; size of page mapping info
dc.l 0 ; 0bc ; PageMapInitOffset ; offset to page mapping info (from base of ConfigInfo)
dc.l 0 ; 0c0 ; PageMapIRPOffset ; offset of InfoRecord map info (from base of PageMap)
dc.l 0 ; 0c4 ; PageMapKDPOffset ; offset of KernelData map info (from base of PageMap)
dc.l 0 ; 0c8 ; PageMapEDPOffset ; offset of EmulatorData map info (from base of PageMap)
dcb.l 32, 0 ; 0cc ; SegMap32SupInit ; 32 bit mode Segment Map Supervisor space
dcb.l 32, 0 ; 14c ; SegMap32UsrInit ; 32 bit mode Segment Map User space
dcb.l 32, 0 ; 1cc ; SegMap32CPUInit ; 32 bit mode Segment Map CPU space
dcb.l 32, 0 ; 24c ; SegMap32OvlInit ; 32 bit mode Segment Map Overlay mode
dcb.l 32, 0 ; 2cc ; BATRangeInit ; BAT mapping ranges
dc.l 0 ; 34c ; BatMap32SupInit ; 32 bit mode BAT Map Supervisor space
dc.l 0 ; 350 ; BatMap32UsrInit ; 32 bit mode BAT Map User space
dc.l 0 ; 354 ; BatMap32CPUInit ; 32 bit mode BAT Map CPU space
dc.l 0 ; 358 ; BatMap32OvlInit ; 32 bit mode BAT Map Overlay mode
; Only needed for Smurf
dc.l 0 ; 35c ; SharedMemoryAddr ; physical address of Mac/Smurf shared message mem
dc.l -1 ; 360 ; PA_RelocatedLowMemInit ; physical address of RelocatedLowMem
dc.l 0x330000 - 0x30d000 ; 364 ; OpenFWBundleOffset ; Offset of base of OpenFirmware PEF Bundle
dc.l 0x20000 ; 368 ; OpenFWBundleSize ; Number of bytes in OpenFirmware PEF Bundle
dc.l 0xff800000 ; 36c ; LA_OpenFirmware ; logical address of Open Firmware
dc.l 0x00400000 ; 370 ; PA_OpenFirmware ; physical address of Open Firmware
dc.l 0xfff0c000 ; 374 ; LA_HardwarePriv ; logical address of HardwarePriv callback
; There are still some fixed-location fields here that the Trampoline will populate,
; but the ROM we are building contains just zeros.
;
; Key/value pairs for initializing Low Memory Globals.
; (at the end of ConfigInfo's 4k max size)
;
; A wee little macro to write LoMem key/value pairs *below* the asm location counter
macro
LowMem &addr, &val
@b
org @b - 4
dc.l &val
org @b - 8
dc.l &addr
org @b - 8
endm
; Sentinel zero at end (late address) of list
org 4096 - 4
dc.l 0
org 4096 - 4
; The table (older RISC versions have more in here.)
; The 68k emulator's cold-start vector, points to a "JMP StartBoot"
; instruction in the 68k ROM header. (Normally this value would be
; read from the ROM while it was overlaid on RAM at cold start, but
; why emulate that on a PowerPC?)
; SheepShaver patches the 68k reset vector around this location,
; but assumed offset 0xfd8.
LowMem 0x00000004, 0xffc0002a
LowMemVals

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Set Parent "`Files -f "{0}" | StreamEdit -d -e '/((Å:)*)¨1([Â:]*)/ Print ¨1'`"
SetDirectory "{Parent}" # too easy
Make -w > :BuildResults:BuildOut
:BuildResults:BuildOut

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EDP record 0,INCR
org 0x70
IplValue ds.w 1 ; 070 ; 68k int level or -1
org 0x100
ContextBlock ds.b 768 ; 100:300 ; Emulator Context Block, ECB; NKv2 ties this to blue task
org 0xf00
BootstrapVersion ds.b 16 ; f00:f10 ; Bootstrap loader version info, from ConfigInfo
endr
; Lives in EDP. Keeping a separate record to EDP makes the code nicer.
; Gets called the "system context"
ContextBlock record 0,INCR
EmpiricalCpuFeatures ds.l 1 ; 000 ; (SPAC) copied from kdp by CreateTask
org 0x5c
LA_EmulatorKernelTrapTable ds.l 1
org 0x84
LA_EmulatorEntry ds.l 1 ; 084 ; Entry pt of emulator; set by NK Init.s
org 0x94
LA_EmulatorData ds.l 1
org 0x9c
LA_DispatchTable ds.l 1
org 0xa4
MSR ds.l 1 ; 0a4 ; (SPAC) copied from kdp by CreateTask
org 0xc4
MQ ds.l 1 ; 0c4 ; 601 only
ds.l 1
PriorityShifty ds.l 1 ; 0cc ; if low nybble is empty, InitRDYQs sets this to 2
org 0xd4
XER ds.l 1
VectorSaveArea ds.l 1 ; 0d8 ; AltiVec hack: vector registers don't fit in CB!
org 0xe0
PageInSystemHeap ds.l 1 ; 0e0 ; these are set by StartInit.a:FiddleWithEmulator
OtherPageInSystemHeap ds.l 1 ; 0e4
FE000000 ds.l 1 ; 0e8
Zero ds.l 1 ; 0ec
org 0xfc
CodePtr ds.l 1 ; 0fc ; probably goes in SRR0?
org 0x100
ds.l 1
r0 ds.l 1 ; 104
ds.l 1
r1 ds.l 1 ; 10c
ds.l 1
r2 ds.l 1 ; 114
ds.l 1
r3 ds.l 1 ; 11c
ds.l 1
r4 ds.l 1 ; 124
ds.l 1
r5 ds.l 1 ; 12c
ds.l 1
r6 ds.l 1 ; 134
ds.l 1
r7 ds.l 1 ; 13c
ds.l 1
r8 ds.l 1 ; 144
ds.l 1
r9 ds.l 1 ; 14c
ds.l 1
r10 ds.l 1 ; 154
ds.l 1
r11 ds.l 1 ; 15c
ds.l 1
r12 ds.l 1 ; 164
ds.l 1
r13 ds.l 1 ; 16c
ds.l 1
r14 ds.l 1 ; 174
ds.l 1
r15 ds.l 1 ; 17c
ds.l 1
r16 ds.l 1 ; 184
ds.l 1
r17 ds.l 1 ; 18c
ds.l 1
r18 ds.l 1 ; 194
ds.l 1
r19 ds.l 1 ; 19c
ds.l 1
r20 ds.l 1 ; 1a4
ds.l 1
r21 ds.l 1 ; 1ac
ds.l 1
r22 ds.l 1 ; 1b4
ds.l 1
r23 ds.l 1 ; 1bc
ds.l 1
r24 ds.l 1 ; 1c4
ds.l 1
r25 ds.l 1 ; 1cc
ds.l 1
r26 ds.l 1 ; 1d4
ds.l 1
r27 ds.l 1 ; 1dc
ds.l 1
r28 ds.l 1 ; 1e4
ds.l 1
r29 ds.l 1 ; 1ec
ds.l 1
r30 ds.l 1 ; 1f4
ds.l 1
r31 ds.l 1 ; 1fc
FloatRegisters ds.d 32 ; 200:300
endr

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;_______________________________________________________________________
; Configuration Info Record
; Used to pass Configuration information from the Boot Program to the
; NanoKernel for data structure and address mapping initialization.
;_______________________________________________________________________
NKConfigurationInfo record 0,increment
ROMByteCheckSums ds.l 8 ; 000 ; ROM Checksums - one word for each of 8 byte lanes
ROMCheckSum64 ds.l 2 ; 020 ; ROM Checksum - 64 bit sum of doublewords
ROMImageBaseOffset ds.l 1 ; 028 ; Offset of Base of total ROM image
ROMImageSize ds.l 1 ; 02c ; Number of bytes in ROM image
ROMImageVersion ds.l 1 ; 030 ; ROM Version number for entire ROM
Mac68KROMOffset ds.l 1 ; 034 ; Offset of base of Macintosh 68K ROM
Mac68KROMSize ds.l 1 ; 038 ; Number of bytes in Macintosh 68K ROM
ExceptionTableOffset ds.l 1 ; 03c ; Offset of base of PowerPC Exception Table Code
ExceptionTableSize ds.l 1 ; 040 ; Number of bytes in PowerPC Exception Table Code
HWInitCodeOffset ds.l 1 ; 044 ; Offset of base of Hardware Init Code (field moved!)
HWInitCodeSize ds.l 1 ; 048 ; Number of bytes in Hardware Init Code
KernelCodeOffset ds.l 1 ; 04c ; Offset of base of NanoKernel Code
KernelCodeSize ds.l 1 ; 050 ; Number of bytes in NanoKernel Code
EmulatorCodeOffset ds.l 1 ; 054 ; Offset of base of Emulator Code
EmulatorCodeSize ds.l 1 ; 058 ; Number of bytes in Emulator Code
OpcodeTableOffset ds.l 1 ; 05c ; Offset of base of Opcode Table
OpcodeTableSize ds.l 1 ; 060 ; Number of bytes in Opcode Table
BootstrapVersion ds.b 16 ; 064 ; Bootstrap loader version info
BootVersionOffset ds.l 1 ; 074 ; offset within EmulatorData of BootstrapVersion
ECBOffset ds.l 1 ; 078 ; offset within EmulatorData of ECB
IplValueOffset ds.l 1 ; 07c ; offset within EmulatorData of IplValue
EmulatorEntryOffset ds.l 1 ; 080 ; offset within Emulator Code of entry point
KernelTrapTableOffset ds.l 1 ; 084 ; offset within Emulator Code of KernelTrapTable
TestIntMaskInit ds.l 1 ; 088 ; initial value for test interrupt mask
ClearIntMaskInit ds.l 1 ; 08c ; initial value for clear interrupt mask
PostIntMaskInit ds.l 1 ; 090 ; initial value for post interrupt mask
LA_InterruptCtl ds.l 1 ; 094 ; logical address of Interrupt Control I/O page
InterruptHandlerKind ds.b 1 ; 098 ; kind of handler to use
ds.b 3 ; 099 ; filler
LA_InfoRecord ds.l 1 ; 09c ; logical address of InfoRecord page
LA_KernelData ds.l 1 ; 0a0 ; logical address of KernelData page
LA_EmulatorData ds.l 1 ; 0a4 ; logical address of EmulatorData page
LA_DispatchTable ds.l 1 ; 0a8 ; logical address of Dispatch Table
LA_EmulatorCode ds.l 1 ; 0ac ; logical address of Emulator Code
MacLowMemInitOffset ds.l 1 ; 0b0 ; offset to list of LowMem addr/data values
PageAttributeInit ds.l 1 ; 0b4 ; default WIMG/PP settings for PTE creation
PageMapInitSize ds.l 1 ; 0b8 ; size of page mapping info
PageMapInitOffset ds.l 1 ; 0bc ; offset to page mapping info (from base of ConfigInfo)
PageMapIRPOffset ds.l 1 ; 0c0 ; offset of InfoRecord map info (from base of PageMap)
PageMapKDPOffset ds.l 1 ; 0c4 ; offset of KernelData map info (from base of PageMap)
PageMapEDPOffset ds.l 1 ; 0c8 ; offset of EmulatorData map info (from base of PageMap)
SegMaps
SegMap32SupInit ds.l 32 ; 0cc ; 32 bit mode Segment Map Supervisor space
SegMap32UsrInit ds.l 32 ; 14c ; 32 bit mode Segment Map User space
SegMap32CPUInit ds.l 32 ; 1cc ; 32 bit mode Segment Map CPU space
SegMap32OvlInit ds.l 32 ; 24c ; 32 bit mode Segment Map Overlay mode
BATRangeInit ds.l 32 ; 2cc ; BAT mapping ranges
BatMap32SupInit ds.l 1 ; 34c ; 32 bit mode BAT Map Supervisor space
BatMap32UsrInit ds.l 1 ; 350 ; 32 bit mode BAT Map User space
BatMap32CPUInit ds.l 1 ; 354 ; 32 bit mode BAT Map CPU space
BatMap32OvlInit ds.l 1 ; 358 ; 32 bit mode BAT Map Overlay mode
SharedMemoryAddr ds.l 1 ; 35c ; physical address of Mac/Smurf shared message mem
PA_RelocatedLowMemInit ds.l 1 ; 360 ; physical address of RelocatedLowMem
OpenFWBundleOffset ds.l 1 ; 364 ; Offset of base of OpenFirmware PEF Bundle
OpenFWBundleSize ds.l 1 ; 368 ; Number of bytes in OpenFirmware PEF Bundle
LA_OpenFirmware ds.l 1 ; 36c ; logical address of Open Firmware
PA_OpenFirmware ds.l 1 ; 370 ; physical address of Open Firmware
LA_HardwarePriv ds.l 1 ; 374 ; logical address of HardwarePriv callback
; Used to stop here, plus 8 bytes for cache block alignment (0x380 bytes).
; Now there be more!
Debug ds.w 1 ; 378 ; > 256 required for screen log
DebugThreshold equ 257
org 0x388
DebugFlags ds.l 1 ; 388 ; bit 1<< 1 required for screen log
NanodbgrFlagShift equ 0
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
LogFlagShift equ 1
LogFlagBit equ 31 - LogFlagShift
endr
;_______________________________________________________________________
; System Info Record
;
; Used to pass System information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKSystemInfoPtr equ $5FFFEFF0 ; logical address of NKSystemInfo record
NKSystemInfoVer equ $5FFFEFF4 ; version number of NKSystemInfo record
NKSystemInfoLen equ $5FFFEFF6 ; length of NKSystemInfo record
NKSystemInfo record 0,increment
PhysicalMemorySize ds.l 1 ; 000, irp+dc0 ; Number of bytes in Physical RAM
UsableMemorySize ds.l 1 ; 004, irp+dc4 ; Number of bytes in Usable RAM
LogicalMemorySize ds.l 1 ; 008, irp+dc8 ; Number of bytes in Logical RAM
HashTableSize ds.l 1 ; 00c, irp+dcc ; Number of bytes in Memory Hash Table
L2DataCacheTotalSize ds.l 1 ; 010, irp+dd0 ; number of bytes in the L2 Data Cache
L2InstCacheTotalSize ds.l 1 ; 014, irp+dd4 ; number of bytes in the L2 Instruction Cache
L2CombinedCaches ds.w 1 ; 018, irp+dd8 ; 1 <- combined or no cache, 0 <- split cache
L2InstCacheBlockSize ds.w 1 ; 01a, irp+dda ; number of bytes in a Block of the L2 Instruction Cache
L2DataCacheBlockSize ds.w 1 ; 01c, irp+ddc ; number of bytes in a Block of the L2 Data Cache
L2InstCacheAssociativity ds.w 1 ; 01e, irp+dde ; Associativity of the L2 Instruction Cache
L2DataCacheAssociativity ds.w 1 ; 020, irp+de0 ; Associativity of the L2 Data Cache
ds.b 2 ; 022, irp+de2 ; unused
ds.b 2 ; 024, irp+de4 ; unused
FlashManufacturerCode ds.b 1 ; 026, irp+de6 ; Flash ROM Manufacturer code
FlashDeviceCode ds.b 1 ; 027, irp+de7 ; Flash ROM Device code
FlashStart ds.l 1 ; 028, irp+de8 ; Starting address of Flash ROM
FlashSize ds.l 1 ; 02c, irp+dec ; Number of bytes in Flash ROM
Bank0Start ds.l 1 ; 030, irp+df0 ; Starting address of RAM bank 0
Bank0Size ds.l 1 ; 034, irp+df4 ; Number of bytes in RAM bank 0
Bank1Start ds.l 1 ; 038, irp+df8 ; Starting address of RAM bank 1
Bank1Size ds.l 1 ; 03c, irp+dfc ; Number of bytes in RAM bank 1
Bank2Start ds.l 1 ; 040, irp+e00 ; Starting address of RAM bank 2
Bank2Size ds.l 1 ; 044, irp+e04 ; Number of bytes in RAM bank 2
Bank3Start ds.l 1 ; 048, irp+e08 ; Starting address of RAM bank 3
Bank3Size ds.l 1 ; 04c, irp+e0c ; Number of bytes in RAM bank 3
Bank4Start ds.l 1 ; 050, irp+e10 ; Starting address of RAM bank 4
Bank4Size ds.l 1 ; 054, irp+e14 ; Number of bytes in RAM bank 4
Bank5Start ds.l 1 ; 058, irp+e18 ; Starting address of RAM bank 5
Bank5Size ds.l 1 ; 05c, irp+e1c ; Number of bytes in RAM bank 5
Bank6Start ds.l 1 ; 060, irp+e20 ; Starting address of RAM bank 6
Bank6Size ds.l 1 ; 064, irp+e24 ; Number of bytes in RAM bank 6
Bank7Start ds.l 1 ; 068, irp+e28 ; Starting address of RAM bank 7
Bank7Size ds.l 1 ; 06c, irp+e2c ; Number of bytes in RAM bank 7
Bank8Start ds.l 1 ; 070, irp+e30 ; Starting address of RAM bank 8
Bank8Size ds.l 1 ; 074, irp+e34 ; Number of bytes in RAM bank 8
Bank9Start ds.l 1 ; 078, irp+e38 ; Starting address of RAM bank 9
Bank9Size ds.l 1 ; 07c, irp+e3c ; Number of bytes in RAM bank 9
Bank10Start ds.l 1 ; 080, irp+e40 ; Starting address of RAM bank 10
Bank10Size ds.l 1 ; 084, irp+e44 ; Number of bytes in RAM bank 10
Bank11Start ds.l 1 ; 088, irp+e48 ; Starting address of RAM bank 11
Bank11Size ds.l 1 ; 08c, irp+e4c ; Number of bytes in RAM bank 11
Bank12Start ds.l 1 ; 090, irp+e50 ; Starting address of RAM bank 12
Bank12Size ds.l 1 ; 094, irp+e54 ; Number of bytes in RAM bank 12
Bank13Start ds.l 1 ; 098, irp+e58 ; Starting address of RAM bank 13
Bank13Size ds.l 1 ; 09c, irp+e5c ; Number of bytes in RAM bank 13
Bank14Start ds.l 1 ; 0a0, irp+e60 ; Starting address of RAM bank 14
Bank14Size ds.l 1 ; 0a4, irp+e64 ; Number of bytes in RAM bank 14
Bank15Start ds.l 1 ; 0a8, irp+e68 ; Starting address of RAM bank 15
Bank15Size ds.l 1 ; 0ac, irp+e6c ; Number of bytes in RAM bank 15
Bank16Start ds.l 1 ; 0b0, irp+e70 ; Starting address of RAM bank 16
Bank16Size ds.l 1 ; 0b4, irp+e74 ; Number of bytes in RAM bank 16
Bank17Start ds.l 1 ; 0b8, irp+e78 ; Starting address of RAM bank 17
Bank17Size ds.l 1 ; 0bc, irp+e7c ; Number of bytes in RAM bank 17
Bank18Start ds.l 1 ; 0c0, irp+e80 ; Starting address of RAM bank 18
Bank18Size ds.l 1 ; 0c4, irp+e84 ; Number of bytes in RAM bank 18
Bank19Start ds.l 1 ; 0c8, irp+e88 ; Starting address of RAM bank 19
Bank19Size ds.l 1 ; 0cc, irp+e8c ; Number of bytes in RAM bank 19
Bank20Start ds.l 1 ; 0d0, irp+e90 ; Starting address of RAM bank 20
Bank20Size ds.l 1 ; 0d4, irp+e94 ; Number of bytes in RAM bank 20
Bank21Start ds.l 1 ; 0d8, irp+e98 ; Starting address of RAM bank 21
Bank21Size ds.l 1 ; 0dc, irp+e9c ; Number of bytes in RAM bank 21
Bank22Start ds.l 1 ; 0e0, irp+ea0 ; Starting address of RAM bank 22
Bank22Size ds.l 1 ; 0e4, irp+ea4 ; Number of bytes in RAM bank 22
Bank23Start ds.l 1 ; 0e8, irp+ea8 ; Starting address of RAM bank 23
Bank23Size ds.l 1 ; 0ec, irp+eac ; Number of bytes in RAM bank 23
Bank24Start ds.l 1 ; 0f0, irp+eb0 ; Starting address of RAM bank 24
Bank24Size ds.l 1 ; 0f4, irp+eb4 ; Number of bytes in RAM bank 24
Bank25Start ds.l 1 ; 0f8, irp+eb8 ; Starting address of RAM bank 25
Bank25Size ds.l 1 ; 0fc, irp+ebc ; Number of bytes in RAM bank 25
EndOfBanks
MaxBanks equ 26 ; Pads out to old struct len (cache block), more to come...
; Interrupt Support Data
IntCntrBaseAddr ds.l 1 ; 100, irp+ec0 ; Interrupt Controller Base Address (variable is used since this is a PCI Dev and address is relocatable)
IntPendingReg ds.l 2 ; 104, irp+ec4 ; Data of current interrupts pending register
; These fields were added to report information about tightly-coupled L2 caches.
; The inline L2 information should be used in situations where there is a CPU
; card L2 cache that can coexist with a motherboard L2.
InlineL2DSize ds.l 1 ; 10c, irp+ecc ; Size of in-line L2 Dcache
InlineL2ISize ds.l 1 ; 110, irp+ed0 ; Size of in-line L2 Icache
InlineL2Combined ds.w 1 ; 114, irp+ed4 ; 1 <- combined or no cache, 0 <- split cache
InlineL2IBlockSize ds.w 1 ; 116, irp+ed6 ; Block size of in-line I L2 cache
InlineL2DBlockSize ds.w 1 ; 118, irp+ed8 ; Block size of in-line D L2 cache
InlineL2IAssoc ds.w 1 ; 11a, irp+eda ; Associativity of L2 I
InlineL2DAssoc ds.w 1 ; 11c, irp+edc ; Associativity of L2 D
ds.w 1 ; 11e, irp+ede ; pad
; More Interrupt Support Data
IntsCompleted ds.l 2 ; 120, irp+ee0 ; completed interrupts
align 5 ; pad to nice cache block alignment
endr
;_______________________________________________________________________
; Diagnostic Info Record
;
; Used to pass Diagnostic information from the power on Diagnostics to
; the NanoKernel, and from the NanoKernel to user mode software.
;_______________________________________________________________________
NKDiagInfoPtr equ $5FFFEFE8 ; logical address of DiagnosticInfo record
NKDiagInfoVer equ $5FFFEFEC ; version number of DiagnosticInfo record
NKDiagInfoLen equ $5FFFEFEE ; length of DiagnosticInfo record
NKDiagInfo record 0,increment
BankMBFailOffset ds.l 1 ; 000 ; Mother Board RAM failure code
BankAFailOffset ds.l 1 ; 004 ; Bank A RAM failure code
BankBFailOffset ds.l 1 ; 008 ; Bank B RAM failure code
BankCFailOffset ds.l 1 ; 00c ; Bank C RAM failure code
BankDFailOffset ds.l 1 ; 010 ; Bank D RAM failure code
BankEFailOffset ds.l 1 ; 014 ; Bank E RAM failure code
BankFFailOffset ds.l 1 ; 018 ; Bank F RAM failure code
BankGFailOffset ds.l 1 ; 01c ; Bank G RAM failure code
BankHFailOffset ds.l 1 ; 020 ; Bank H RAM failure code
CacheFailOffset ds.l 1 ; 024 ; cache failure code
LongBootParamOffset ds.l 1 ; 028 ; on longBoot this is where the params will be
POSTTraceOffset ds.l 1 ; 02c ; this tells us what route the POST took
POSTOldWarmOffset ds.l 1 ; 030 ; logged address of old warmstart flag
POSTOldLongOffset ds.l 1 ; 034 ; logged address of old long boot flag
POSTOldGlobbOffset ds.l 1 ; 038 ; logged address of old Diagnostic Info Record
POSTOldParamOffset ds.l 1 ; 03c ; the params from the old diag globb
POSTStartRTCUOffset ds.l 1 ; 040 ; PPC Real Time Clock Upper at start of POST
POSTStartRTCLOffset ds.l 1 ; 044 ; PPC Real Time Clock Lower at start of POST
POSTEndRTCUOffset ds.l 1 ; 048 ; PPC Real Time Clock Upper at end of POST
POSTEndRTCLOffset ds.l 1 ; 04c ; PPC Real Time Clock Lower at end of POST
POSTTestTypeOffset ds.l 1 ; 050 ; when long RAM tests fail test type which failed is put here
POSTError2Offset ds.l 1 ; 054 ; result codes from tests
POSTError3Offset ds.l 1 ; 058 ; result codes from tests
POSTError4Offset ds.l 1 ; 05c ; result codes from tests
RegistersStore ds.b 140 ; 060 ; store all 60x registers here, still fit into 256 bytes size.
; Everything BEFORE here is new (hence the funny-sized register store)
DiagPOSTResult2 ds.l 1 ; 0ec ; POST results
DiagPOSTResult1 ds.l 1 ; 0f0 ; POST results
DiagLongBootSig ds.l 1 ; 0f4 ; Burn in restart flag
DiagWarmStartHigh ds.l 1 ; 0f8 ; First long of native warm start (WLSC) <SM44>
DiagWarmStartLow ds.l 1 ; 0fc ; Second long of native warm start (SamB) <SM44>
align 5 ; pad to nice cache block alignment
endr
;_______________________________________________________________________
; NanoKernel Info Record
;
; Used to pass NanoKernel statistics from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKNanoKernelInfoPtr equ $5FFFEFE0 ; logical address of NanoKernelInfo record
NKNanoKernelInfoVer equ $5FFFEFE4 ; version number of NanoKernelInfo record
NKNanoKernelInfoLen equ $5FFFEFE6 ; length of NanoKernelInfo record
NKNanoKernelInfo record 0,increment
ExceptionCauseCounts ds.l 32 ; 000, kdp+dc0 ; counters per exception cause
NanoKernelCallCounts ds.l 16 ; 080, kdp+e40 ; counters per NanoKernel call
ExternalIntCount ds.l 1 ; 0c0, kdp+e80 ; count of External Interrupts
MisalignmentCount ds.l 1 ; 0c4, kdp+e84 ; count of Misalignment Interrupts
FPUReloadCount ds.l 1 ; 0c8, kdp+e88 ; count of FPU reloads on demand
DecrementerIntCount ds.l 1 ; 0cc, kdp+e8c ; count of Decrementer Interrupts
QuietWriteCount ds.l 1 ; 0d0, kdp+e90 ; count of Writes to Quiet Read-Only memory
HashTableCreateCount ds.l 1 ; 0d4, kdp+e94 ; count of Hash Table Entry creations
HashTableDeleteCount ds.l 1 ; 0d8, kdp+e98 ; count of Hash Table Entry deletions
HashTableOverflowCount ds.l 1 ; 0dc, kdp+e9c ; count of Hash Table Entry overflows
EmulatedUnimpInstCount ds.l 1 ; 0e0, kdp+ea0 ; count of Emulated unimplemented instructions
NCBPtrCacheMissCount ds.l 1 ; 0e4, kdp+ea4 ; count of NCB Pointer cache misses
ExceptionPropagateCount ds.l 1 ; 0e8, kdp+ea8 ; count of Exceptions propagated to system
ExceptionForcedCount ds.l 1 ; 0ec, kdp+eac ; count of Exceptions forced to system
SysContextCpuTime ds.l 2 ; 0f0, kdp+eb0 ; CPU Time used by System Context
AltContextCpuTime ds.l 2 ; 0f8, kdp+eb4 ; CPU Time used by Alternate Context
; This stuff is new (starts at 0x100)
blueProcessID ds.l 1 ; 100, kdp+ec0 ; ID of the blue process.
blueTaskID ds.l 1 ; 104, kdp+ec4 ; ID of the blue task.
pageQueueID ds.l 1 ; 108, kdp+ec8 ; ID of the page fault queue.
TaskCount ds.l 1 ; 10c, kdp+ecc ; Number of tasks.
FreePoolExtendCount ds.l 1 ; 110, kdp+ed0 ; Number of pages given to the nanokernel.
;rsrv1 ds.l 3 ; 114, kdp+ed4 ; reserved???
; My additions
org 0x11c
ConfigFlags ds.l 1 ; 11c, kdp+edc ; includes ScreenConsole ... TODO put flag equs here
NanodbgrFlagShift equ 1
NanodbgrFlagBit equ 31 - NanodbgrFlagShift
LogFlagShift equ 3
LogFlagBit equ 31 - LogFlagShift
; bit 31 always set on replacement, bit 27 set on replacement with ROM 2.7f3 or later
org 0x128
VMDispatchCountTblPtr ds.l 1 ; 128, kdp+ee8
ds.l 1
ds.l 1
MPDispatchCountTblPtr ds.l 1 ; 134, kdp+ef4 ; ???????
AddrSpcSetCtr ds.l 1 ; 138, kdp+ef8 ; incremented by SetAddrSpcRegisters
IDCtr ds.l 1 ; 13c, kdp+efc
org 0x160
endr
;_______________________________________________________________________
; Processor Info Record
;
; Used to pass Processor information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKProcessorInfoPtr equ $5FFFEFD8 ; logical address of ProcessorInfo record
NKProcessorInfoVer equ $5FFFEFDC ; version number of ProcessorInfo record
NKProcessorInfoLen equ $5FFFEFDE ; length of ProcessorInfo record
NKProcessorInfo record 0,increment
ProcessorVersionReg ds.l 1 ; 000, kdp+f20 ; contents of the PVR special purpose register
CpuClockRateHz ds.l 1 ; 004, kdp+f24 ; CPU Clock frequency
BusClockRateHz ds.l 1 ; 008, kdp+f28 ; Bus Clock frequency
DecClockRateHz ds.l 1 ; 00c, kdp+f2c ; Decrementer Clock frequency
Ovr
PageSize ds.l 1 ; 010, kdp+f30 ; number of bytes in a memory page
DataCacheTotalSize ds.l 1 ; 014, kdp+f34 ; number of bytes in the Data Cache
InstCacheTotalSize ds.l 1 ; 018, kdp+f38 ; number of bytes in the Instruction Cache
CoherencyBlockSize ds.w 1 ; 01c, kdp+f3c ; number of bytes in a Coherency Block
ReservationGranuleSize ds.w 1 ; 01e, kdp+f3e ; number of bytes in a Reservation Granule
CombinedCaches ds.w 1 ; 020, kdp+f40 ; 1 <- combined or no cache, 0 <- split cache
InstCacheLineSize ds.w 1 ; 022, kdp+f42 ; number of bytes in a Line of the Instruction Cache
DataCacheLineSize ds.w 1 ; 024, kdp+f44 ; number of bytes in a Line of the Data Cache
DataCacheBlockSizeTouch ds.w 1 ; 026, kdp+f46 ; number of bytes in a Block for DCBT DCBTST
InstCacheBlockSize ds.w 1 ; 028, kdp+f48 ; number of bytes in a Block of the Instruction Cache
DataCacheBlockSize ds.w 1 ; 02a, kdp+f4a ; number of bytes in a Block of the Data Cache
InstCacheAssociativity ds.w 1 ; 02c, kdp+f4c ; Associativity of the Instruction Cache
DataCacheAssociativity ds.w 1 ; 02e, kdp+f4e ; Associativity of the Data Cache
TransCacheTotalSize ds.w 1 ; 030, kdp+f50 ; number of entries in the Translation Cache
TransCacheAssociativity ds.w 1 ; 032, kdp+f52 ; Associativity of the Translation Cache
OvrEnd
; These fields were added to report information about back-side L2 caches
ProcessorL2DSize ds.l 1 ; 034, kdp+f54 ; Size of back-side L2 Dcache
ProcessorL2ISize ds.l 1 ; 038, kdp+f58 ; Size of back-side L2 Icache
ProcessorL2Combined ds.w 1 ; 03c, kdp+f5c ; 1 <- combined or no cache, 0 <- split cache
ProcessorL2IBlockSize ds.w 1 ; 03e, kdp+f5e ; Block size of back-side I L2 cache
ProcessorL2DBlockSize ds.w 1 ; 040, kdp+f60 ; Block size of back-side D L2 cache
ProcessorL2IAssoc ds.w 1 ; 042, kdp+f62 ; Associativity of L2 I
ProcessorL2DAssoc ds.w 1 ; 044, kdp+f64 ; Associativity of L2 D
filler1 ds.w 1 ; 046, kdp+f66 ; align to long
; ProcessorFlags - Definitions for the processor flags field. These are bit positions,
; as in 1 << hasVMX, and not masks.
hasL2CR equ 0
hasPLRUL1 equ 1
hasTAU equ 2
hasVMX equ 3
unknownFlag equ 4
hasExtraBATs equ 5
ProcessorFlags ds.l 1 ; 048, kdp+f68 ; flags to specify processor features
align 5 ; pad to nice cache block alignment
org 0x05e
SetToZero ds.w 1 ; 05e, kdp+f7e ; by same code that sets below
CpuClockRateHzCopy ds.l 1 ; 060, kdp+f80 ; copies by Init.s
BusClockRateHzCopy ds.l 1 ; 064, kdp+f84 ; copies by Init.s
DecClockRateHzCopy ds.l 1 ; 068, kdp+f88 ; copies by Init.s
endr
;_______________________________________________________________________
; Hardware Info Record
;
; Used to pass hardware information from the NanoKernel to user mode
; software.
;_______________________________________________________________________
NKHWInfoPtr equ $5FFFEFD0 ; logical address of HWInfo record
NKHWInfoVer equ $5FFFEFD4 ; version number of HWInfo record
NKHWInfoLen equ $5FFFEFD6 ; length of HWInfo record
NKHWInfo record 0,increment
MacROM_Base ds.l 1 ; 000, irp+f00 ; base address (physical) of Mac ROM
DeviceTreeBase ds.l 1 ; 004, irp+f04 ; base address of the copied device tree properties
UniversalInfoTableBase ds.l 1 ; 008, irp+f08 ; base address of the Universal Info Table
ConfigInfoTableBase ds.l 1 ; 00c, irp+f0c ; base address of the Config Info Table
VectorLookupTable ds.l 1 ; 010, irp+f10 ; base address of the interrupt vector lookup table (short *)
VectorMaskTable ds.l 1 ; 014, irp+f14 ; base address of the interrupt vector mask table (long *)
OpenPICBaseAddr ds.l 1 ; 018, irp+f18 ; OpenPIC base address
ISAMaster8259 ds.l 1 ; 01c, irp+f1c ; ISA Master 8259 ports (char *)
ISASlave8259 ds.l 1 ; 020, irp+f20 ; ISA Slave 8259 ports (char *)
InterruptAck8259 ds.l 1 ; 024, irp+f24 ; address to read to ack 8259 interrupt (long *)
; interrupt pending bits (actively changing)
PendingInts ds.l 2 ; 028, irp+f28 ; 64 bits of pending interrupts
; some Mac I/O device base addresses
ADB_Base ds.l 1 ; 030, irp+f30 ; base address of ADB
SCSI_DMA_Base ds.l 1 ; 034, irp+f34 ; base address of SCSI DMA registers
; RTAS related stuff
RTAS_PrivDataArea ds.l 1 ; 038, irp+f38 ; RTAS private data area
MacOS_NVRAM_Offset ds.l 1 ; 03c, irp+f3c ; offset into nvram to MacOS data
RTAS_NVRAM_Fetch ds.l 1 ; 040, irp+f40 ; token for RTAS NVRAM fetch
RTAS_NVRAM_Store ds.l 1 ; 044, irp+f44 ; token for RTAS NVRAM store
RTAS_Get_Clock ds.l 1 ; 048, irp+f48 ; token for RTAS clock get
RTAS_Set_Clock ds.l 1 ; 04c, irp+f4c ; token for RTAS clock set
RTAS_Restart ds.l 1 ; 050, irp+f50 ; token for RTAS Restart
RTAS_Shutdown ds.l 1 ; 054, irp+f54 ; token for RTAS Shutdown
RTAS_Restart_At ds.l 1 ; 058, irp+f58 ; token for RTAS system startup at specified time
RTAS_EventScan ds.l 1 ; 05c, irp+f5c ; token for RTAS event scan
RTAS_Check_Exception ds.l 1 ; 060, irp+f60 ; token for RTAS check exception
RTAS_Read_PCI_Config ds.l 1 ; 064, irp+f64 ; token for RTAS read PCI config
RTAS_Write_PCI_Config ds.l 1 ; 068, irp+f68 ; token for RTAS write PCI config
; SIO interrupt source numbers for the MPIC
SIOIntVect ds.w 1 ; 06c, irp+f6c ; SIO (8259 cascade vector) vector number
SIOIntBit ds.w 1 ; 06e, irp+f6e ; SIO (8259 cascade vector) bit number
Signature ds.l 1 ; 070, irp+f70 ; signature for this record ('Hnfo')
; more interrupt source numbers
SpuriousIntVect ds.w 1 ; 074, irp+f74 ; spurious vector number
CPU_ID ds.w 1 ; 076, irp+f76 ; the ID of this CPU (universal-tables-related)
SCCAIntVect ds.w 1 ; 078, irp+f78 ; SCC A (non-DMA) vector number
SCCBIntVect ds.w 1 ; 07a, irp+f7a ; SCC B (non-DMA) vector number
SCSIIntVect ds.w 1 ; 07c, irp+f7c ; SCSI vector number
SCSIDMAIntVect ds.w 1 ; 07e, irp+f7e ; SCSI DMA vector number
VIAIntVect ds.w 1 ; 080, irp+f80 ; VIA vector number
VIAIntBit ds.w 1 ; 082, irp+f82 ; VIA bit number
ADBIntVect ds.w 1 ; 084, irp+f84 ; vector number
NMIIntVect ds.w 1 ; 086, irp+f86 ; NMI vector number
NMIIntBit ds.w 1 ; 088, irp+f88 ; NMI bit number
; current (actively changing) interrupt handling variables
ISAPendingInt ds.w 1 ; 08a, irp+f8a ; currently pending ISA/8259 interrupt
CompletedInts ds.b 8 ; 08c, irp+f8c ; completed interrupts
nkHWInfoFlagSlowMESH equ 1 ; set if fast MESH doesn't work on this box
nkHWInfoFlagAsynchMESH equ 2 ; set if Synchronous MESH doesn't work on this box
nkHWInfoFlagNoCopySWTLB equ 4 ; set if the software TLB walk code for 603 should NOT be copied
HardwareInfoFlags ds.l 1 ; 094, irp+f94 ; 32 bits of flags (see enum above)
RTAS_Get_PowerOn_Time ds.l 1 ; 098, irp+f98 ; token for RTAS getting time for system startup
align 5 ; pad to nice cache block alignment (did i get this right?)
endr
;_______________________________________________________________________
; Processor State Record
;
; Used to save the state of the processor across sleep.
;_______________________________________________________________________
NKProcessorStatePtr equ $5FFFEFC8 ; logical address of ProcessorState record
NKProcessorStateVer equ $5FFFEFCC ; version number of ProcessorState record
NKProcessorStateLen equ $5FFFEFCE ; length of ProcessorState record
NKProcessorState record 0,increment
saveDBAT0u ds.l 1 ; 000 ; place to store DBAT0U
saveDBAT0l ds.l 1 ; 004 ; place to store DBAT0L
saveDBAT1u ds.l 1 ; 008 ; place to store DBAT1U
saveDBAT1l ds.l 1 ; 00c ; place to store DBAT1L
saveDBAT2u ds.l 1 ; 010 ; place to store DBAT2U
saveDBAT2l ds.l 1 ; 014 ; place to store DBAT2L
saveDBAT3u ds.l 1 ; 018 ; place to store DBAT3U
saveDBAT3l ds.l 1 ; 01c ; place to store DBAT3L
saveIBAT0u ds.l 1 ; 020 ; place to store IBAT0U
saveIBAT0l ds.l 1 ; 024 ; place to store IBAT0L
saveIBAT1u ds.l 1 ; 028 ; place to store IBAT1U
saveIBAT1l ds.l 1 ; 02c ; place to store IBAT1L
saveIBAT2u ds.l 1 ; 030 ; place to store IBAT2U
saveIBAT2l ds.l 1 ; 034 ; place to store IBAT2L
saveIBAT3u ds.l 1 ; 038 ; place to store IBAT3U
saveIBAT3l ds.l 1 ; 03c ; place to store IBAT3L
saveSPRG0 ds.l 1 ; 040 ; place to store SPRG0
saveSPRG1 ds.l 1 ; 044 ; place to store SPRG1
saveSPRG2 ds.l 1 ; 048 ; place to store SPRG2
saveSPRG3 ds.l 1 ; 04c ; place to store SPRG3
saveL2CR ds.l 1 ; 050 ; place to store Arthur's L2CR
saveSRR0 ds.l 1 ; 054 ; place to store SRR0
saveSRR1 ds.l 1 ; 058 ; place to store SRR1
saveTBU ds.l 1 ; 05c ; place to store TBU
saveTBL ds.l 1 ; 060 ; place to store TBL
saveHID0 ds.l 1 ; 064 ; place to store HID0
saveDEC ds.l 1 ; 068 ; place to store DEC
saveMSR ds.l 1 ; 06c ; place to store MSR
saveSDR1 ds.l 1 ; 070 ; place to store SDR1
; saveKernelDataPtr needs to always be right after saveReturnAddr
; because of how the code works. DO NOT CHANGE THIS ORDERING!
saveReturnAddr ds.l 1 ; 074 ; place to store the addr to jump to.
saveKernelDataPtr ds.l 1 ; 078 ; place to store the KernelDataPtr
saveContextPtr ds.l 1 ; 07c ; place to store the ContextPtr
endr

544
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; Opaque NanoKernel structures:
; - stored in the NanoKernel pool (not always)
; - associated with a class number and opaque ID (not always)
; - referenced by opaque ID (for MPLibrary's benefit)
;_______________________________________________________________________
; ID CLASS 1: PROCESS
; (size: 32b, thud command: id -p)
;
; The NanoKernel's internal representation of a cooperative process
; within the blue environment. Processes and tasks have a many-to-one
; relationship.
;
; There is a special 'blue' process that owns the blue task and all
; the CPU idle tasks.
;_______________________________________________________________________
Process record 0,INCR
kIDClass equ 1
kSignature equ 'PROC'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04 ; 'PROC'
Unused ds.l 1 ; 08 ; MPCall_5 does something here
SystemAddressSpaceID ds.l 1 ; 0c ; set by Init.s after addrspc creation
TaskCount ds.l 1 ; 10 ; incremented by CreateTask
SystemAddressSpacePtr ds.l 1 ; 14
AddressSpaceCount ds.l 1 ; 18 ; incremented by NKCreateAddressSpaceSub
ds.l 1 ; 1c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 2: TASK
; (size: 1k, thud command: id -t)
;
; What the MPLibrary and NanoKernel call the unit of multitasking.
; (Remember that 'Thread' and 'Process' were taken.)
;
; Contains space for a ContextBlock in the style of the ECB, but
; blue's ContextBlockPtr is redirected to the ECB.
;_______________________________________________________________________
Task record 0,INCR
kIDClass equ 2
kSignature equ 'TASK'
;_______________________
; Task priorities
;_______________________
kCriticalPriority equ 0
kLatencyProtectPriority equ 1
kNominalPriority equ 2
kIdlePriority equ 3
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 000
Signature ds.l 1 ; 004
QueueMember ds.l 4 ; 008:018 ; a task is always a member of a queue, e.g. the RDYQ
MysteryByte1 ds.b 1 ; 018 ; CreateTask sets 0 by default (blue = 2)
Priority ds.b 1 ; 019 ; CreateTask sets 2 by default
MysteryHalf ds.w 1 ; 01a
Weight ds.l 1 ; 01c ; default is 100, blue gets 200, idle gets 1
ds.l 1 ; 020
ds.l 1 ; 024
ds.l 1 ; 028
ds.l 1 ; 02c
ds.l 1 ; 030
ds.l 1 ; 034
ds.l 1 ; 038
ds.l 1 ; 03c
ds.l 1 ; 040
ds.l 1 ; 044
ds.l 1 ; 048
ds.l 1 ; 04c
ds.l 1 ; 050
ds.l 1 ; 054
ds.l 1 ; 058
ds.l 1 ; 05c
ProcessID ds.l 1 ; 060
ThingThatAlignVecHits ds.l 1 ; 064 ; IntAlignment is interested in bit 9, MPCall 116 in bit 15
ds.l 1 ; 068
OwningProcessPtr ds.l 1 ; 06c
AddressSpacePtr ds.l 1 ; 070 ; borrowed from PROC argument to CreateTask
Name ds.l 1 ; 074 ; 'blue', creator of owning cooperative process, etc
CpuID ds.l 1 ; 078
ds.l 1 ; 07c
CreateTime3 ds.d 1 ; 080
ContextBlockPtr ds.l 1 ; 088 ; points internally by default, and to EDP.ECB in blue
VectorSaveArea ds.l 1 ; 08c
ds.l 1 ; 090
ds.l 1 ; 094
ds.l 1 ; 098
NotificationPtr ds.l 1 ; 09c
SemaphoreLLL ds.l 4 ; 0a0:0b0
Zero ds.l 1 ; 0b0
One ds.l 1 ; 0b4
ds.l 1 ; 0b8
ds.l 1 ; 0bc
Zero1 ds.l 1 ; 0c0
Zero2 ds.l 1 ; 0c4
CreateTime1 ds.d 1 ; 0c8
CreateTime2 ds.d 1 ; 0d0
ds.l 1 ; 0d8
ds.l 1 ; 0dc
Zero3 ds.l 1 ; 0e0
Zero4 ds.l 1 ; 0e4
Zero5 ds.l 1 ; 0e8
ds.l 1 ; 0ec
YellowVecTblPtr ds.l 1 ; 0f0
ds.l 1 ; 0f4
ds.l 1 ; 0f8
ds.l 1 ; 0fc
ContextBlock ds.b 768 ; 100:400 ; like the EDP's Emulator Context Block -- unsure of size
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 3: TIMER
; (size: 64b, thud command: id -tm)
;
;_______________________________________________________________________
Timer record 0,INCR
kIDClass equ 3
kSignature equ 'TIME'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
ds.l 1 ; 08
ds.l 1 ; 0c
ProcessID ds.l 1 ; 10
ds.l 1 ; 14
ds.l 1 ; 18
ds.l 1 ; 1c
ds.l 1 ; 20
ds.l 1 ; 24
ds.l 1 ; 28
ds.l 1 ; 2c
ds.l 1 ; 30
ds.l 1 ; 34
ds.l 1 ; 38
ds.l 1 ; 3c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 4: QUEUE
; (size: 52b, thud command: id -q)
;
;_______________________________________________________________________
Queue record 0,INCR
kIDClass equ 4
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10
ds.l 4 ; 10:20
ProcessID ds.l 1 ; 20
ds.l 1 ; 24
ds.l 1 ; 28
ds.l 1 ; 2c
ds.l 1 ; 30
Size equ *
endr
ReadyQueue record 0,INCR
LLL ds.l 4 ; 00:10 ; nothing fancy
Counter ds.l 1 ; 10 ; InitRDYQs sets, TaskReadyAsNext bumps
TotalWeight ds.l 1 ; 14 ; divide available time by these
Timecake ds.d 1 ; 18 ; period of ~1ms, 8ms, 64ms, 512ms
org 0x20
; Constants
kSignature equ 'RDYQ'
endr
kTimerQueueSignature equ 'TMRQ'
kDelayQueueSignature equ 'DLYQ'
kDbugQueueSignature equ 'DBUG'
kPageQueueSignature equ 'PAGQ'
kNotQueueSignature equ 'NOTQ'
kSemaQueueSignature equ 'SEMQ'
;_______________________________________________________________________
; ID CLASS 5: SEMAPHORE
; (size: 32b, thud command: id -s)
;
;_______________________________________________________________________
Semaphore record 0,INCR
kIDClass equ 5
kSignature equ 'SEMA'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10
ds.l 1 ; 10
ds.l 1 ; 14
ProcessID ds.l 1 ; 18
ds.l 1 ; 1c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 6: CRITICAL REGION
; (size: 36b, thud command: id -r)
;
;_______________________________________________________________________
CriticalRegion record 0,INCR
kIDClass equ 6
kSignature equ 'CRGN'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10
ProcessID ds.l 4 ; 10:20 ; lll.freeform is the field?
ds.l 1 ; 20
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 7: CPU
; (size: 32+800+128 = 960b, thud command: id -c)
;
;_______________________________________________________________________
CPU record 0,INCR
kIDClass equ 7
kSignature equ 'CPU '
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
CgrpList ds.l 4 ; 08:18
Eff ds.l 1 ; 18 ; contains 0x0000000f
IdleTaskPtr ds.l 1 ; 1c
EWABase ds.b 800 ; negative-indexed parts of EWA
EWA ds.b 128 ; positive-indexed parts of EWA
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 8: ADDRESS SPACE
; (size: 192b, thud command: id -sp)
;
;_______________________________________________________________________
AddressSpace record 0,INCR
kIDClass equ 8
kSignature equ 'SPAC'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
ds.l 1 ; 08
TaskCount ds.l 1 ; 0c ; incremented by CreateTask
RsrvList ds.l 4 ; 10:20 ; LLL
AreaList ds.l 4 ; 20:30 ; LLL
SRs ds.l 16 ; 30:70 ; segment register values
ParentCoherenceSpecialPtr ds.l 1 ; 70 ; SpecialPtr of owning cgrp (in list owned by Cpu)
ProcessID ds.l 1 ; 74 ; ID of owning PROC
ds.l 1 ; 78
ds.l 1 ; 7c
BATs
BAT0U ds.l 1 ; 80
BAT0L ds.l 1 ; 84
BAT1U ds.l 1 ; 88
BAT1L ds.l 1 ; 8c
BAT2U ds.l 1 ; 90
BAT2L ds.l 1 ; 94
BAT3U ds.l 1 ; 98
BAT3L ds.l 1 ; 9c
ExtraBATs ; the flag that enables these is never set?
ExtraBAT0U ds.l 1 ; a0
ExtraBAT0L ds.l 1 ; a4
ExtraBAT1U ds.l 1 ; a8
ExtraBAT1L ds.l 1 ; ac
ExtraBAT2U ds.l 1 ; b0
ExtraBAT2L ds.l 1 ; b4
ExtraBAT3U ds.l 1 ; b8
ExtraBAT3L ds.l 1 ; bc
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 9: EVENT GROUP
; (size: 32b, thud command: id -e)
;
;_______________________________________________________________________
EventGroup record 0,INCR
kIDClass equ 9
kSignature equ 'EVNT'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10 ; first field is ID
ds.l 1 ; 10
ProcessID ds.l 1 ; 14
ds.l 1 ; 18 ; contains 1-8 +/- 16
ds.l 1 ; 1c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 10: COHERENCE GROUP
; (size: 88b, thud command: id -cg)
;
;_______________________________________________________________________
CoherenceGroup record 0,INCR
kIDClass equ 10
kSignature equ 'CGRP'
;_______________________
; Fields
;_______________________
LLL ds.l 4 ; 00:10 ; element in CpuStructs list of cgrps
GRPSList ds.l 4 ; 10:20 ; my own list of GRPSes (what are they?)
CpuCount ds.l 1 ; 20
ScheduledCpuCount ds.l 1 ; 24
ds.l 1 ; 28
ds.l 1 ; 2c
ds.l 1 ; 30
ds.l 1 ; 34
ds.l 1 ; 38
ds.l 1 ; 3c
ds.l 1 ; 40
ds.l 1 ; 44
Incrementer ds.l 1 ; 48 ; number of NKCreateAddressSpaceSub calls % 1M
ds.l 1 ; 4c
ds.l 1 ; 50
ds.l 1 ; 54
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 11: AREA
; (size: 160b, thud command: id -a)
;
; A contiguous region of effective addresses with similar properties.
;_______________________________________________________________________
Area record 0,INCR
kIDClass equ 11
kSignature equ 'AREA'
;_______________________
; Fields
;_______________________
ID ds.l 1 ; 00
Signature ds.l 1 ; 04
TwoFiftySix ds.l 1 ; 08
ProcessID ds.l 1 ; 0c
AddressSpaceID ds.l 1 ; 10
ds.l 1 ; 14
ds.l 1 ; 18
ds.l 1 ; 1c
ds.l 1 ; 20
LogicalBase ds.l 1 ; 24
LogicalBase2 ds.l 1 ; 28
Length ds.l 1 ; 2c ; in actual bytes!
Zero ds.l 1 ; 30
ds.l 1 ; 34
Length2 ds.l 1 ; 38
ds.l 1 ; 3c
ds.l 1 ; 40
ds.l 1 ; 44
ds.l 1 ; 48
ds.l 1 ; 4c
ds.l 1 ; 50
LLL ds.l 4 ; 54:64 ; member of address space
ds.l 1 ; 64
ds.l 1 ; 68
AddressSpacePtr ds.l 1 ; 6c
ds.l 1 ; 70
ds.l 1 ; 74
ds.l 1 ; 78
ds.l 1 ; 7c
ds.l 1 ; 80
ds.l 1 ; 84
ds.l 1 ; 88
ds.l 1 ; 8c
ds.l 1 ; 90
ds.l 1 ; 94
ds.l 1 ; 98
ds.l 1 ; 9c
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 12: NOTIFICATION
; (size: 40b, thud command: id -n)
;
;_______________________________________________________________________
Notification record 0,INCR
kIDClass equ 12
kSignature equ 'KNOT'
;_______________________
; Fields
;_______________________
ds.l 1 ; 00
Signature ds.l 1 ; 04
ProcessID ds.l 1 ; 08
ds.l 1 ; 0c
ds.l 1 ; 10
ds.l 1 ; 14
ds.l 1 ; 18
ds.l 1 ; 1c
ds.l 1 ; 20
ds.l 1 ; 24
Size equ *
endr
;_______________________________________________________________________
; ID CLASS 13: CONSOLE LOG
; (size: 16b, thud command: id -nc)
;
; Never seen one in the wild -- must have been in debug builds.
;_______________________________________________________________________
ConsoleLog record 0,INCR
kIDClass equ 13
;_______________________
; Fields
;_______________________
ds.l 1 ; 00
ds.l 1 ; 04
ProcessID ds.l 1 ; 08
ds.l 1 ; 0c
Size equ *
endr

1001
Internal/NKPublic.a Normal file
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151
Linker/LinkPowerROM Normal file
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Set Streamer " | StreamEdit -d -e '/?Å/ Pr ¶¶¶"1¶¶¶"'"
If {#} ¶< 2
Echo "USAGE: {0} DEST SRC ... > ShellScript"
Exit 1
End
Set DestFile "{1}"
Shift
Set TempPrepFile "{TempFolder}PPCROMLinkPrepCmds"
Set TempCmdFile "{TempFolder}PPCROMLinkCmds"
Echo -n "" > "{TempPrepFile}"
Echo -n "PPCLink -xm library -codestart 0 -warn -o " > "{TempCmdFile}"
Quote -n "{DestFile}.x" >> "{TempCmdFile}"
Set OffsetSoFar 0
Set NeedTool 1 # Always extract binary, so always need tool
Loop # over arguments
If !{#}
Break
End
If "{1}" =~ /[0-9]+/ || "{1}" =~ /0x[0-9a-f]+/
# Move-to-offset argument (hex or decimal literal)
If `Evaluate {1} ¶< {OffsetSoFar}`
Echo "{0} failed: cannot pad to offset {1} because we are already past it!"
Exit 1
End
Set Delta `Evaluate -h {1} - {OffsetSoFar}`
If {Delta}
Echo -n "Set F ¶"¶{TempFolder¶}Zeros_{Delta}.s¶";¶t" >> "{TempPrepFile}"
Echo -n 'If !`Exists "{F}"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '`; ' >> "{TempPrepFile}"
Echo -n "Echo ¶¶tDCB.B {Delta}, 0" '> "{F}"; ' >> "{TempPrepFile}"
Echo -n 'PPCAsm "{F}"; ' >> "{TempPrepFile}"
Echo "End" >> "{TempPrepFile}"
Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}"
Echo -n "¶"¶{TempFolder¶}Zeros_{Delta}.s.o¶"" >> "{TempCmdFile}"
Set OffsetSoFar {1}
End
Else If "{1}" =~ /([A-Za-z0-9]+)¨1:/
# Label argument
Echo -n "Set F ¶"¶{TempFolder¶}{¨1}.s¶";¶t" >> "{TempPrepFile}"
Echo -n 'If !`Exists "{F}"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '`; ' >> "{TempPrepFile}"
Echo -n "Echo ¶¶tEXPORT {¨1}¶¶n{¨1}" '> "{F}"; ' >> "{TempPrepFile}"
Echo -n 'PPCAsm "{F}"; ' >> "{TempPrepFile}"
Echo "End" >> "{TempPrepFile}"
Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}"
Echo -n "¶"¶{TempFolder¶}{¨1}.s.o¶"" >> "{TempCmdFile}"
Else
# Filename argument
If "{1}" !~ /Å.x/
Echo -n "Set F " >> "{TempPrepFile}"
Quote -n "{1}" >> "{TempPrepFile}"
Echo -n "; " >> "{TempPrepFile}"
Echo -n 'If !`Exists "{F}.x"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '` || `Newer "{F}" "{F}.x"' >> "{TempPrepFile}"
Echo -n "{Streamer}" >> "{TempPrepFile}"
Echo -n '`; ' >> "{TempPrepFile}"
Quote -n "{0}.tool" >> "{TempPrepFile}"
Echo -n ' tox "{F}" "{F}.x"; ' >> "{TempPrepFile}"
Echo "End" >> "{TempPrepFile}"
Set NeedTool 1
Set TheXCOFF "{1}.x"
Set TextLen `Files -x b -n "{1}" | StreamEdit -d -e '/([0-9]+)¨1b°/ Print ¨1'`
Else
Set TheXCOFF "{1}"
Set TextLen `DumpXCOFF -do h "{TheXCOFF}" | StreamEdit -d -e '/s_nameŶ".(Å)¨1¶"/ Set CurSec ¨1' -e '/s_sizeŶ((Å)¨1¶)/ Print CurSec " " ¨1' | StreamEdit -d -e '/text (Å)¨1/ Print ¨1'`
End
Echo -n "¶t¶¶¶n¶t" >> "{TempCmdFile}"
Quote -n "{TheXCOFF}" >> "{TempCmdFile}"
Set OffsetSoFar `Evaluate {OffsetSoFar} + {TextLen}`
End
Shift
End
If {NeedTool}
Echo "# Compile a C program to create/extract basic XCOFFs"
Echo -n 'If !`Exists '
Quote -n "{0}.tool"
Echo -n "{Streamer}"
Echo '`'
Echo -n "¶tSC "
Echo -n '-o "{TempFolder}LinkPowerROM.o" '
Quote "{0}.c"
Echo -n "¶tILink -d -t MPST -c 'MPS ' -o "
Quote -n "{0}.tool"
Echo ' "{Libraries}Stubs.o" "{CLibraries}StdCLib.o" "{Libraries}MacRuntime.o" "{Libraries}IntEnv.o" "{Libraries}Interface.o" "{TempFolder}LinkPowerROM.o"'
Echo "End"
Echo
End
Echo "# Auto-generate some XCOFFs (padding and labels)"
Catenate "{TempPrepFile}"
Echo
Echo "# Link whole-ROM XCOFF"
Catenate "{TempCmdFile}"
Echo
Echo
Echo "# Extract raw ROM binary"
Quote -n "{0}.tool"
Echo -n " fromx "
Quote -n "{DestFile}.x"
Echo -n " "
Quote "{DestFile}"
Echo
Echo "# Checksum the ConfigInfo structure(s)"
Echo -n 'Set CksumOffsets "`DumpXCOFF -do s '
Quote -n "{DestFile}.x"
Echo ' | StreamEdit -d -e "/C_EXTÅAddrÅ(0x[A-Fa-f0-9]+)¨1ÅConfigInfoChecksum/ Print ¨1"`"'
Quote -n "{0}.tool"
Echo -n " cksum "
Quote -n "{DestFile}"
Echo ' {CksumOffsets}'

216
Linker/LinkPowerROM.c Normal file
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#include <stdio.h>
#include <XCOFF.h>
#include <stdlib.h>
#ifdef macintosh
typedef unsigned long uint32_t;
typedef long int32_t;
typedef unsigned short uint16_t;
typedef short int16_t;
typedef unsigned char uint8_t;
typedef char int8_t;
#endif
uint32_t narrow[8];
uint32_t wide[2];
int slurp(char *path, uint8_t **datap, unsigned long *sizep)
{
FILE *f;
long pos;
uint8_t *bytes;
f = fopen(path, "rb");
if(f == NULL) return 1;
fseek(f, 0, SEEK_END);
pos = ftell(f);
fseek(f, 0, SEEK_SET);
bytes = (uint8_t *)malloc(pos);
if(bytes == NULL) return 1;
fread(bytes, pos, 1, f);
fclose(f);
*datap = bytes;
*sizep = pos;
return 0; /* no error */
}
const uint16_t pretend_header[] = {
0x01df /*f_magic*/,
1 /*f_nscns*/,
0xd611, 0x2977 /*f_timdat*/,
0, 0 /*f_symptr*/,
0, 2 /*f_nsyms*/,
0 /*f_opthdr*/,
0 /*f_flags*/,
/* now for single .text symbol header */
0x2e74, 0x6578, 0x7400, 0x0000 /*s_name = .text*/,
0, 0 /*s_paddr*/,
0, 0 /*s_vaddr*/,
1234, 5678 /*s_size*/,
0, 0x3c /*s_scnptr = len of this header*/,
0, 0 /*s_relptr*/,
0, 0 /*s_lnnoptr*/,
0 /*s_nreloc*/,
0 /*s_nlnno*/,
0, 0x20 /*s_flags = text*/
};
const uint16_t pretend_footer[] = {
0, 0,
0, 0,
0, 0,
1, 0,
0x6b01,
1234, 5678,
0, 0, 0,
0x1100, 0, 0, 0
};
int main(int argc, char **argv)
{
FILE *fp;
uint8_t *buf, *sec, *dest;
unsigned long buflen, seclen, destlen;
unsigned long i;
if(argc < 2)
{
fprintf(stderr, "%s: No command specified -- use tox, fromx or cksum\n", argv[0]);
return 1;
}
if(!strcmp(argv[1], "cksum"))
{
unsigned long offset;
if(argc < 3)
{
fprintf(stderr, "%s: %s: Specify a file!\n", argv[0], argv[1]);
return 1;
}
if(argc < 4)
{
return 0; /* No offset specified -- fail silently */
}
if(slurp(argv[2], &buf, &buflen))
{
fprintf(stderr, "%s: %s: Could not open input\n", argv[0], argv[1]);
return 1;
}
offset = strtoul(argv[3], NULL, 0);
if(offset > buflen - 40) {
fprintf(stderr, "%s: Bad offset for ConfigInfo checksum: 0x%x\n", argv[0], offset);
return 1;
}
memset(buf + offset, 0, 40);
for(i=0; i<buflen; i++)
{
/* eight 4-byte sums, for each of eight byte lanes */
narrow[i & 7] += buf[i];
}
for(i=0; i<buflen; i+=8)
{
/* a single 64-bit sum */
uint32_t oldlow = wide[1];
wide[0] += *(uint32_t *)(buf + i);
wide[1] += *(uint32_t *)(buf + i + 4);
if(wide[1] < oldlow) wide[0]++;
}
fp = fopen(argv[2], "r+b");
if(!fp) {
fprintf(stderr, "%s: Could not open output\n", argv[0]);
return 1;
}
fseek(fp, offset, SEEK_SET);
fwrite(narrow, sizeof narrow, 1, fp);
fwrite(wide, sizeof wide, 1, fp);
fclose(fp);
}
else
{
/* XCOFF personality */
if(argc != 4) {
fprintf(stderr, "Usage: %s (tox | fromx) IN OUT\n", argv[0]);
return 1;
}
if(slurp(argv[2], &buf, &buflen))
{
fprintf(stderr, "%s: %s: Could not open input\n", argv[0], argv[1]);
return 1;
}
if(!strcmp(argv[1], "tox"))
{
sec = buf;
seclen = buflen;
}
else if(!strcmp(argv[1], "fromx"))
{
FileHdrPtr fhp;
SectionHdrEntryPtr shp;
fhp = (FileHdrPtr)buf;
shp = (SectionHdrEntryPtr)(buf + sizeof *fhp + fhp->f_opthdr);
sec = buf + shp->s_scnptr;
seclen = shp->s_size;
}
/* now to create my template XCOFF */
if(!strcmp(argv[1], "tox"))
{
destlen = sizeof pretend_header + seclen + sizeof pretend_footer;
dest = (uint8_t *)malloc(destlen);
if(dest == NULL)
{
fprintf(stderr, "%s: OOM\n", argv[0]);
return 1;
}
memcpy(dest, (const char *)pretend_header, sizeof pretend_header);
memcpy(dest + sizeof pretend_header, sec, seclen);
memcpy(dest + sizeof pretend_header + seclen, (const char *)pretend_footer, sizeof pretend_footer);
*(uint32_t *)(dest + 36) = seclen;
*(uint32_t *)(dest + 8) = sizeof pretend_header + seclen;
*(uint32_t *)(dest + sizeof pretend_header + seclen + 18) = seclen;
}
else if(!strcmp(argv[1], "fromx"))
{
dest = sec;
destlen = seclen;
}
fp = fopen(argv[3], "wb");
if(!fp) {
fprintf(stderr, "%s: Could not open output\n", argv[0]);
return 1;
}
fwrite(dest, 1, destlen, fp);
fclose(fp);
}
return 0;
}

60
MakeFile Normal file
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ResultDir = :BuildResults:
LinkerDir = :Linker:
MainTarget Ä {ResultDir}PowerROM
RomBin = :RomMondo.bin
ExceptionTableBin = {ResultDir}PPCExceptionTable.x
{ExceptionTableBin} Ä PPCExceptionTable.s
PPCAsm -o {Targ} {Deps}
ConfigInfoBin = {ResultDir}ConfigInfo.x
{ConfigInfoBin} Ä ConfigInfo.s
PPCAsm -o {Targ} {Deps}
#### PowerPC NanoKernel ####
NKDir = :NanoKernel:
NKIncDir = :Internal:
NKBin = {ResultDir}NanoKernel.x
NKOpts =
#include "{NKDir}InnerMakeFile"
EmulatorBin = Emulator.x
{ResultDir}PowerROM Ä {RomBin} {ExceptionTableBin} {ConfigInfoBin} {NKBin} {EmulatorBin}
{LinkerDir}LinkPowerROM {Targ} ¶
RomTop: ¶
0x000000 Mac68kRomTop: ¶
{RomBin} ¶
Mac68kRomBtm: ¶
0x300000 ExTblTop: ¶
{ExceptionTableBin} ¶
0x30d000 ConfigInfoChecksum: ¶
{ConfigInfoBin} ¶
0x310000 NKTop: ¶
{NKBin} ¶
0x360000 ¶
{EmulatorBin} ¶
0x400000 RomBtm: ¶
> {ResultDir}LinkerScript ; {ResultDir}LinkerScript

42
NanoKernel/InnerMakeFile Normal file
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# I expect these variables to be set already:
# NKDir, NKIncDir, NKBin
NKFiles = ¶
{NKDir}NKInit.s ¶
{NKDir}NKReplacementInit.s ¶
{NKDir}NKBuiltinInit.s ¶
{NKDir}NKProcFlagsTbl.s ¶
{NKDir}NKProcInfoTbl.s ¶
{NKDir}NKInterrupts.s ¶
{NKDir}NKPaging.s ¶
{NKDir}NKTranslation.s ¶
{NKDir}NKVMCalls.s ¶
{NKDir}NKPowerCalls.s ¶
{NKDir}NKRTASCalls.s ¶
{NKDir}NKCacheCalls.s ¶
{NKDir}NKMPCalls.s ¶
{NKDir}NKSync.s ¶
{NKDir}NKTasks.s ¶
{NKDir}NKAddressSpaceMPCalls.s ¶
{NKDir}NKPoolAllocator.s ¶
{NKDir}NKTimers.s ¶
{NKDir}NKScheduler.s ¶
{NKDir}NKIndex.s ¶
{NKDir}NKPrimaryIntHandlers.s ¶
{NKDir}NKConsoleLog.s ¶
{NKDir}NKSleep.s ¶
{NKDir}NKThud.s ¶
{NKDir}NKScreenConsole.s ¶
{NKDir}NKAdditions.s ¶
NKIncludes = ¶
{NKDir}NKMacros.s ¶
{NKDir}NKEquates.s ¶
{NKIncDir}InfoRecords.a ¶
{NKIncDir}EmulatorPublic.a ¶
{NKIncDir}NKPublic.a ¶
{NKIncDir}NKOpaque.a ¶
# We get warning 3202 from ALIGN directives -- kill it
{NKBin} Ä {NKDir}NanoKernel.s {NKFiles} {NKIncludes}
PPCAsm -o {Targ} -w 3202 -i {NKIncDir} -i "{AIncludes}" {NKDir}NanoKernel.s

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# Lets you just run Make in this directory,
# while ignoring the rest of the build system
NKDir = :
NKIncDir = {NKDir}:Internal:
NKBin = {NKDir}NanoKernel.s.x
NKOpts =
#include "{NKDir}InnerMakeFile"

61
NanoKernel/NKAdditions.s Normal file
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;_______________________________________________________________________
; My additions to the NanoKernel, to go at the end of the code image
;_______________________________________________________________________
if &TYPE('NKDebugShim') != 'UNDEFINED'
DeclareMPCall 200, NKDebug
NKDebug
; Lifted from NKxprintf:
; Put the physical address of the r3 arg in r8
rlwinm. r9, r11, 0, MSR_DRbit, MSR_DRbit ; IntSyscall sets this
mr r8, r3
beq- @already_physical
li r9, 0
bl V2P ; takes page EA in r8, r9=0, returns page PA in r17
beq- @fail
rlwimi r8, r17, 0, 0, 19
@already_physical
; Copy the command into the KDP buffer reserved for this purpose:
; r8 = src
; r29 = dest
; r30 = ctr
; r31 = val
mfsprg r1, 0
lwz r1, EWA.PA_KDP(r1)
li r30, 0
addi r29, r1, -0x960
@cmdloop
lbzx r31, r8, r30
stbx r31, r29, r30
addi r30, r30, 1
cmpwi r31, 0
bne @cmdloop
lwz r31, -0x404(r1)
stw r8, -0x404(r1)
bl panic
lwz r8, -0x404(r1)
li r0, 0
stw r0, 0(r8)
stw r31, -0x404(r1)
b ReturnZeroFromMPCall
@fail
b ReturnMPCallOOM
endif

4454
NanoKernel/NKAddressSpaceMPCalls.s Normal file
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NanoKernel/NKBuiltinInit.s Normal file
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NanoKernel/NKCacheCalls.s Normal file
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kcCacheDispatch ; OUTSIDE REFERER
stw r21, 0x01ac(r6)
stw r22, 0x01b4(r6)
stw r23, 0x01bc(r6)
clrlwi r8, r3, 0x10
cmplwi r8, 0x02
bgt- kcCacheDispatch_0x4c
lwz r8, 0x0f68(r1)
andi. r8, r8, 0x01
beq- kcCacheDispatch_0x178
rlwinm. r9, r3, 0, 2, 2
bnel- kcCacheDispatch_0x1e4
srwi r8, r3, 30
cmpwi r8, 0x03
beq- kcCacheDispatch_0xd8
clrlwi r8, r3, 0x10
cmplwi r8, 0x01
beq- kcCacheDispatch_0x58
cmplwi r8, 0x02
beq- kcCacheDispatch_0xb8
kcCacheDispatch_0x4c
lis r3, -0x01
ori r3, r3, 0xfffe
b kcCacheDispatch_0x1c4
kcCacheDispatch_0x58
rlwinm. r9, r3, 0, 1, 1
bne- kcCacheDispatch_0x74
rlwinm. r9, r3, 0, 0, 0
bne- kcCacheDispatch_0x98
rlwinm. r9, r3, 0, 3, 3
bl kcCacheDispatch_0x258
b kcCacheDispatch_0x1c4
kcCacheDispatch_0x74
bl kcCacheDispatch_0x258
rlwinm r22, r3, 0, 4, 5
srwi r22, r22, 12
mfspr r21, hid0
andc r21, r21, r22
sync
mtspr hid0, r21
li r3, 0x00
b kcCacheDispatch_0x1c4
kcCacheDispatch_0x98
rlwinm r22, r3, 0, 4, 5
srwi r22, r22, 12
mfspr r21, hid0
or r21, r21, r22
sync
mtspr hid0, r21
li r3, 0x00
b kcCacheDispatch_0x1c4
kcCacheDispatch_0xb8
rlwinm. r9, r3, 0, 1, 1
bne- kcCacheDispatch_0x180
rlwinm. r9, r3, 0, 0, 0
bne- kcCacheDispatch_0xe8
rlwinm. r9, r3, 0, 3, 3
bne- kcCacheDispatch_0xe4
rlwinm. r9, r3, 0, 2, 2
bne- kcCacheDispatch_0x1c4
kcCacheDispatch_0xd8
lis r3, -0x01
ori r3, r3, 0xfffc
b kcCacheDispatch_0x1c4
kcCacheDispatch_0xe4
bl kcCacheDispatch_0x180
kcCacheDispatch_0xe8
mfspr r21, l2cr
sync
andis. r21, r21, 0x8000
bne- kcCacheDispatch_0x1c4
lwz r8, 0x0f54(r1)
and. r8, r8, r8
beq- kcCacheDispatch_0x178
mfspr r21, hid0
rlwinm r8, r21, 0, 12, 10
mtspr hid0, r8
sync
addi r8, r1, -0x4d0
lwz r8, 0x0050(r8)
and. r8, r8, r8
beq- kcCacheDispatch_0x1c4
sync
lis r9, 0x20
or r8, r8, r9
mtspr l2cr, r8
sync
kcCacheDispatch_0x138
mfspr r8, l2cr
sync
andi. r9, r8, 0x01
bne+ kcCacheDispatch_0x138
lis r9, 0x20
andc r8, r8, r9
mtspr l2cr, r8
sync
lis r9, -0x8000
or r8, r8, r9
mtspr l2cr, r8
sync
mtspr hid0, r21
sync
li r3, 0x00
b kcCacheDispatch_0x1c4
kcCacheDispatch_0x178
li r3, -0x02
b kcCacheDispatch_0x1c4
kcCacheDispatch_0x180
mfspr r22, l2cr
sync
andis. r22, r22, 0x8000
beq- kcCacheDispatch_0x1c4
bl kcCacheDispatch_0x258
mfspr r22, l2cr
sync
clrlwi r22, r22, 0x01
mtspr l2cr, r22
sync
addi r8, r1, -0x4d0
stw r22, 0x0050(r8)
sync
rlwinm r22, r22, 0, 7, 3
oris r22, r22, 0x10
mtspr l2cr, r22
sync
kcCacheDispatch_0x1c4
ori r23, r23, 0xffff
oris r3, r3, 0xffff
and r3, r3, r23
kcCacheDispatch_0x1d0
lwz r21, 0x01ac(r6)
lwz r22, 0x01b4(r6)
lwz r23, 0x01bc(r6)
sync
b skeleton_key
kcCacheDispatch_0x1e4
clrlwi r8, r3, 0x10
cmplwi r8, 0x01
beq- kcCacheDispatch_0x204
cmplwi r8, 0x02
beq- kcCacheDispatch_0x218
lis r3, -0x01
ori r3, r3, 0xfffb
b kcCacheDispatch_0x1d0
kcCacheDispatch_0x204
mfspr r21, hid0
rlwinm. r21, r21, 12, 4, 5
beq- kcCacheDispatch_0x24c
oris r23, r21, 0x8000
blr
kcCacheDispatch_0x218
lwz r8, 0x0f54(r1)
and. r8, r8, r8
beq+ kcCacheDispatch_0x178
mfspr r21, hid0
rlwinm r21, r21, 12, 4, 5
mfspr r22, l2cr
rlwinm r22, r22, 5, 4, 4
andc r21, r21, r22
mfspr r22, l2cr
andis. r22, r22, 0x8000
beq- kcCacheDispatch_0x24c
or r23, r21, r22
blr
kcCacheDispatch_0x24c
lis r23, 0x4000
ori r23, r23, 0x00
blr
kcCacheDispatch_0x258 ; OUTSIDE REFERER
mfctr r8
stw r25, 0x01cc(r6)
stw r24, 0x01c4(r6)
stw r8, 0x00f4(r6)
lhz r25, 0x0f44(r1)
and. r25, r25, r25
cntlzw r8, r25
beq- kcCacheDispatch_0x338
subfic r9, r8, 0x1f
lwz r8, 0x0f34(r1)
and. r8, r8, r8
beq- kcCacheDispatch_0x338
lwz r24, 0x0f68(r1)
mtcr r24
bso- cr6, kcCacheDispatch_0x350
bne- cr7, kcCacheDispatch_0x2a4
slwi r24, r8, 1
add r8, r8, r24
srwi r8, r8, 1
kcCacheDispatch_0x2a4
srw r8, r8, r9
mtctr r8
lwz r8, 0x0630(r1)
lwz r9, 0x0028(r8)
add r8, r8, r9
kcCacheDispatch_0x2b8
lwzux r9, r8, r25
bdnz+ kcCacheDispatch_0x2b8
lwz r24, 0x0f68(r1)
andi. r24, r24, 0x01
beq- kcCacheDispatch_0x338
mfspr r24, l2cr
andis. r24, r24, 0x8000
beq- kcCacheDispatch_0x338
lhz r25, 0x0f60(r1)
and. r25, r25, r25
cntlzw r8, r25
beq- kcCacheDispatch_0x338
subfic r9, r8, 0x1f
lwz r8, 0x0f54(r1)
and. r8, r8, r8
beq- kcCacheDispatch_0x338
srw r8, r8, r9
mtctr r8
mfspr r24, l2cr
oris r24, r24, 0x40
mtspr l2cr, r24
isync
lwz r8, 0x0630(r1)
lwz r9, 0x0028(r8)
add r8, r8, r9
addis r8, r8, 0x19
neg r25, r25
kcCacheDispatch_0x324
lwzux r9, r8, r25
bdnz+ kcCacheDispatch_0x324
rlwinm r24, r24, 0, 10, 8
mtspr l2cr, r24
isync
kcCacheDispatch_0x338
lwz r8, 0x00f4(r6)
lwz r25, 0x01cc(r6)
lwz r24, 0x01c4(r6)
sync
mtctr r8
blr
kcCacheDispatch_0x350
dssall
sync
mfspr r8, 1014
oris r8, r8, 0x80
mtspr 1014, r8
sync
kcCacheDispatch_0x368
mfspr r8, 1014
sync
andis. r8, r8, 0x80
bne+ kcCacheDispatch_0x368
mfspr r8, l2cr
ori r8, r8, 0x800
mtspr l2cr, r8
sync
kcCacheDispatch_0x388
mfspr r8, l2cr
sync
andi. r8, r8, 0x800
bne+ kcCacheDispatch_0x388
b kcCacheDispatch_0x338
kcCacheDispatch_0x39c ; OUTSIDE REFERER
lwz r8, 0x0f68(r1)
mtcr r8
bnslr- cr6
dssall
sync
mfspr r8, 1014
oris r8, r8, 0x80
mtspr 1014, r8
sync
kcCacheDispatch_0x3c0
mfspr r8, 1014
sync
andis. r8, r8, 0x80
bne+ kcCacheDispatch_0x3c0
blr

802
NanoKernel/NKConsoleLog.s Normal file
View File

@ -0,0 +1,802 @@
; prints
; _log null-terminated string with a few special escapes.
; Not done figuring this out, with the serial and stuff.
; Xrefs:
; replace_old_kernel
; new_world
; setup
; undo_failed_kernel_replacement
; AcquireLock
; spinlock_what
; major_0x02ccc
; IntMachineCheckMemRetry
; IntMachineCheck
; major_0x03ab0
; IntThermalEvent
; kcResetSystem
; non_skeleton_reset_trap
; PagingFunc1
; KCRegisterCpuPlugin
; KCStartCPU
; NKxprintf
; MPCall_108
; NKSetClockStep
; NKSetClockDriftCorrection
; convert_pmdts_to_areas
; NKCreateAddressSpaceSub
; createarea
; major_0x10320
; MPCall_95
; ExtendPool
; major_0x12b94
; InitTMRQs
; StartTimeslicing
; InitRDYQs
; major_0x14bcc
; panic
; major_0x18040
; print_xpt_info
; print_sprgs
; print_sprs
; print_segment_registers
; print_gprs
; print_memory
; print_memory_logical
prints ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, -0x0004(r1)
lwz r28, -0x0900(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq- cr7, prints_skip_serial
crmove 30, 2
beq- PrintS_skip_serial
mfmsr r31
bl serial_io
bl serial_flush
prints_skip_serial
addi r8, r8, -0x01
prints_next_char
bl serial_busywait
lbzu r29, 0x0001(r8)
cmpwi r29, 0x00
beq- print_common
cmpwi r29, 10
beq- PrintS_newline
cmpwi r29, 13
beq- PrintS_newline
cmpwi r29, '\\'
beq- PrintS_escape_code
cmpwi r29, '^'
bne- PrintS_normal_char
prints_escape_code
lbzu r29, 0x0001(r8)
cmpwi r29, 'n'
beq- PrintS_newline
cmpwi r29, 'r'
beq- PrintS_newline
cmpwi r29, 'b'
bne- PrintS_literal_backslash_or_caret
li r29, 0x07
b PrintS_normal_char
prints_literal_backslash_or_caret
lbzu r29, -0x0001(r8)
addi r8, r8, 0x01
prints_normal_char
mr r24, r29
; r1 = kdp
bl ScreenConsole_putchar
beq- cr7, prints_0xe4
ori r30, r31, 0x10
mtmsr r30
isync
stb r24, 0x0006(r28)
eieio
mtmsr r31
isync
prints_0xe4
b PrintS_next_char
prints_newline
li r29, 0x0d
; r1 = kdp
bl ScreenConsole_putchar
li r29, 0x0a
; r1 = kdp
bl ScreenConsole_putchar
; r1 = kdp
bl ScreenConsole_redraw
beq- cr7, prints_0x13c
ori r30, r31, 0x10
mtmsr r30
isync
li r29, 0x0d
stb r29, 0x0006(r28)
eieio
prints_0x118
lbz r29, 0x0002(r28)
eieio
andi. r29, r29, 0x04
beq+ PrintS_0x118
li r29, 0x0a
stb r29, 0x0006(r28)
eieio
mtmsr r31
isync
prints_0x13c
b PrintS_next_char
; print_common
; Xrefs:
; PrintS
; Printd
; print_digity_common
; getchar
; Printc
print_common ; OUTSIDE REFERER
beq- cr7, print_common_0x8c
mtmsr r31
isync
lwz r29, -0x0438(r1)
srwi r29, r29, 8
mfspr r30, dec
subf r29, r29, r30
ori r30, r31, 0x10
mtmsr r30
isync
print_common_0x28
mfspr r30, dec
subf. r30, r29, r30
ble- print_common_0x50
li r30, 0x01
stb r30, 0x0002(r28)
eieio
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x01
beq+ print_common_0x28
print_common_0x50
sync
mtmsr r31
isync
mfspr r30, pvr
rlwinm. r30, r30, 0, 0, 14
li r31, 0x00
beq- print_common_0x78
mtspr dbat3u, r31
mtspr dbat3l, r31
b print_common_0x80
print_common_0x78
mtspr ibat3l, r31
mtspr ibat3u, r31
print_common_0x80
isync
mtspr srr0, r26
mtspr srr1, r27
print_common_0x8c
sync
lwz r30, -0x0af0(r1)
cmpwi cr1, r30, 0x00
li r30, 0x00
bne+ cr1, print_common_0xa8
mflr r30
bl panic
print_common_0xa8
stw r30, -0x0af0(r1)
; print_return
; Restores registers from EWA and returns.
; Xrefs:
; print_common
; getchar
print_return ; OUTSIDE REFERER
mfsprg r1, 0
lwz r24, -0x0110(r1)
lwz r25, -0x010c(r1)
mtlr r24
mtcr r25
lmw r24, -0x0108(r1)
lwz r1, -0x0004(r1)
blr
; printd
; _log decimal
; Xrefs:
; setup
; NKPrintDecimal
; MPCall_108
; NKSetClockStep
; NKSetClockDriftCorrection
; ExtendPool
; major_0x12b94
printd ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, -0x0004(r1)
lwz r28, -0x0900(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq- cr7, printd_0x58
crmove 30, 2
beq- Printd_0x58
bl serial_io
bl serial_flush
printd_0x58
cmpwi r8, 0x00
li r25, 0x2d
blt- Printd_0x9c
printd_0x64
mr. r24, r8
li r25, 0x30
beq- Printd_0x9c
lis r24, 0x3b9a
ori r24, r24, 0xca00
printd_0x78
divw. r25, r8, r24
bne- Printd_0x8c
li r25, 0x0a
divw r24, r24, r25
b Printd_0x78
printd_0x8c
divw r29, r8, r24
addi r25, r29, 0x30
mullw r29, r29, r24
subf r8, r29, r8
printd_0x9c
bl serial_busywait
mr r29, r25
; r1 = kdp
bl ScreenConsole_putchar
beq- cr7, printd_0xc8
ori r30, r31, 0x10
mtmsr r30
isync
stb r25, 0x0006(r28)
eieio
mtmsr r31
isync
printd_0xc8
cmpwi r8, 0x00
bge- Printd_0xd8
neg r8, r8
b Printd_0x64
printd_0xd8
li r25, 0x0a
divw. r24, r24, r25
bne+ Printd_0x8c
li r29, 0x20
; r1 = kdp
bl ScreenConsole_putchar
beq- cr7, printd_0x120
ori r30, r31, 0x10
mtmsr r30
isync
printd_0xfc
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq+ Printd_0xfc
li r29, 0x20
stb r29, 0x0006(r28)
eieio
mtmsr r31
isync
printd_0x120
b print_common
; printw
; _log word (hex) then a space
; Xrefs:
; replace_old_kernel
; setup
; AcquireLock
; spinlock_what
; major_0x02ccc
; IntMachineCheckMemRetry
; IntMachineCheck
; major_0x03ab0
; kcResetSystem
; PagingFunc1
; NKPrintHex
; NKCreateAddressSpaceSub
; createarea
; ExtendPool
; major_0x12b94
; InitRDYQs
; major_0x14bcc
; panic
; print_xpt_info
; print_sprgs
; print_sprs
; print_segment_registers
; print_gprs
; print_memory
; print_memory_logical
printw ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x08
crset cr6_eq
b print_digity_common
; printh
; _log halfword (hex) then a space
; Xrefs:
; replace_old_kernel
; new_world
; NKPrintHex
; major_0x14bcc
; panic
printh ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x04
rotlwi r8, r8, 0x10
crset cr6_eq
b print_digity_common
; printb
; _log byte (hex) then a space
; Xrefs:
; setup
; NKPrintHex
printb ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x02
rotlwi r8, r8, 0x18
crset cr6_eq
b print_digity_common
; print_unknown
; Xrefs:
; print_memory_logical
print_unknown ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
li r24, 0x02
rotlwi r8, r8, 0x18
crclr cr6_eq
b print_digity_common
; print_digity_common
; Xrefs:
; Printw
; Printh
; Printb
; print_unknown
print_digity_common ; OUTSIDE REFERER
lwz r1, -0x0004(r1)
lwz r28, -0x0900(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq- cr7, print_digity_common_0x40
crmove 30, 2
beq- print_digity_common_0x40
bl serial_io
bl serial_flush
print_digity_common_0x40
bl serial_busywait
li r25, 0x30
rlwimi r25, r8, 4, 28, 31
rotlwi r8, r8, 0x04
cmpwi r25, 0x39
ble- print_digity_common_0x5c
addi r25, r25, 0x27
print_digity_common_0x5c
mr r29, r25
; r1 = kdp
bl ScreenConsole_putchar
beq- cr7, print_digity_common_0x84
ori r30, r31, 0x10
mtmsr r30
isync
stb r25, 0x0006(r28)
eieio
mtmsr r31
isync
print_digity_common_0x84
addi r24, r24, -0x01
mr. r24, r24
bne+ print_digity_common_0x40
bne- cr6, print_digity_common_0xd0
li r29, 0x20
; r1 = kdp
bl ScreenConsole_putchar
beq- cr7, print_digity_common_0xd0
ori r30, r31, 0x10
mtmsr r30
isync
print_digity_common_0xac
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq+ print_digity_common_0xac
li r29, 0x20
stb r29, 0x0006(r28)
eieio
mtmsr r31
isync
print_digity_common_0xd0
b print_common
; getchar
; Xrefs:
; panic
; print_memory
; print_memory_logical
getchar ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, EWA.PA_KDP(r1)
lwz r28, -0x0900(r1)
cmpwi cr7, r28, 0x00
li r8, -0x01
beq+ cr7, print_return
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
bl serial_io
ori r30, r31, 0x10
mtmsr r30
isync
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x01
beq+ print_common
lbz r8, 0x0006(r28)
b print_common
; printc
; _log char
; Xrefs:
; spinlock_what
; major_0x12b94
; panic
; print_memory
; print_memory_logical
printc ; OUTSIDE REFERER
mfsprg r1, 0
stmw r24, -0x0108(r1)
mflr r24
mfcr r25
stw r24, -0x0110(r1)
stw r25, -0x010c(r1)
lwz r1, -0x0004(r1)
lwz r28, -0x0900(r1)
lwz r29, 0x0edc(r1)
_Lock PSA.DbugLock, scratch1=r30, scratch2=r31
cmpwi cr7, r28, 0x00
andi. r29, r29, 0x02
beq- cr7, printc_0x58
crmove 30, 2
beq- Printc_0x58
bl serial_io
bl serial_flush
printc_0x58
mr r29, r8
; r1 = kdp
bl ScreenConsole_putchar
beq- cr7, printc_0x90
ori r30, r31, 0x10
mtmsr r30
isync
printc_0x70
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq+ Printc_0x70
stb r8, 0x0006(r28)
eieio
mtmsr r31
isync
printc_0x90
b print_common
; serial_flush
; This and the following func are a bit speculative, but
; whatever.
; Whoa. Turns on data but not code paging. Crikey.
; Xrefs:
; PrintS
; Printd
; print_digity_common
; Printc
serial_flush ; OUTSIDE REFERER
ori r30, r31, MSR_DR
mtmsr r30
isync
lbz r29, 0x0002(r28)
li r29, 0x09
stb r29, 0x0002(r28)
eieio
li r29, 0x80
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x04
stb r29, 0x0002(r28)
eieio
li r29, 0x48
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x03
stb r29, 0x0002(r28)
eieio
li r29, 0xc0
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x05
stb r29, 0x0002(r28)
eieio
li r29, 0x60
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x09
stb r29, 0x0002(r28)
eieio
li r29, 0x00
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x0a
stb r29, 0x0002(r28)
eieio
li r29, 0x00
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x0b
stb r29, 0x0002(r28)
eieio
li r29, 0x50
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x0c
stb r29, 0x0002(r28)
eieio
li r29, 0x00
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x0d
stb r29, 0x0002(r28)
eieio
li r29, 0x00
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x0e
stb r29, 0x0002(r28)
eieio
li r29, 0x01
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x03
stb r29, 0x0002(r28)
eieio
li r29, 0xc1
stb r29, 0x0002(r28)
eieio
lbz r29, 0x0002(r28)
li r29, 0x05
stb r29, 0x0002(r28)
eieio
li r29, 0xea
stb r29, 0x0002(r28)
eieio
mtmsr r31
isync
blr
; serial_io
; See disclaimer above.
; Xrefs:
; PrintS
; Printd
; print_digity_common
; getchar
; Printc
serial_io ; OUTSIDE REFERER
mfspr r26, srr0
mfspr r27, srr1
isync
mfspr r30, pvr
rlwinm. r30, r30, 0, 0, 14
rlwinm r29, r28, 0, 0, 14
beq- serial_io_0x38
li r30, 0x03
or r30, r30, r29
li r31, 0x3a
or r31, r31, r29
mtspr dbat3l, r31
mtspr dbat3u, r30
b serial_io_0x50
serial_io_0x38
li r30, 0x32
or r30, r30, r29
li r31, 0x40
or r31, r31, r29
mtspr ibat3u, r30
mtspr ibat3l, r31
serial_io_0x50
isync
mfmsr r31
blr
; serial_busywait
; See disclaimer above.
; Xrefs:
; PrintS
; Printd
; print_digity_common
serial_busywait ; OUTSIDE
beqlr- cr7
ori r30, r31, 0x10
mtmsr r30
isync
serial_busywait_0x10
lbz r30, 0x0002(r28)
eieio
andi. r30, r30, 0x04
beq+ serial_busywait_0x10
mtmsr r31
isync
blr

50
NanoKernel/NKEquates.s Normal file
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@ -0,0 +1,50 @@
;_______________________________________________________________________
; Equates for the whole NanoKernel
;_______________________________________________________________________
kNanoKernelVersion equ $0228
; PowerPC Machine Status Register (MSR) bits
; (borrowing the _bitEqu macro from NKInfoRecordsPriv.s)
_bitEqu MSR_POW, 13
_bitEqu MSR_ILE, 15
_bitEqu MSR_EE, 16
_bitEqu MSR_PR, 17
_bitEqu MSR_FP, 18
_bitEqu MSR_ME, 19
_bitEqu MSR_FE0, 20
_bitEqu MSR_SE, 21
_bitEqu MSR_BE, 22
_bitEqu MSR_FE1, 23
_bitEqu MSR_IP, 25
_bitEqu MSR_IR, 26
_bitEqu MSR_DR, 27
_bitEqu MSR_RI, 30
_bitEqu MSR_LE, 31
; Special Purpose Registers (SPRs) not understood by MPW
l2cr equ 1017
; Alignment for NanoKernel interrupt routines (mostly Interrupts.s)
kIntAlign equ 5
; Junk
; IRP is 10 pages below KDP (measured start to start)
IRPOffset equ (-10) * 4096
kKDPfromIRP equ 10 * 4096
noErr equ 0

298
NanoKernel/NKIndex.s Normal file
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@ -0,0 +1,298 @@
;_______________________________________________________________________
; NanoKernel Opaque ID Index
;
; Creates opaque structure IDs and stores them in the Pool. An opaque
; ID maps back to the (type, pointer) pair passed to MakeID.
;
; This abstraction is very important to the Multiprocessing Services.
;
; Rene on comp.sys.mac.programmer.help, 26 Oct 01:
;
; Total opaque IDs - The number of IDs currently in use. All MP
; objects: address spaces, areas, processors, memory coherence groups,
; queues, semaphores, critical regions, event groups, timers,
; notifications, etc. are assigned an ID when created, and they are
; accessed by way of this ID. The kernel presently handles 65,000
; simultaneous IDs with a bit pattern reuse probability of 1 in 4
; billion.
;_______________________________________________________________________
Local_Panic set *
b panic
; ARG KDP *r1
InitIDIndex
mflr r23
li r8, Index.Size
bl PoolAlloc
mr. r22, r8
stw r8, PSA.IndexPtr(r1)
beq+ Local_Panic
li r9, 0
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
sth r9, Index.HalfOne(r22)
sth r9, Index.HalfTwo(r22)
lisori r9, Index.kSignature
stw r9, Index.Signature(r22)
; Then what the hell is this?
li r8, 0xfd8
bl PoolAlloc
cmpwi r8, 0
stw r8, Index.IDsPtr(r22)
beq+ Local_Panic
mtlr r23
li r9, 0x00
sth r9, 0x0000(r8)
li r9, 0x1fa
sth r9, 0x0002(r8)
lisori r9, 'IDs '
stw r9, 0x0004(r8)
blr
; ARG void *r8, IDClass r9
; RET ID r8
MakeID
lwz r18, -0x0a98(r1)
lhz r19, 0x0000(r18)
mr r21, r19
@_c
lwz r18, -0x0a98(r1)
rlwinm r20, r19, 25, 23, 29
addi r20, r20, 0x08
clrlwi. r19, r19, 0x17
lwzx r18, r18, r20
slwi r22, r19, 3
addi r20, r18, 0x08
cmpwi r18, 0x00
add r22, r22, r20
bne- @_48
li r19, 0x00
b @_c
@_3c
add r20, r20, r19
cmpw r20, r21
beq- @_70
@_48
lbz r23, 0x0000(r22)
cmpwi r23, 0x00
beq- @_f0
addi r19, r19, 0x01
cmpwi cr1, r19, 0x1fa
addi r22, r22, 0x08
lhz r20, 0x0000(r18)
blt+ cr1, @_3c
addi r19, r20, 0x200
b @_c
@_70
lwz r18, -0x0a98(r1)
mr r21, r8
lhz r19, 0x0002(r18)
mr r22, r9
addi r19, r19, 0x200
rlwinm. r20, r19, 25, 23, 29
li r8, 0x00
beqlr-
mflr r23
li r8, 0xfd8
; r1 = kdp
; r8 = size
bl PoolAlloc
; r8 = ptr
mr. r18, r8
mtlr r23
li r8, 0x00
beqlr-
lwz r17, -0x0a98(r1)
lhz r19, 0x0002(r17)
addi r19, r19, 0x200
rlwinm r20, r19, 25, 23, 29
addi r20, r20, 0x08
sth r19, 0x0002(r17)
stwx r18, r20, r17
sth r19, 0x0000(r18)
li r9, 0x1fa
sth r9, 0x0002(r18)
lis r9, 0x4944
ori r9, r9, 0x7320
stw r9, 0x0004(r18)
li r19, 0x00
mr r8, r21
mr r9, r22
addi r22, r18, 0x08
@_f0
stw r8, 0x0004(r22)
stb r9, 0x0000(r22)
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
addi r9, r9, 0x01
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
lhz r20, 0x0000(r18)
lhz r8, 0x0002(r22)
lwz r21, -0x0a98(r1)
add r19, r19, r20
addi r8, r8, 0x01
lhz r20, 0x0002(r18)
sth r8, 0x0002(r22)
addi r20, r20, -0x01
rlwimi. r8, r19, 16, 0, 15
sth r20, 0x0002(r18)
sth r19, 0x0000(r21)
bnelr+
lhz r8, 0x0002(r22)
addi r8, r8, 0x01
sth r8, 0x0002(r22)
rlwimi r8, r19, 16, 0, 15
blr
; ARG ID r8
align 5
DeleteID
rlwinm r20, r8, 9, 23, 29
lwz r18, -0x0a98(r1)
addi r20, r20, 0x08
rlwinm. r19, r8, 16, 23, 31
lwzx r18, r18, r20
cmplwi cr1, r19, 0x1fa
cmpwi r18, 0x00
addi r20, r18, 0x08
slwi r22, r19, 3
add r22, r22, r20
clrlwi r20, r8, 0x10
li r8, 0x00
bgelr- cr1
beqlr-
lbz r19, 0x0000(r22)
lhz r23, 0x0002(r22)
cmpwi r19, 0x00
cmpw cr1, r23, r20
beqlr-
bnelr- cr1
lwz r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
addi r9, r9, -0x01
stw r9, KDP.NanoKernelInfo + NKNanoKernelInfo.IDCtr(r1)
lhz r20, 0x0002(r18)
stb r8, 0x0000(r22)
addi r20, r20, 0x01
li r8, 0x01
sth r20, 0x0002(r18)
blr
; ARG ID r8
; RET Ptr r8, IDClass r9
align 5
LookupID
rlwinm r20, r8, 9, 23, 29
lwz r18, -0x0a98(r1)
addi r20, r20, 0x08
rlwinm. r19, r8, 16, 23, 31
lwzx r18, r18, r20
cmplwi cr1, r19, 0x1fa
cmpwi r18, 0x00
addi r20, r18, 0x08
slwi r22, r19, 3
add r22, r22, r20
clrlwi r20, r8, 0x10
li r8, 0x00
li r9, 0x00
bgelr- cr1
beqlr-
lbz r19, 0x0000(r22)
lhz r23, 0x0002(r22)
cmpwi r19, 0x00
cmpw cr1, r23, r20
beqlr-
bnelr- cr1
lwz r8, 0x0004(r22)
mr r9, r19
blr
; ARG ID r8, IDClass r9
; RET ID r8
align 5
GetNextIDOfClass
rlwinm r20, r8, 9, 23, 29
lwz r18, -0x0a98(r1)
addi r20, r20, 0x08
rlwinm. r19, r8, 16, 23, 31
lwzx r18, r18, r20
cmplwi cr1, r19, 0x1fa
cmpwi r18, 0x00
cmpwi cr2, r8, 0x00
addi r20, r18, 0x08
slwi r22, r19, 3
li r8, 0x00
bgelr- cr1
beqlr-
add r22, r22, r20
bne- cr2, @_48
@_3c
lbz r23, 0x0000(r22)
cmpwi r23, 0x00
bne- @_8c
@_48
addi r19, r19, 0x01
cmpwi r19, 0x1fa
addi r22, r22, 0x08
blt+ @_3c
lhz r20, 0x0000(r18)
addi r20, r20, 0x200
rlwinm. r20, r20, 25, 23, 29
lwz r18, -0x0a98(r1)
beqlr-
addi r20, r20, 0x08
li r19, 0x00
lwzx r18, r18, r20
cmpwi r18, 0x00
addi r22, r18, 0x08
bne+ @_3c
li r8, 0x00
blr
@_8c
cmpwi r9, 0x00
cmpw cr1, r9, r23
beq- @_9c
bne+ cr1, @_48
@_9c
lhz r20, 0x0000(r18)
lhz r8, 0x0002(r22)
add r19, r19, r20
rlwimi r8, r19, 16, 0, 15
blr

2134
NanoKernel/NKInit.s Normal file
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File diff suppressed because it is too large Load Diff

2851
NanoKernel/NKInterrupts.s Normal file
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File diff suppressed because it is too large Load Diff

2672
NanoKernel/NKMPCalls.s Normal file
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File diff suppressed because it is too large Load Diff

192
NanoKernel/NKMacros.s Normal file
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@ -0,0 +1,192 @@
MACRO
_log &s
BL @paststring
STRING AsIs
DC.B &s, 0, 0
ALIGN 2
@paststring
mflr r8
BL PrintS
ENDM
; Cool macro for one-line debug calls
MACRO
_wlog &s1, &reg, &s2, &scratch==r8
if &TYPE('ExtraNKLogging') != 'UNDEFINED'
mr &scratch, r8
_log &s1
_log '[ '
mr r8, &reg
bl PrintW
_log ']'
_log &s2
mr r8, &scratch
endif
ENDM
MACRO
_wlogh &s1, &reg, &s2, &scratch==r8
if &TYPE('ExtraNKLogging') != 'UNDEFINED'
mr &scratch, r8
_log &s1
_log '[ '
mr r8, &reg
bl PrintH
_log ']'
_log &s2
mr r8, &scratch
endif
ENDM
MACRO
_clog &s
if &TYPE('ExtraNKLogging') != 'UNDEFINED'
_log &s
endif
ENDM
MACRO
LHHI &reg, &val
lis (&reg), ((&val) >> 16) & 0xffff
ENDM
MACRO
LLHI &reg, &val
ori (&reg), (&reg), (&val) & 0xffff
ENDM
MACRO
lisori &reg, &val
lis &reg, ((&val) >> 16) & 0xffff
ori &reg, &reg, (&val) & 0xffff
ENDM
MACRO
llabel &reg, &val
lisori &reg, &val - NKTop
ENDM
MACRO
StartLoadingWord &reg, &val
LHHI (&reg), (&val)
HalfLoadedWord set (&val)
HalfLoadedReg set (&reg)
ENDM
MACRO
FinishLoadingWord
LLHI HalfLoadedReg, HalfLoadedWord
ENDM
MACRO
InitList &ptr, &sig, &scratch==r8
StartLoadingWord &scratch, &sig
stw &ptr, LLL.Next(&ptr)
FinishLoadingWord
stw &ptr, LLL.Prev(&ptr)
stw &scratch, LLL.Signature(&ptr)
ENDM
; Next is 8, Prev is C
MACRO
InsertAsPrev &el, &next, &scratch==r18
stw &next, LLL.Next(&el)
lwz &scratch, LLL.Prev(&next)
stw &scratch, LLL.Prev(&el)
stw &el, LLL.Next(&scratch)
stw &el, LLL.Prev(&next)
ENDM
MACRO
InsertAsNext &el, &prev, &scratch==r18
stw &prev, LLL.Prev(&el)
lwz &scratch, LLL.Next(&prev)
stw &scratch, LLL.Next(&el)
stw &el, LLL.Prev(&scratch)
stw &el, LLL.Next(&prev)
ENDM
MACRO
RemoveFromList &el, &scratch1==r17, &scratch2==r18
; Point neighbours of el up and down at each other
lwz &scratch1, 8(&el)
lwz &scratch2, 12(&el)
stw &scratch1, 8(&scratch2)
stw &scratch2, 12(&scratch1)
; Zero out the pointers in el
li &scratch1, 0
stw &scratch1, 8(&el)
stw &scratch1, 12(&el)
ENDM
MACRO
_Lock &lockoffset, &scratch1==r17, &scratch2==r18
mr &scratch1, r8
mr &scratch2, r9
addi r8, r1, &lockoffset
bl AcquireLock
mr r8, &scratch1
mr r9, &scratch2
ENDM
MACRO
_bset &dest, &src, &bit
IF &bit < 16
oris&dot &dest, &src, 1 << (15 - (&bit))
ELSE
ori&dot &dest, &src, 1 << (31 - (&bit))
ENDIF
ENDM
MACRO
_bclr &dest, &src, &bit
rlwinm&dot &dest, &src, 0, (&bit)+1, (&bit)-1
ENDM
MACRO
_band &dest, &src, &bit
IF &bit < 16
andis&dot &dest, &src, 1 << (15 - (&bit))
ELSE
andi&dot &dest, &src, 1 << (31 - (&bit))
ENDIF
ENDM

753
NanoKernel/NKPaging.s Normal file
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@ -0,0 +1,753 @@
Local_Panic set *
b panic
; PagingFunc1
; Xrefs:
; setup
; IntDSIOtherOther
; IntISI
; IntDSIOther
; kcVMDispatch
; print_memory_logical
align 5
PagingFunc1 ; OUTSIDE REFERER
mfsprg r29, 0
mflr r28
stw r8, -0x00dc(r29)
mfcr r8
stw r9, -0x00d8(r29)
stw r8, -0x00a4(r29)
stw r14, -0x00d4(r29)
stw r15, -0x00d0(r29)
stw r16, -0x00cc(r29)
stw r17, -0x00c8(r29)
stw r18, -0x00c4(r29)
stw r19, -0x00c0(r29)
stw r20, -0x00bc(r29)
stw r21, -0x00b8(r29)
stw r22, -0x00b4(r29)
stw r28, -0x00e0(r29)
b @_88
@_44
mfsprg r29, 0
lwz r8, -0x00a4(r29)
lwz r28, -0x00e0(r29)
mtcrf 0x7f, r8
lwz r8, -0x00dc(r29)
mtlr r28
lwz r9, -0x00d8(r29)
lwz r14, -0x00d4(r29)
lwz r15, -0x00d0(r29)
lwz r16, -0x00cc(r29)
lwz r17, -0x00c8(r29)
lwz r18, -0x00c4(r29)
lwz r19, -0x00c0(r29)
lwz r20, -0x00bc(r29)
lwz r21, -0x00b8(r29)
lwz r22, -0x00b4(r29)
blr
@_88
mfsprg r30, 0
mr r9, r27
lwz r8, -0x001c(r30)
bl FindAreaAbove
mr r31, r8
stw r8, -0x00e4(r30)
stw r27, -0x00e8(r30)
lwz r16, 0x0024(r31)
lwz r17, 0x0020(r31)
cmplw r16, r27
lwz r18, 0x007c(r31)
bgt- @_1a0
bgt+ @_44
and r28, r27, r18
rlwinm. r26, r17, 0, 16, 16
lwz r17, 0x0038(r31)
beq- @_fc
lwz r18, 0x0070(r31)
subf r19, r16, r28
clrlwi r31, r18, 0x1e
cmpwi cr7, r17, -0x01
cmpwi cr6, r31, 0x00
beq- cr7, @_1a0
beq+ cr6, @_44
cmpwi r17, 0x01
add r31, r18, r19
blt+ @_44
li r26, 0x00
b @_208
@_fc
mr r8, r27
bl MPCall_95_0x1e4
lwz r28, 0x0000(r30)
mr r26, r30
mr r8, r27
bl MPCall_95_0x254
beq- @_12c
lhz r16, 0x0000(r30)
rlwinm. r8, r16, 0, 16, 16
bne- @_12c
srwi r16, r16, 1
sth r16, 0x0000(r30)
@_12c
lwz r8, 0x0024(r31)
lwz r9, 0x06b4(r1)
cmpwi r8, 0x00
cmpwi cr6, r9, 0x00
li r8, 0x801
li r9, 0x01
bne- @_154
beq- cr6, @_154
li r8, 0x881
li r9, 0x81
@_154
lwz r31, 0x0688(r1)
and. r30, r28, r8
rlwimi r31, r28, 0, 0, 19
cmplwi cr6, r30, 0x800
cmplwi r30, 0x01
bge- cr6, @_2ec
cmplw cr7, r30, r9
ori r31, r31, 0x100
rlwimi r31, r28, 28, 28, 28
rlwimi r31, r28, 3, 24, 24
rlwimi r31, r28, 31, 26, 26
rlwimi r31, r28, 1, 25, 25
xori r31, r31, 0x40
rlwimi r31, r28, 30, 31, 31
rlwimi r31, r28, 0, 30, 30
xori r31, r31, 0x02
beq- @_208
blt+ cr7, @_44
bl Local_Panic
@_1a0
lwz r29, 0x05e8(r1)
rlwinm r28, r27, 7, 25, 28
lwzx r29, r29, r28
rlwinm r28, r27, 20, 16, 31
lhz r30, 0x0000(r29)
b @_1bc
@_1b8
lhzu r30, 0x0008(r29)
@_1bc
lhz r31, 0x0002(r29)
subf r30, r30, r28
cmplw cr7, r30, r31
bgt+ cr7, @_1b8
lwz r28, 0x0690(r1)
lwz r31, 0x0004(r29)
cmpwi cr7, r28, 0x00
bnel- cr7, @_314
rlwinm. r26, r31, 23, 29, 30
cmplwi cr7, r26, 0x06
beq- @_200
cmplwi cr6, r26, 0x02
beq- cr7, @_368
beq- cr6, @_3b8
b @_44
dc.l 0x41800168
dc.l 0x418101bc
@_200
slwi r28, r30, 12
add r31, r31, r28
@_208
mfsrin r30, r27
rlwinm r28, r27, 26, 10, 25
rlwinm r30, r30, 6, 7, 25
xor r28, r28, r30
lwz r30, KDP.PTEGMask(r1)
lwz r29, KDP.HTABORG(r1)
and r28, r28, r30
or. r29, r29, r28
@_228
lwz r30, 0x0000(r29)
lwz r28, 0x0008(r29)
cmpwi cr6, r30, 0x00
lwz r30, 0x0010(r29)
cmpwi cr7, r28, 0x00
lwzu r28, 0x0018(r29)
bge- cr6, @_298
cmpwi cr6, r30, 0x00
lwzu r30, 0x0008(r29)
bge- cr7, @_298
cmpwi cr7, r28, 0x00
lwzu r28, 0x0008(r29)
bge- cr6, @_298
cmpwi cr6, r30, 0x00
lwzu r30, 0x0008(r29)
bge- cr7, @_298
cmpwi cr7, r28, 0x00
lwzu r28, 0x0008(r29)
bge- cr6, @_298
cmpwi cr6, r30, 0x00
addi r29, r29, 0x08
bge- cr7, @_298
cmpwi cr7, r28, 0x00
addi r29, r29, 0x08
bge- cr6, @_298
rlwinm r28, r31, 0, 26, 26
addi r29, r29, 0x08
blt- cr7, @_3e0
@_298
cmpwi r26, 0x00
mfsrin r28, r27
rlwinm r30, r27, 10, 26, 31
stw r27, 0x0694(r1)
oris r30, r30, 0x8000
ori r31, r31, 0x100
rlwimi r30, r31, 27, 25, 25
rlwinm r31, r31, 0, 21, 19
rlwimi r30, r28, 7, 1, 24
stw r31, -0x0014(r29)
eieio
stwu r30, -0x0018(r29)
sync
lwz r28, 0x0e94(r1)
stw r29, 0x0698(r1)
addi r28, r28, 0x01
stw r28, 0x0e94(r1)
beq+ @_44
cmpwi r26, 0x5a5a
bne- @_2f4
stw r29, 0x0690(r1)
@_2ec
cmpw r29, r29
b @_44
@_2f4
lwz r28, 0x0000(r26)
lwz r30, KDP.HTABORG(r1)
ori r28, r28, 0x800
subf r30, r30, r29
cmpw r29, r29
rlwimi r28, r30, 9, 0, 19
stw r28, 0x0000(r26)
b @_44
@_314
lwz r28, 0x0e98(r1)
lwz r29, 0x0690(r1)
addi r28, r28, 0x01
stw r28, 0x0e98(r1)
li r28, 0x00
stw r28, 0x0000(r29)
lwz r29, 0x068c(r1)
stw r28, 0x068c(r1)
stw r28, 0x0690(r1)
mfspr r28, pvr
rlwinm. r28, r28, 0, 0, 14
sync
tlbie r29
beq- @_354
sync
tlbsync
@_354
sync
isync
blr
dc.l 0x57fca803
dc.l 0x40800068
@_368
slwi r28, r30, 2
rlwinm r26, r31, 22, 0, 29
lwzux r28, r26, r28
lwz r31, 0x0688(r1)
andi. r30, r28, 0x881
rlwimi r31, r28, 0, 0, 19
cmplwi cr6, r30, 0x800
cmplwi cr7, r30, 0x81
cmplwi r30, 0x01
bge+ cr6, @_2ec
cmplwi cr7, r30, 0x81
ori r31, r31, 0x100
rlwimi r31, r28, 3, 24, 24
rlwimi r31, r28, 31, 26, 26
rlwimi r31, r28, 1, 25, 25
xori r31, r31, 0x40
rlwimi r31, r28, 30, 31, 31
beq+ @_208
blt+ cr7, @_44
bl Local_Panic
@_3b8
ori r28, r27, 0xfff
stw r28, 0x068c(r1)
rlwinm r31, r31, 0, 22, 19
li r26, 0x5a5a
b @_208
dc.l 0x4181fc78
dc.l 0x4bfffc11
dc.l 0x3ba105c8
dc.l 0x48000281
dc.l 0x4bfffc68
@_3e0
cmplw cr6, r28, r26
addi r29, r29, -0x50
ble- cr6, @_400
crnot 2, 2
lwz r30, KDP.PTEGMask(r1)
xori r31, r31, 0x800
xor r29, r29, r30
beq+ @_228
@_400
lwz r26, 0x069c(r1)
crclr cr6_eq
rlwimi r26, r29, 0, 0, 25
li r9, 0x08
addi r29, r26, 0x08
b @_428
dc.l 0x409a0008
dc.l 0x7fbaeb78
@_420
cmpw cr6, r29, r26
addi r29, r29, 0x08
@_428
rlwimi r29, r26, 0, 0, 25
lwz r31, 0x0004(r29)
lwz r30, 0x0000(r29)
beq- cr6, @_444
rlwinm r28, r31, 30, 25, 25
andc. r28, r28, r30
bne+ @_420
@_444
addi r9, r9, -0x01
cmpwi cr7, r9, 0x00
rlwinm r31, r30, 0, 25, 25
blel+ cr7, Local_Panic
rlwinm r28, r30, 1, 0, 3
neg r31, r31
rlwimi r28, r30, 22, 4, 9
xor r31, r31, r29
rlwimi r28, r30, 5, 10, 19
rlwinm r31, r31, 6, 10, 19
xor r28, r28, r31
xoris r30, r30, 0x8000
lwz r31, 0x0e9c(r1)
stw r29, 0x069c(r1)
addi r31, r31, 0x01
stw r31, 0x0e9c(r1)
lwz r31, 0x0e98(r1)
stw r30, 0x0000(r29)
addi r31, r31, 0x01
stw r31, 0x0e98(r1)
sync
mfspr r31, pvr
rlwinm. r31, r31, 0, 0, 14
tlbie r28
beq- @_4b0
sync
tlbsync
@_4b0
sync
isync
li r8, -0x01
stw r8, 0x0340(r1)
stw r8, 0x0348(r1)
stw r8, 0x0350(r1)
stw r8, 0x0358(r1)
mfsprg r8, 0
mr r9, r28
lwz r8, -0x001c(r8)
bl FindAreaAbove
lwz r16, 0x0024(r8)
mr r31, r8
cmplw r16, r28
mr r8, r28
bgt- @_600
bgt+ Local_Panic
bl MPCall_95_0x1e4
mr r26, r30
beql+ @_88
@_500
lwz r28, 0x0000(r26)
lwz r31, 0x0004(r29)
andi. r30, r28, 0x800
rlwinm r30, r28, 23, 9, 28
xor r30, r30, r29
beq+ Local_Panic
andi. r30, r30, 0xffff
xori r28, r28, 0x800
bne+ Local_Panic
rlwimi r28, r31, 0, 0, 19
rlwimi r28, r31, 29, 27, 27
rlwimi r28, r31, 27, 28, 28
stw r28, 0x0000(r26)
bl @_88
_log 'PTEG overflow: EA '
mr r8, r27
bl Printw
_log 'Victim EA: '
mr r8, r28
bl Printw
_log 'MapInfo: '
mr r8, r29
bl Printw
lwz r16, 0x0000(r26)
mr r8, r26
bl Printw
mr r8, r16
bl Printw
_log ' PTE: '
lwz r16, 0x0000(r29)
lwz r17, 0x0004(r29)
mr r8, r29
bl Printw
mr r8, r16
bl Printw
mr r8, r17
bl Printw
_log '^n'
bl @_88
@_600
lwz r26, 0x05e8(r1)
rlwinm r30, r28, 7, 25, 28
lwzx r26, r26, r30
@_60c
lhz r30, 0x0000(r26)
rlwinm r31, r28, 20, 16, 31
subf r30, r30, r31
lhz r31, 0x0002(r26)
addi r26, r26, 0x08
cmplw cr7, r30, r31
lwz r31, -0x0004(r26)
andi. r31, r31, 0xe01
cmpwi r31, 0xa01
bgt+ cr7, @_60c
beq+ @_60c
lwz r26, -0x0004(r26)
slwi r30, r30, 2
rlwinm r31, r26, 22, 30, 31
cmpwi cr7, r31, 0x03
rlwinm r26, r26, 22, 0, 29
add r26, r26, r30
bnel+ cr7, @_88
b @_500
; PagingFunc2
; Xrefs:
; setup
PagingFunc2 ; OUTSIDE REFERER
sync
isync
lwz r28, 0x0000(r29)
stw r28, 0x05e8(r1)
addi r28, r28, 0x84
lis r31, 0x00
@_18
lwzu r30, -0x0008(r28)
addis r31, r31, -0x1000
mr. r31, r31
mtsrin r30, r31
bne+ @_18
isync
PagingFunc2AndAHalf
lwz r28, 0x0004(r29)
mfspr r31, pvr
rlwinm. r31, r31, 0, 0, 14
addi r29, r1, 0x00
stw r28, 0x05ec(r1)
beq- @_168
li r30, 0x00
mtspr ibat0u, r30
mtspr ibat1u, r30
mtspr ibat2u, r30
mtspr ibat3u, r30
mtspr dbat0u, r30
mtspr dbat1u, r30
mtspr dbat2u, r30
mtspr dbat3u, r30
rlwimi r29, r28, 7, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
rlwinm r31, r31, 0, 29, 27
mtspr ibat0l, r31
mtspr ibat0u, r30
stw r31, 0x0304(r1)
stw r30, 0x0300(r1)
rlwimi r29, r28, 11, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
rlwinm r31, r31, 0, 29, 27
mtspr ibat1l, r31
mtspr ibat1u, r30
stw r31, 0x030c(r1)
stw r30, 0x0308(r1)
rlwimi r29, r28, 15, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
rlwinm r31, r31, 0, 29, 27
mtspr ibat2l, r31
mtspr ibat2u, r30
stw r31, 0x0314(r1)
stw r30, 0x0310(r1)
rlwimi r29, r28, 19, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
rlwinm r31, r31, 0, 29, 27
mtspr ibat3l, r31
mtspr ibat3u, r30
stw r31, 0x031c(r1)
stw r30, 0x0318(r1)
rlwimi r29, r28, 23, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
mtspr dbat0l, r31
mtspr dbat0u, r30
stw r31, 0x0324(r1)
stw r30, 0x0320(r1)
rlwimi r29, r28, 27, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
mtspr dbat1l, r31
mtspr dbat1u, r30
stw r31, 0x032c(r1)
stw r30, 0x0328(r1)
rlwimi r29, r28, 31, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
mtspr dbat2l, r31
mtspr dbat2u, r30
stw r31, 0x0334(r1)
stw r30, 0x0330(r1)
rlwimi r29, r28, 3, 25, 28
lwz r31, 0x0284(r29)
lwz r30, 0x0280(r29)
mtspr dbat3l, r31
mtspr dbat3u, r30
stw r31, 0x033c(r1)
stw r30, 0x0338(r1)
isync
cmpw r29, r29
blr
@_168
rlwimi r29, r28, 7, 25, 28
lwz r30, 0x0280(r29)
lwz r31, 0x0284(r29)
stw r30, 0x0300(r1)
stw r31, 0x0304(r1)
stw r30, 0x0320(r1)
stw r31, 0x0324(r1)
rlwimi r30, r31, 0, 25, 31
mtspr ibat0u, r30
lwz r30, 0x0280(r29)
rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25
mtspr ibat0l, r31
rlwimi r29, r28, 11, 25, 28
lwz r30, 0x0280(r29)
lwz r31, 0x0284(r29)
stw r30, 0x0308(r1)
stw r31, 0x030c(r1)
stw r30, 0x0328(r1)
stw r31, 0x032c(r1)
rlwimi r30, r31, 0, 25, 31
mtspr ibat1u, r30
lwz r30, 0x0280(r29)
rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25
mtspr ibat1l, r31
rlwimi r29, r28, 15, 25, 28
lwz r30, 0x0280(r29)
lwz r31, 0x0284(r29)
stw r30, 0x0310(r1)
stw r31, 0x0314(r1)
stw r30, 0x0330(r1)
stw r31, 0x0334(r1)
rlwimi r30, r31, 0, 25, 31
mtspr ibat2u, r30
lwz r30, 0x0280(r29)
rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25
mtspr ibat2l, r31
rlwimi r29, r28, 19, 25, 28
lwz r30, 0x0280(r29)
lwz r31, 0x0284(r29)
stw r30, 0x0318(r1)
stw r31, 0x031c(r1)
stw r30, 0x0338(r1)
stw r31, 0x033c(r1)
rlwimi r30, r31, 0, 25, 31
mtspr ibat3u, r30
lwz r30, 0x0280(r29)
rlwimi r31, r30, 30, 26, 31
rlwimi r31, r30, 6, 25, 25
mtspr ibat3l, r31
cmpw r29, r29
blr
; PagingFunc3
; Xrefs:
; IntDSIOtherOther
; kcRunAlternateContext
; kcRTASDispatch
; KCRegisterCpuPlugin
; MPCall_103
PagingFunc3 ; OUTSIDE REFERER
lwz r30, 0x0000(r29)
li r28, -0x01
rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30
andc. r31, r31, r28
beq- @_54
lwzu r30, 0x0008(r29)
rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30
andc. r31, r31, r28
beq- @_54
lwzu r30, 0x0008(r29)
rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30
andc. r31, r31, r28
beq- @_54
lwzu r30, 0x0008(r29)
rlwimi r28, r30, 15, 0, 14
xor r31, r27, r30
andc. r31, r31, r28
bne- PagingFunc4
@_54
andi. r31, r30, 0x01
rlwinm r28, r28, 0, 8, 19
lwzu r31, 0x0004(r29)
and r28, r27, r28
or r31, r31, r28
bnelr-
; PagingFunc4
; Xrefs:
; setup
; PagingFunc3
; print_memory_logical
; major_0x18c08
PagingFunc4 ; OUTSIDE REFERER
mfsrin r31, r27
rlwinm r30, r27, 10, 26, 31
rlwimi r30, r31, 7, 1, 24
rlwinm r28, r27, 26, 10, 25
oris r30, r30, 0x8000
rlwinm r31, r31, 6, 7, 25
xor r28, r28, r31
lwz r31, KDP.PTEGMask(r1)
lwz r29, KDP.HTABORG(r1)
and r28, r28, r31
or. r29, r29, r28
@_2c
lwz r31, 0x0000(r29)
lwz r28, 0x0008(r29)
cmpw cr6, r30, r31
lwz r31, 0x0010(r29)
cmpw cr7, r30, r28
lwzu r28, 0x0018(r29)
bne- cr6, @_50
@_48
lwzu r31, -0x0014(r29)
blr
@_50
cmpw cr6, r30, r31
lwzu r31, 0x0008(r29)
beq+ cr7, @_48
cmpw cr7, r30, r28
lwzu r28, 0x0008(r29)
beq+ cr6, @_48
cmpw cr6, r30, r31
lwzu r31, 0x0008(r29)
beq+ cr7, @_48
cmpw cr7, r30, r28
lwzu r28, 0x0008(r29)
beq+ cr6, @_48
cmpw cr6, r30, r31
lwzu r31, -0x000c(r29)
beqlr- cr7
cmpw cr7, r30, r28
lwzu r31, 0x0008(r29)
beqlr- cr6
lwzu r31, 0x0008(r29)
beqlr- cr7
lwz r31, KDP.PTEGMask(r1)
xori r30, r30, 0x40
andi. r28, r30, 0x40
addi r29, r29, -0x3c
xor r29, r29, r31
bne+ @_2c
blr
; PagingFlushTLB
; Xrefs:
; setup
; major_0x14bcc
; MPCall_103
pb equ 12
PagingFlushTLB ; OUTSIDE REFERER
lhz r29, KDP.ProcessorInfo + NKProcessorInfo.TransCacheTotalSize(r1)
slwi r29, r29, pb
@loop
subi r29, r29, 1 << pb
cmpwi r29, 0
tlbie r29
bgt+ @loop
mfspr r29, pvr
rlwinm. r29, r29, 0, 0, 14
; All cpus
sync
beqlr-
; Non-601 stuff
tlbsync
sync
isync
blr

530
NanoKernel/NKPoolAllocator.s Normal file
View File

@ -0,0 +1,530 @@
Local_Panic set *
b panic
; InitPool
; Allocate one page for the kernel pool. Same layout at
; Memtop starts at 7 pages below KDP.
; Take note of the structure from kdp-ab0 to kdp-aa0
; Xrefs:
; setup
; > r1 = kdp
InitPool ; OUTSIDE REFERER
; r9 = LA_KD - 7 pages
lwz r8, KDP.PA_ConfigInfo(r1)
lwz r8, NKConfigurationInfo.LA_KernelData(r8)
lisori r9, 0x7000
subf r9, r9, r8
stw r9, -0x0a9c(r1)
lisori r9, -0x7000
add r9, r9, r1
stw r9, -0x0aa0(r1)
; bit of a mystery
lisori r8, 0x00006458
add r23, r8, r9
stw r8, 0x0000(r9)
lisori r8, '‡BGN'
stw r8, 0x0004(r9)
addi r9, r9, 0x08
lisori r8, 0x00006450
stw r8, 0x0000(r9)
lisori r8, 'free'
stw r8, 0x0004(r9)
li r8, 0x00
stw r8, 0x0000(r23)
lisori r8, '‡END'
stw r8, 0x0004(r23)
; set up linked list
addi r8, r1, PSA.FreePool
stw r9, LLL.Next(r8)
stw r9, LLL.Prev(r8)
stw r8, LLL.Next(r9)
stw r8, LLL.Prev(r9)
lisori r9, 'POOL'
stw r9, LLL.Signature(r8)
blr
; PoolAlloc
; Easy to use! 0xfd8 (a page minus 10 words) is the
; largest request that can be satisfied.
; Xrefs:
; setup
; major_0x02ccc
; KCCreateProcess
; KCCreateCpuStruct
; MPCall_15
; MPCall_39
; MPCall_17
; MPCall_20
; MPCall_25
; MPCall_49
; MPCall_40
; MPCall_31
; MPCall_64
; major_0x0db04
; CreateTask
; MPCall_58
; convert_pmdts_to_areas
; NKCreateAddressSpaceSub
; MPCall_72
; createarea
; MPCall_73
; MPCall_130
; InitTMRQs
; InitIDIndex
; MakeID
; > r1 = kdp
; > r8 = size
; < r8 = ptr
PoolAlloc ; OUTSIDE REFERER
crclr cr7_eq
b PoolAllocCommon
PoolAlloc_with_crset ; OUTSIDE REFERER
crset cr7_eq
PoolAllocCommon
; Save LR and arg to EWA. Get lock.
mflr r17
mfsprg r18, 0
_Lock PSA.PoolLock, scratch1=r15, scratch2=r16
; These saves are my first real hint at the contents of that
; large unexplored area of the EWA. This file, then, owns
; part of the EWA, for its CPU-scoped globals. Because the
; kernel runs stackless.
stw r17, EWA.PoolSavedLR(r18)
stw r8, EWA.PoolSavedSizeArg(r18)
@try_again
; Check that requested allocation is in the doable size range.
cmpwi r8, 0
cmpwi cr1, r8, 0xfd8
ble+ Local_Panic ; zero-byte request => thud
bgt- cr1, @request_too_large
addi r8, r8, 39
rlwinm r8, r8, 0, 0, 26
; Check that the pool has any pages in it.
addi r14, r1, PSA.FreePool
lwz r15, LLL.Next(r14)
@try_different_page
cmpw r14, r15
bne+ @pool_has_page
; No? Then claim a page from the system free list for the pool?
; Got a free page in the system free list? It's ours.
li r8, 0 ; return zero if there is no page at all
li r9, 1 ; number of pages to grab
lwz r16, PSA.FreePageCount(r1)
lwz r17, PSA.UnheldFreePageCount(r1)
subf. r16, r9, r16
subf r17, r9, r17
blt- PoolCommonReturn
stw r16, PSA.FreePageCount(r1)
stw r17, PSA.UnheldFreePageCount(r1)
; Get that page, mofo. Macros FTW.
lwz r8, PSA.FreeList + LLL.Next(r1)
RemoveFromList r8, scratch1=r17, scratch2=r18
; There was probably once a mechanism for virtual addressing of the pool!
li r9, 0
bl ExtendPool ; r8=page, r9=virt=0
; Now that the pool is not empty, start over.
mfsprg r18, 0
lwz r8, EWA.PoolSavedSizeArg(r18)
b @try_again
@request_too_large
li r8, 0
b PoolCommonReturn
@pool_has_page
; We have a page (r15) that might have room in it.
; r8 contains the size describing our actual demand on the page!
lwz r16, PoolPage.FreeBytes(r15)
cmplw r16, r8
lis r20, 'fr'
bgt- @fits_with_leftover_space
beq- @fits_perfectly
ori r20, r20, 'ee'
lwz r16, PoolPage.FreeBytes(r15)
add r18, r16, r15 ; r18 = ???
lwz r19, 0x0004(r18)
cmplw cr1, r18, r15
cmpw r19, r20
ble+ cr1, Local_Panic
bne- @_118
lwz r17, 0x0000(r18)
rotlwi r19, r19, 0x08
add r17, r17, r16
stw r17, 0x0000(r15)
stw r19, 0x0004(r18)
lwz r17, 0x000c(r18)
lwz r16, LLL.Next(r18)
stw r16, LLL.Next(r17)
stw r17, 0x000c(r16)
b @pool_has_page
@_118
lwz r15, LLL.Next(r15)
b @try_different_page
@fits_with_leftover_space
subf r16, r8, r16
cmpwi r16, 0x28
blt- @fits_perfectly
stw r16, 0x0000(r15)
add r15, r15, r16
stw r8, 0x0000(r15)
b @_14c
@fits_perfectly
lwz r14, 0x000c(r15)
lwz r16, LLL.Next(r15)
stw r16, LLL.Next(r14)
stw r14, 0x000c(r16)
@_14c
lisori r8, '‡loc'
stw r8, 0x0004(r15)
addi r8, r15, 0x08
beq- cr7, PoolCommonReturn
lwz r16, 0x0000(r15)
addi r16, r16, -0x08
li r14, 0x00
add r16, r16, r15
addi r15, r15, 0x04
@_174
stwu r14, 0x0004(r15)
cmpw r15, r16
ble+ @_174
b PoolCommonReturn
; PoolFree
; ARG void *r8
PoolFree ; OUTSIDE REFERER
mflr r17
mfsprg r18, 0
_Lock PSA.PoolLock, scratch1=r15, scratch2=r16
stw r17, EWA.PoolSavedLR(r18)
bl major_0x129fc
bl major_0x12a34
; File-internal
; Return path of most of these functions?
; Releases Pool lock and Returns to the link
; address saved in EWA.
PoolCommonReturn ; OUTSIDE REFERER
mfsprg r18, 0
sync
lwz r15, PSA.PoolLock + Lock.Count(r1)
cmpwi cr1, r15, 0
li r15, 0
bne+ cr1, @no_panic
mflr r15
bl panic
@no_panic
stw r15, PSA.PoolLock + Lock.Count(r1)
lwz r17, EWA.PoolSavedLR(r18)
mtlr r17
blr
; major_0x129fc
; Xrefs:
; PoolFree
; ExtendPool
; ARG Area *r8
major_0x129fc ; OUTSIDE REFERER
subi r15, r8, 8
lis r20, 'fr'
lhz r16, 4(r15)
ori r20, r20, 'ee'
cmplwi r16, 0x876c
bne+ Local_Panic
stw r20, 4(r15)
addi r16, r1, PSA.FreePool
InsertAsPrev r15, r16, scratch=r17
blr
; major_0x12a34
; Xrefs:
; PoolFree
; ExtendPool
major_0x12a34 ; OUTSIDE REFERER
lis r20, 0x6672
lwz r16, 0x0000(r15)
ori r20, r20, 0x6565
add r18, r16, r15
lwz r19, 0x0004(r18)
cmplw cr1, r18, r15
cmpw r19, r20
ble+ cr1, Local_Panic
bnelr-
lwz r17, 0x0000(r18)
rotlwi r19, r19, 0x08
add r17, r17, r16
stw r17, 0x0000(r15)
stw r19, 0x0004(r18)
lwz r17, 0x000c(r18)
lwz r16, LLL.Next(r18)
stw r16, LLL.Next(r17)
stw r17, 0x000c(r16)
b major_0x12a34
; ExtendPool
; 0xed0(r1) = pool extends (I increment)
; -0xa9c(r1) = virt last page (I update)
; -0xaa0(r1) = phys last page (I update)
; Assumes that cache blocks are 32 bytes! Uh-oh.
; Page gets decorated like this:
; 000: 00 00 0f e8
; 004: 87 'B 'G 'N
; 008: 00 00 0f e8
; 00c: 87 'l 'o 'c
; ... zeros << r8 passes ptr to here
; fe8: phys offset from here to prev page
; fec: 87 'E 'N 'D
; ff0: logical abs address of prev page
; ff4: 00 00 00 00
; ff8: 00 00 00 00
; ffc: 00 00 00 00
; Xrefs:
; MPCall_0
; PoolAlloc
; > r1 = kdp
; > r8 = anywhere in new page (phys)
; > r9 = page_virt
ExtendPool ; OUTSIDE REFERER
mflr r14
rlwinm r17, r8, 0, 0, 19
lwz r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1)
addi r16, r16, 1
stw r16, KDP.NanoKernelInfo + NKNanoKernelInfo.FreePoolExtendCount(r1)
_log 'Extend free pool: phys 0x'
mr r8, r17
bl Printw
_log ' virt 0x'
mr r8, r9
bl Printw
_log ' count: '
mr r8, r16
bl Printd
_log '^n'
li r16, 0x1000
@zeroloop
subi r16, r16, 32
cmpwi r16, 0
dcbz r16, r17
bgt+ @zeroloop
; Put the funny stuff in
li r16, 0xfe8
stw r16, 0x0000(r17)
lisori r16, '‡BGN'
stw r16, 0x0004(r17)
addi r15, r17, 0x08
li r16, 0xfe0
stw r16, 0x0000(r15)
lisori r16, '‡loc'
stw r16, 0x0004(r15)
addi r15, r17, 0xfe8
lwz r18, -0x0aa0(r1)
subf r18, r15, r18
stw r18, 0x0000(r15)
lisori r16, '‡END'
stw r16, 0x0004(r15)
lwz r16, -0x0a9c(r1)
stw r16, LLL.Next(r15)
; Update globals
stw r9, -0x0a9c(r1)
stw r17, -0x0aa0(r1)
; Unknown func calls
addi r8, r17, 0x10
bl major_0x129fc
bl major_0x12a34
mtlr r14
blr
; major_0x12b94
; Xrefs:
; "HeapSegCorrupt"
mflr r19
lwz r20, -0x0aa0(r1)
major_0x12b94_0x8
addi r8, r20, 0x08
bl major_0x12b94_0x30
lwz r17, 0x0000(r20)
add r17, r17, r20
lwz r18, 0x0000(r17)
cmpwi r18, 0x00
add r20, r18, r17
bne+ major_0x12b94_0x8
mtlr r19
blr
major_0x12b94_0x30
mflr r14
addi r16, r8, -0x08
major_0x12b94_0x38
lwz r17, 0x0004(r16)
lis r18, -0x78bb
ori r18, r18, 0x4e44
cmpw r17, r18
li r9, 0x00
beq- major_0x12b94_0x1a4
lis r18, -0x7894
ori r18, r18, 0x6f63
cmpw r17, r18
beq- major_0x12b94_0x94
lis r18, 0x6672
ori r18, r18, 0x6565
li r9, 0x04
cmpw r17, r18
bne- major_0x12b94_0xa8
lwz r17, 0x000c(r16)
cmpwi r17, 0x00
li r9, 0x05
beq- major_0x12b94_0xa8
lwz r17, LLL.Next(r16)
cmpwi r17, 0x00
li r9, 0x06
beq- major_0x12b94_0xa8
major_0x12b94_0x94
lwz r17, 0x0000(r16)
add r16, r16, r17
cmpwi r17, 0x00
li r9, 0x07
bgt+ major_0x12b94_0x38
major_0x12b94_0xa8
mr r18, r8
_log 'Heap segment corrupt '
mr r8, r9
bl Printd
_log 'at '
mr r8, r16
bl Printw
_log '^n'
addi r16, r16, -0x40
li r17, 0x08
major_0x12b94_0x10c
mr r8, r16
bl Printw
_log ' '
lwz r8, 0x0000(r16)
bl Printw
lwz r8, 0x0004(r16)
bl Printw
lwz r8, LLL.Next(r16)
bl Printw
lwz r8, 0x000c(r16)
bl Printw
_log ' *'
li r8, 0x10
addi r16, r16, -0x01
mtctr r8
major_0x12b94_0x164
lbzu r8, 0x0001(r16)
cmpwi r8, 0x20
bgt- major_0x12b94_0x174
li r8, 0x20
major_0x12b94_0x174
bl Printc
bdnz+ major_0x12b94_0x164
_log '*^n'
addi r17, r17, -0x01
addi r16, r16, 0x01
cmpwi r17, 0x00
bne+ major_0x12b94_0x10c
mr r8, r18
major_0x12b94_0x1a4
mtlr r14
blr

579
NanoKernel/NKPowerCalls.s Normal file
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@ -0,0 +1,579 @@
; FillIndigo
; Xrefs:
; setup
align kIntAlign
FillIndigo ; EXPORTED
mflr r9
llabel r23, panic
add r23, r23, r25
addi r8, r1, PSA.IndigoVecBase
li r22, 192 ;VecTable.Size
bl wordfill
mtlr r9
llabel r23, IntIndigo
add r23, r23, r25
stw r23, VecTable.SystemResetVector(r8)
stw r23, VecTable.ExternalIntVector(r8)
stw r23, VecTable.DecrementerVector(r8)
blr
; kcPowerDispatch
; NB: I was probably wrong about this.
; Contains a (very rare) mtsprg0 instruction.
; Xrefs:
; "sup"
align kIntAlign
kcPowerDispatch ; EXPORTED ; OUTSIDE REFERER
mtcr r7
lwz r4, 0x0670(r1)
cmplwi cr7, r3, 0x0b
mr r9, r13
blt- cr2, kcPowerDispatch_0x18
lwz r9, -0x0440(r1)
kcPowerDispatch_0x18
and. r8, r4, r9
bgt- cr7, major_0x09e28_0x34
bne- major_0x09e28_0x2c
cmplwi cr7, r3, 0x0b
beq- cr7, major_0x0a600_0x1c
cmplwi cr7, r3, 0x08
beq- cr7, major_0x09e28_0x3c
cmplwi cr7, r3, 0x09
beq- cr7, major_0x0a600_0x10
stw r26, 0x01d4(r6)
stw r27, 0x01dc(r6)
stw r28, 0x01e4(r6)
stw r29, 0x01ec(r6)
stw r30, 0x01f4(r6)
stw r31, 0x01fc(r6)
mfsprg r31, 3
addi r8, r1, -0x810
mtsprg 3, r8
rlwinm r26, r3, 0, 29, 29
clrlwi r3, r3, 0x1e
lbz r8, 0x06b8(r1)
slwi r3, r3, 1
addi r3, r3, 0x1a
rlwnm r3, r8, r3, 0x1e, 0x1f
cmpwi r3, 0x00
beq- major_0x09e28_0x24
lbz r9, 0x06b9(r1)
cmpwi r9, 0x00
beq- kcPowerDispatch_0xb0
mfspr r27, hid0
mr r8, r27
cmpwi r9, 0x01
beq- kcPowerDispatch_0xa8
oris r9, r3, 0x100
srw r9, r9, r9
rlwimi r8, r9, 0, 8, 10
kcPowerDispatch_0xa8
oris r8, r8, 0x01
mtspr hid0, r8
kcPowerDispatch_0xb0
cmplwi r26, 0x04
beql- kcCacheDispatch_0x258
mfmsr r8
ori r8, r8, 0x8002
cmplwi r3, 0x00
beq- kcPowerDispatch_0xcc
oris r8, r8, 0x04
kcPowerDispatch_0xcc
sync
mtmsr r8
isync
kcPowerDispatch_0xd8
b kcPowerDispatch_0xd8
; IntIndigo
; Odd that this is unaligned
IntIndigo
lbz r8, 0x06b9(r1)
cmpwi r8, 0x00
beq- IntIndigo_0x10
mtspr hid0, r27
IntIndigo_0x10
mfsprg r1, 2
mtlr r1
mfsprg r1, 1
lis r9, 0x7fff
mfspr r8, dec
mtspr dec, r9
mtspr dec, r8
; major_0x09e28
; Xrefs:
; kcPowerDispatch
; IntIndigo
li r3, 0x00
major_0x09e28_0x4
mtsprg 3, r31
lwz r26, 0x01d4(r6)
lwz r27, 0x01dc(r6)
lwz r28, 0x01e4(r6)
lwz r29, 0x01ec(r6)
lwz r30, 0x01f4(r6)
lwz r31, 0x01fc(r6)
b skeleton_key
major_0x09e28_0x24 ; OUTSIDE REFERER
li r3, -0x7267
b major_0x09e28_0x4
major_0x09e28_0x2c ; OUTSIDE REFERER
li r3, 0x00
b skeleton_key
major_0x09e28_0x34 ; OUTSIDE REFERER
li r3, -0x01
b skeleton_key
major_0x09e28_0x3c ; OUTSIDE REFERER
mfsprg r9, 0
lwz r8, -0x0338(r9)
lwz r9, 0x0024(r8)
cmpwi r9, 0x01
li r3, -0x7267
bgt+ skeleton_key
stw r26, 0x01d4(r6)
stw r27, 0x01dc(r6)
stw r28, 0x01e4(r6)
stw r29, 0x01ec(r6)
stw r30, 0x01f4(r6)
stw r31, 0x01fc(r6)
bl kcCacheDispatch_0x258
mfspr r9, hid0
rlwinm r9, r9, 0, 18, 16
rlwinm r9, r9, 0, 17, 15
mtspr hid0, r9
sync
isync
lwz r26, 0x0f68(r1)
andi. r26, r26, 0x01
beq- major_0x09e28_0xb0
mfspr r9, l2cr
clrlwi r9, r9, 0x01
mtspr l2cr, r9
sync
isync
addi r8, r1, -0x4d0
stw r9, 0x0050(r8)
major_0x09e28_0xb0
stw r7, 0x0000(r6)
stw r2, 0x0114(r6)
stw r3, 0x011c(r6)
stw r4, 0x0124(r6)
stw r5, 0x012c(r6)
stw r14, 0x0174(r6)
stw r15, 0x017c(r6)
stw r16, 0x0184(r6)
stw r17, 0x018c(r6)
stw r18, 0x0194(r6)
stw r19, 0x019c(r6)
stw r20, 0x01a4(r6)
stw r21, 0x01ac(r6)
stw r22, 0x01b4(r6)
stw r23, 0x01bc(r6)
stw r24, 0x01c4(r6)
stw r25, 0x01cc(r6)
stw r13, 0x00dc(r6)
andi. r8, r11, 0x2000
beq- major_0x09e28_0x198
mfmsr r8
ori r8, r8, 0x2000
mtmsr r8
isync
stfd f0, 0x0200(r6)
stfd f1, 0x0208(r6)
stfd f2, 0x0210(r6)
stfd f3, 0x0218(r6)
stfd f4, 0x0220(r6)
stfd f5, 0x0228(r6)
stfd f6, 0x0230(r6)
stfd f7, 0x0238(r6)
stfd f8, 0x0240(r6)
stfd f9, 0x0248(r6)
stfd f10, 0x0250(r6)
stfd f11, 0x0258(r6)
stfd f12, 0x0260(r6)
stfd f13, 0x0268(r6)
stfd f14, 0x0270(r6)
stfd f15, 0x0278(r6)
stfd f16, 0x0280(r6)
mffs f0
stfd f17, 0x0288(r6)
stfd f18, 0x0290(r6)
stfd f19, 0x0298(r6)
stfd f20, 0x02a0(r6)
stfd f21, 0x02a8(r6)
stfd f22, 0x02b0(r6)
stfd f23, 0x02b8(r6)
stfd f24, 0x02c0(r6)
stfd f25, 0x02c8(r6)
stfd f26, 0x02d0(r6)
stfd f27, 0x02d8(r6)
stfd f28, 0x02e0(r6)
stfd f29, 0x02e8(r6)
stfd f30, 0x02f0(r6)
stfd f31, 0x02f8(r6)
stfd f0, 0x00e0(r6)
major_0x09e28_0x198
mfxer r9
addi r16, r1, -0x4d0
stw r9, 0x00d4(r6)
mfctr r9
stw r9, 0x00f0(r6)
stw r12, 0x00e8(r6)
stw r10, 0x0054(r16)
stw r11, 0x0058(r16)
mfspr r9, hid0
stw r9, 0x0064(r16)
major_0x09e28_0x1c0
mftbu r9
stw r9, 0x005c(r16)
mftb r9
stw r9, 0x0060(r16)
mftbu r8
lwz r9, 0x005c(r16)
cmpw r8, r9
bne+ major_0x09e28_0x1c0
mfmsr r9
stw r9, 0x006c(r16)
mfspr r9, sdr1
stw r9, 0x0070(r16)
mfspr r9, dbat0u
stw r9, 0x0000(r16)
mfspr r9, dbat0l
stw r9, 0x0004(r16)
mfspr r9, dbat1u
stw r9, 0x0008(r16)
mfspr r9, dbat1l
stw r9, 0x000c(r16)
mfspr r9, dbat2u
stw r9, 0x0010(r16)
mfspr r9, dbat2l
stw r9, 0x0014(r16)
mfspr r9, dbat3u
stw r9, 0x0018(r16)
mfspr r9, dbat3l
stw r9, 0x001c(r16)
mfspr r9, ibat0u
stw r9, 0x0020(r16)
mfspr r9, ibat0l
stw r9, 0x0024(r16)
mfspr r9, ibat1u
stw r9, 0x0028(r16)
mfspr r9, ibat1l
stw r9, 0x002c(r16)
mfspr r9, ibat2u
stw r9, 0x0030(r16)
mfspr r9, ibat2l
stw r9, 0x0034(r16)
mfspr r9, ibat3u
stw r9, 0x0038(r16)
mfspr r9, ibat3l
stw r9, 0x003c(r16)
mfsprg r9, 0
stw r9, 0x0040(r16)
mfsprg r9, 1
stw r9, 0x0044(r16)
mfsprg r9, 2
stw r9, 0x0048(r16)
mfsprg r9, 3
stw r9, 0x004c(r16)
stw r6, 0x007c(r16)
bl major_0x09e28_0x59c
lwz r1, 0x0004(r1)
addi r16, r1, -0x4d0
lis r8, 0x100
ori r8, r8, 0x00
lis r9, 0x00
major_0x09e28_0x2ac
addis r9, r9, -0x1000
addis r8, r8, -0x10
mr. r9, r9
mtsrin r8, r9
bne+ major_0x09e28_0x2ac
isync
mfspr r9, hid0
li r8, 0x800
ori r8, r8, 0x200
or r9, r9, r8
mtspr hid0, r9
isync
andc r9, r9, r8
mtspr hid0, r9
isync
ori r9, r9, 0x8000
ori r9, r9, 0x4000
mtspr hid0, r9
isync
lwz r26, 0x0f68(r1)
andi. r26, r26, 0x01
beq- major_0x09e28_0x38c
lwz r8, 0x0f54(r1)
mr. r8, r8
beq- major_0x09e28_0x38c
mfspr r9, hid0
rlwinm r9, r9, 0, 12, 10
mtspr hid0, r9
isync
lwz r9, 0x0050(r16)
mtspr l2cr, r9
sync
isync
lis r8, 0x20
or r8, r9, r8
mtspr l2cr, r8
sync
isync
major_0x09e28_0x344
mfspr r8, l2cr
rlwinm. r8, r8, 31, 0, 0
bne+ major_0x09e28_0x344
mfspr r8, l2cr
lis r9, -0x21
ori r9, r9, 0xffff
and r8, r8, r9
mtspr l2cr, r8
sync
mfspr r8, hid0
oris r8, r8, 0x10
mtspr hid0, r8
isync
mfspr r8, l2cr
oris r8, r8, 0x8000
mtspr l2cr, r8
sync
isync
major_0x09e28_0x38c
lwz r6, 0x007c(r16)
lwz r7, 0x0000(r6)
lwz r13, 0x00dc(r6)
lwz r9, 0x00f0(r6)
mtctr r9
lwz r12, 0x00e8(r6)
lwz r9, 0x00d4(r6)
mtxer r9
lwz r10, 0x0054(r16)
lwz r11, 0x0058(r16)
lwz r2, 0x0114(r6)
lwz r3, 0x011c(r6)
lwz r4, 0x0124(r6)
lwz r5, 0x012c(r6)
lwz r14, 0x0174(r6)
lwz r15, 0x017c(r6)
lwz r17, 0x018c(r6)
lwz r18, 0x0194(r6)
lwz r19, 0x019c(r6)
lwz r20, 0x01a4(r6)
lwz r21, 0x01ac(r6)
lwz r22, 0x01b4(r6)
lwz r23, 0x01bc(r6)
lwz r24, 0x01c4(r6)
lwz r25, 0x01cc(r6)
lwz r26, 0x01d4(r6)
lwz r27, 0x01dc(r6)
lwz r28, 0x01e4(r6)
lwz r29, 0x01ec(r6)
lwz r30, 0x01f4(r6)
lwz r31, 0x01fc(r6)
andi. r8, r11, 0x2000
beq- major_0x09e28_0x4a8
mfmsr r8
ori r8, r8, 0x2000
mtmsr r8
isync
lfd f31, 0x00e0(r6)
lfd f0, 0x0200(r6)
lfd f1, 0x0208(r6)
lfd f2, 0x0210(r6)
lfd f3, 0x0218(r6)
lfd f4, 0x0220(r6)
lfd f5, 0x0228(r6)
lfd f6, 0x0230(r6)
lfd f7, 0x0238(r6)
lfd f8, 0x0240(r6)
mtfsf 0xff, f31
lfd f9, 0x0248(r6)
lfd f10, 0x0250(r6)
lfd f11, 0x0258(r6)
lfd f12, 0x0260(r6)
lfd f13, 0x0268(r6)
lfd f14, 0x0270(r6)
lfd f15, 0x0278(r6)
lfd f16, 0x0280(r6)
lfd f17, 0x0288(r6)
lfd f18, 0x0290(r6)
lfd f19, 0x0298(r6)
lfd f20, 0x02a0(r6)
lfd f21, 0x02a8(r6)
lfd f22, 0x02b0(r6)
lfd f23, 0x02b8(r6)
lfd f24, 0x02c0(r6)
lfd f25, 0x02c8(r6)
lfd f26, 0x02d0(r6)
lfd f27, 0x02d8(r6)
lfd f28, 0x02e0(r6)
lfd f29, 0x02e8(r6)
lfd f30, 0x02f0(r6)
lfd f31, 0x02f8(r6)
major_0x09e28_0x4a8
lwz r9, 0x0064(r16)
ori r9, r9, 0x8000
ori r9, r9, 0x4000
mtspr hid0, r9
sync
isync
lwz r9, 0x005c(r16)
mtspr tbu, r9
lwz r9, 0x0060(r16)
mtspr tbl, r9
li r9, 0x01
mtspr dec, r9
lwz r9, 0x006c(r16)
mtmsr r9
sync
isync
lwz r9, 0x0070(r16)
mtspr sdr1, r9
lwz r9, 0x0040(r16)
mtsprg 0, r9
lwz r9, 0x0044(r16)
mtsprg 1, r9
lwz r9, 0x0048(r16)
mtsprg 2, r9
lwz r9, 0x004c(r16)
mtsprg 3, r9
lwz r9, 0x0000(r16)
mtspr dbat0u, r9
lwz r9, 0x0004(r16)
mtspr dbat0l, r9
lwz r9, 0x0008(r16)
mtspr dbat1u, r9
lwz r9, 0x000c(r16)
mtspr dbat1l, r9
lwz r9, 0x0010(r16)
mtspr dbat2u, r9
lwz r9, 0x0014(r16)
mtspr dbat2l, r9
lwz r9, 0x0018(r16)
mtspr dbat3u, r9
lwz r9, 0x001c(r16)
mtspr dbat3l, r9
lwz r9, 0x0020(r16)
mtspr ibat0u, r9
lwz r9, 0x0024(r16)
mtspr ibat0l, r9
lwz r9, 0x0028(r16)
mtspr ibat1u, r9
lwz r9, 0x002c(r16)
mtspr ibat1l, r9
lwz r9, 0x0030(r16)
mtspr ibat2u, r9
lwz r9, 0x0034(r16)
mtspr ibat2l, r9
lwz r9, 0x0038(r16)
mtspr ibat3u, r9
lwz r9, 0x003c(r16)
mtspr ibat3l, r9
lwz r16, 0x0184(r6)
li r3, 0x00
b skeleton_key
major_0x09e28_0x59c
mflr r9
stw r9, 0x0074(r16)
stw r1, 0x0078(r16)
addi r9, r16, 0x74
li r0, 0x00
stw r9, 0x0000(0)
lis r9, 0x4c61
ori r9, r9, 0x7273
stw r9, 0x0004(0)
mfspr r9, hid0
andis. r9, r9, 0x20
mtspr hid0, r9
mfmsr r8
oris r8, r8, 0x04
mfspr r9, hid0
ori r9, r9, 0x8000
mtspr hid0, r9
bl * + 4
mflr r9
addi r9, r9, major_0x0a600 - (* - 4)
lisori r1, 0xcafebabe
b major_0x0a500
align 8
; major_0x0a500
; Xrefs:
; major_0x09e28
major_0x0a500 ; OUTSIDE REFERER
sync
mtmsr r8
isync
cmpwi r1, 0x00
beq+ major_0x0a500
lwz r0, 0x0000(r9)
andi. r1, r1, 0x00
b major_0x0a500
align 8
; major_0x0a600
; Xrefs:
; kcPowerDispatch
major_0x0a600 ; OUTSIDE REFERER
dc.l 0
dc.l 0
dc.l 0
dc.l 0
major_0x0a600_0x10 ; OUTSIDE REFERER
mtspr 1019, r5
li r3, 0x00
b skeleton_key
major_0x0a600_0x1c ; OUTSIDE REFERER
b major_0x0a600_0x1c

1268
NanoKernel/NKPrimaryIntHandlers.s Normal file
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72
NanoKernel/NKProcFlagsTbl.s Normal file
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; Contains the table used by Init.s:SetProcessorFlags, and a label to find it with.
;
; Using this table, three fields in KDP are set:
; KDP.CpuSpecificByte1
; KDP.CpuSpecificByte2 (immediately follows Byte1)
; KDP.ProcessorInfo.ProcessorFlags
ProcessorFlagsTable
dcb.b 32 * (1 + 1 + 4), 0
ProcessorFlagsTableEnd
PflgTblCtr set 0
macro
PflgTblEnt &CpuSpecificByte1, &CpuSpecificByte2, &ProcessorFlags
@fb
org ProcessorFlagsTable + PflgTblCtr
dc.b &CpuSpecificByte1
org ProcessorFlagsTable + 32 + PflgTblCtr
dc.b &CpuSpecificByte2
org ProcessorFlagsTable + 64 + 4*PflgTblCtr
dc.l &ProcessorFlags
org @fb
PflgTblCtr set PflgTblCtr + 1
endm
with NKProcessorInfo
; CpuSpecificByte
; 1 2 ProcessorFlags CPU
; ---- - ------------------------------------------------------------------------ -----------------------
PflgTblEnt 0x03, 1, 0 ; 0**0
PflgTblEnt 0x00, 0, 0 ; 0**1 = 601
PflgTblEnt 0x03, 1, 0 ; 0**2
PflgTblEnt 0x1b, 2, 0 ; 0**3 = 603
PflgTblEnt 0x0a, 1, 0 ; 0**4 = 604
PflgTblEnt 0x1b, 2, 0 ; 0**5
PflgTblEnt 0x1b, 2, 0 ; 0**6 = 603e
PflgTblEnt 0x1b, 2, 0 ; 0**7 = 750FX
PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU ; 0**8 = 750
PflgTblEnt 0x0a, 1, 0 ; 0**9
PflgTblEnt 0x0a, 1, 0 ; 0**a
PflgTblEnt 0x03, 1, 0 ; 0**b
PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 0**c = 7400
PflgTblEnt 0x0b, 2, 0 ; 0**d
PflgTblEnt 0x03, 2, 0 ; 0**e
PflgTblEnt 0x03, 2, 0 ; 0**f
PflgTblEnt 0x03, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 8**0 = 7450
PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 8**1 = 7445/55
PflgTblEnt 0x03, 2, 0 ; 8**2 = 7447 (OS X only)
PflgTblEnt 0x03, 2, 0 ; 8**3
PflgTblEnt 0x03, 1, 0 ; 8**4
PflgTblEnt 0x03, 2, 0 ; 8**5
PflgTblEnt 0x03, 2, 0 ; 8**6
PflgTblEnt 0x03, 2, 0 ; 8**7
PflgTblEnt 0x03, 2, 0 ; 8**8
PflgTblEnt 0x03, 2, 0 ; 8**9
PflgTblEnt 0x03, 2, 0 ; 8**a
PflgTblEnt 0x03, 2, 0 ; 8**b
PflgTblEnt 0x1b, 2, 1<< hasL2CR | 1<< hasPLRUL1 | 1<< hasTAU | 1<< hasVMX | 1<< unknownFlag ; 8**c = 7410
PflgTblEnt 0x03, 2, 0 ; 8**d
PflgTblEnt 0x03, 2, 0 ; 8**e
PflgTblEnt 0x03, 2, 0 ; 8**f
endwith

52
NanoKernel/NKProcInfoTbl.s Normal file
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; Contains the table used by InitBuiltin.s:OverrideProcessorInfo
;
; If the Trampoline fails to pass in a signed HardwareInfo struct,
; this is our first choice for populating ProcessorInfo.
;
; Also contains a 'function' that will do the populating
; (not very clever), and fall through to the end of the file,
; where we expect to find Init.s:FinishInitBuiltin.
macro ; just to make the table below look nicer...
PnfoTblEnt &a, &b, &c, &d, &e, &f, &g, &h, &i, &j, &k, &l, &m, &n, &o
dc.l &a * 1024, &b * 1024, &c * 1024
dc.w &d, &e, &f, &g, &h, &i, &j, &k, &l, &m, &n, &o
endm
ProcessorInfoTable
; - PageSize, KB
; | - DataCacheTotalSize, KB
; | | - InstCacheTotalSize, KB
; | | | - CoherencyBlockSize
; | | | | - ReservationGranuleSize
; | | | | | - CombinedCaches
; | | | | | | - InstCacheLineSize
; | | | | | | | - DataCacheLineSize
; | | | | | | | | - DataCacheBlockSizeTouch
; | | | | | | | | | - InstCacheBlockSize
; | | | | | | | | | | - DataCacheBlockSize
; | | | | | | | | | | | - InstCacheAssociativity
; | | | | | | | | | | | | - DataCacheAssociativity
; | | | | | | | | | | | | | - TransCacheTotalSize
; | | | | | | | | | | | | | | - TransCacheAssociativity
PnfoTblEnt 4, 32, 32, 32, 32, 1, 64, 64, 32, 32, 32, 8, 8, 256, 2 ; 0001 = 601
PnfoTblEnt 4, 8, 8, 32, 32, 0, 32, 32, 32, 32, 32, 2, 2, 64, 2 ; 0003 = 603
PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 128, 2 ; 0004 = 604
PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 64, 2 ; 0006 = 603e
PnfoTblEnt 4, 16, 16, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 64, 2 ; 0007 = 750FX
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 128, 2 ; 0008 = 750
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 4, 4, 128, 2 ; 0009/a = ???
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 128, 2 ; 000c = 7400
PnfoTblEnt 4, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 8, 8, 256, 4 ; 000d = ???
OverrideProcessorInfo
@loop
subic. r9, r9, 4
lwzx r12, r11, r9
stwx r12, r10, r9
bgt+ @loop

2526
NanoKernel/NKQueues.s Normal file
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190
NanoKernel/NKRTASCalls.s Normal file
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@ -0,0 +1,190 @@
Local_Panic set *
b panic
; kcRTASDispatch
; Only major that hits the RTAS globals.
; RTAS requires some specific context stuff.
; Xrefs:
; "sup"
; > r1 = kdp
; > r6 = some kind of place
; > r7 = some kind of flags
align 5
kcRTASDispatch ; OUTSIDE REFERER
lwz r8, 0x0908(r1)
cmpwi r8, 0x00
bne- rtas_is_available
li r3, -0x01
b skeleton_key
rtas_is_available
_Lock PSA.RTASLock, scratch1=r8, scratch2=r9
mtcrf 0x3f, r7
lwz r9, 0x0658(r1)
lwz r8, -0x000c(r1)
stw r7, 0x0000(r6)
stw r8, 0x0004(r6)
bns- cr6, kcRTASDispatch_0x5c
stw r17, 0x0024(r6)
stw r20, 0x0028(r6)
stw r21, 0x002c(r6)
stw r19, 0x0034(r6)
stw r18, 0x003c(r6)
lmw r14, 0x0038(r1)
kcRTASDispatch_0x5c
mfxer r8
stw r13, 0x00dc(r6)
stw r8, 0x00d4(r6)
stw r12, 0x00ec(r6)
mfctr r8
stw r10, 0x00fc(r6)
stw r8, 0x00f4(r6)
ble- cr3, kcRTASDispatch_0x8c
lwz r8, 0x00c4(r9)
mfspr r12, mq
mtspr mq, r8
stw r12, 0x00c4(r6)
kcRTASDispatch_0x8c
lwz r8, 0x0004(r1)
stw r8, 0x010c(r6)
stw r2, 0x0114(r6)
stw r3, 0x011c(r6)
stw r4, 0x0124(r6)
lwz r8, 0x0018(r1)
stw r5, 0x012c(r6)
stw r8, 0x0134(r6)
andi. r8, r11, 0x2000
stw r14, 0x0174(r6)
stw r15, 0x017c(r6)
stw r16, 0x0184(r6)
stw r17, 0x018c(r6)
stw r18, 0x0194(r6)
stw r19, 0x019c(r6)
stw r20, 0x01a4(r6)
stw r21, 0x01ac(r6)
stw r22, 0x01b4(r6)
stw r23, 0x01bc(r6)
stw r24, 0x01c4(r6)
stw r25, 0x01cc(r6)
stw r26, 0x01d4(r6)
stw r27, 0x01dc(r6)
stw r28, 0x01e4(r6)
stw r29, 0x01ec(r6)
stw r30, 0x01f4(r6)
stw r31, 0x01fc(r6)
bnel+ major_0x03e18_0xb4
stw r11, 0x00a4(r6)
mr r27, r3
addi r29, r1, 800
bl PagingFunc3
beql+ Local_Panic
rlwimi r3, r31, 0, 0, 19
lhz r8, 0x0004(r3)
cmpwi r8, 0x00
beq- kcRTASDispatch_0x14c
slwi r8, r8, 2
lwzx r27, r8, r3
addi r29, r1, 800
bl PagingFunc3
beql+ Local_Panic
lwzx r9, r8, r3
rlwimi r9, r31, 0, 0, 19
stwx r9, r8, r3
li r9, 0x00
sth r9, 0x0004(r3)
dcbf r8, r3
kcRTASDispatch_0x14c
li r9, 0x04
dcbf r9, r3
sync
isync
lwz r4, 0x090c(r1)
mfmsr r8
andi. r8, r8, 0x10cf
mtmsr r8
isync
mr r28, r3
lwz r9, 0x0908(r1)
bl rtas_make_actual_call
mfsprg r1, 0
lwz r6, -0x0014(r1)
clrlwi r29, r28, 0x14
subfic r29, r29, 0x1000
lhz r27, 0x0f4a(r1)
kcRTASDispatch_0x190
subf. r29, r27, r29
dcbf r29, r28
sync
icbi r29, r28
bge+ kcRTASDispatch_0x190
sync
isync
lwz r8, 0x0000(r6)
lwz r11, 0x00a4(r6)
mr r7, r8
andi. r8, r11, 0x900
lwz r8, 0x0004(r6)
lwz r13, 0x00dc(r6)
stw r8, -0x000c(r1)
lwz r8, 0x00d4(r6)
lwz r12, 0x00ec(r6)
mtxer r8
lwz r8, 0x00f4(r6)
lwz r10, 0x00fc(r6)
mtctr r8
bnel+ major_0x03e18_0x8
lwz r8, 0x010c(r6)
stw r8, 0x0004(r1)
lwz r2, 0x0114(r6)
lwz r3, 0x011c(r6)
lwz r4, 0x0124(r6)
lwz r8, 0x0134(r6)
lwz r5, 0x012c(r6)
stw r8, 0x0018(r1)
lwz r14, 0x0174(r6)
lwz r15, 0x017c(r6)
lwz r16, 0x0184(r6)
lwz r17, 0x018c(r6)
lwz r18, 0x0194(r6)
lwz r19, 0x019c(r6)
lwz r20, 0x01a4(r6)
lwz r21, 0x01ac(r6)
lwz r22, 0x01b4(r6)
lwz r23, 0x01bc(r6)
lwz r24, 0x01c4(r6)
lwz r25, 0x01cc(r6)
lwz r26, 0x01d4(r6)
lwz r27, 0x01dc(r6)
lwz r28, 0x01e4(r6)
lwz r29, 0x01ec(r6)
lwz r30, 0x01f4(r6)
lwz r31, 0x01fc(r6)
sync
lwz r8, -0x0b10(r1)
cmpwi cr1, r8, 0x00
li r8, 0x00
bne+ cr1, kcRTASDispatch_0x268
mflr r8
bl panic
kcRTASDispatch_0x268
stw r8, -0x0b10(r1)
li r3, 0x00
b skeleton_key
rtas_make_actual_call
mtctr r9
bctr

480
NanoKernel/NKReplacementInit.s Normal file
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; sprg0 = old KDP/EWA/r1 ptr
; r3 = PA_NanoKernelCode
; r4 = physical base of our global area
; r5 = NoIdeaR23
; r6 = PA_EDP or zero?
; r7 = probably ROMHeader.ROMRelease ('rom vers', e.g. 0x10B5 is 1.0§5)
InitReplacement
crset cr5_eq
li r0, 0
; Position and initialise the kernel globals, IRP to KDP inclusive.
; (subset of builtin kernel)
; Zero from IRP (r4) to KDP (r4 + 10 pages)
lisori r12, kKDPfromIRP
mr r13, r4
@wipeloop
subic. r12, r12, 4
stwx r0, r13, r12
bgt+ @wipeloop
; Copy the old KDP to r4 + 10 pages.
; (r1 becomes our main ptr and r4 is discarded)
mfsprg r11, 0
lisori r1, kKDPfromIRP
add r1, r1, r4
li r12, 4096
@kdp_copyloop
subic. r12, r12, 4
lwzx r10, r11, r12
stwx r10, r1, r12
bgt+ @kdp_copyloop
; IRP goes at the base of the area we were given.
; Fill with repeating pattern and point EWA at it.
lisori r12, -kKDPfromIRP
add r12, r12, r1
stw r12, EWA.PA_IRP(r1)
bl InitIRP ; clobbers r10 and r12
; Play with some of the other values we were given
; Leave ROMRelease in r23.
mr r23, r7
; If no EDP (Emulator Data Page) pointer was provided,
; then put the EDP above our new KDP.
cmpwi r6, 0
stw r11, KDP.OldKDP(r1)
stw r9, 0x05a4(r1)
; discarded
bne- @emulatordata_ptr_provided
addi r6, r1, 0x1000
@emulatordata_ptr_provided
; Save a few bits
stw r6, 0x05a8(r1)
stw r3, KDP.PA_NanoKernelCode(r1)
stw r5, PSA.NoIdeaR23(r1)
stw r1, EWA.PA_KDP(r1)
addi r12, r1, -0x340 ; get the base of the main CPU struct
li r10, -1
stw r10, CPU.ID(r12)
lwz r3, KDP.PA_ConfigInfo(r1)
bl LookupInterruptHandler
stw r7, KDP.PA_InterruptHandler(r1)
; Clearly changed our mind about where we might be.
bl @x
@x mflr r12
subi r12, r12, @x - NKTop
stw r12, KDP.PA_NanoKernelCode(r1)
; FDP
llabel r10, FDP
add r12, r10, r12
stw r12, KDP.PA_FDP(r1)
; Do something terrible with the CPU features
lwz r12, -0x0010(r1)
li r10, 0x00
rlwimi r10, r12, 0, 12, 15
rlwimi r10, r12, 0, 28, 30
stw r10, -0x0968(r1)
; Cook up a MSR:
; MSR_EE = 1
; MSR_PR = 1
; MSR_FP = 0
; MSR_ME = 0
; MSR_FE0 = 0
; MSR_SE = 0
; MSR_BE = 0
; MSR_FE1 = 0
; MSR_IP = preserved
; MSR_IR = 1
; MSR_DR = 1
; MSR_RI = 0
; MSR_LE = 0
mfmsr r12
andi. r12, r12, 0x0040
ori r12, r12, 0xd032
stw r12, PSA.UserModeMSR(r1)
; Set SPRG0 (for this CPU at least)
mtsprg 0, r1
; r11 still contains the OLD EWA ptr (which is also KDP/PSA ptr?)
lhz r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r11)
cmpwi r12, 0x0101
bgt- @replaces_later_than_0101
;
lwz r12, KDP.PA_ECB_Old(r1)
stw r12, EWA.PA_ContextBlock(r1)
lwz r12, 0x660(r1)
oris r12, r12, 0x20
stw r12, EWA.Flags(r1)
lwz r12, 0x0664(r1)
stw r12, -0x000c(r1) ; boy, better figure out what this is
b @endif
@replaces_later_than_0101
; Obviously cannot replace a v2 NanoKernel like myself
cmpwi r12, 0x0200
bge- CancelReplacement
lwz r12, EWA.PA_ContextBlock(r11)
stw r12, EWA.PA_ContextBlock(r1)
lwz r12, EWA.Flags(r11)
oris r12, r12, 0x20
stw r12, EWA.Flags(r1)
lwz r12, -0x000c(r11)
stw r12, -0x000c(r1)
@endif
lwz r12, 0x0340(r11)
lwz r10, 0x05b4(r11)
cmpw r12, r10
beq- replace_old_kernel_0x198
stw r12, 0x05b4(r1)
stw r0, 0x06b4(r1)
lwz r10, 0x05b0(r11)
stw r10, 0x06c0(r1)
lwz r10, 0x05b4(r11)
stw r10, 0x06c4(r1)
lwz r10, 0x05b8(r11)
stw r10, 0x06c8(r1)
lwz r10, 0x05bc(r11)
stw r10, 0x06cc(r1)
stw r0, 0x06d0(r1)
stw r0, 0x06d4(r1)
stw r0, 0x06d8(r1)
stw r0, 0x06dc(r1)
stw r0, 0x06e0(r1)
stw r0, 0x06e4(r1)
stw r0, 0x06e8(r1)
stw r0, 0x06ec(r1)
stw r0, 0x06f0(r1)
stw r0, 0x06f4(r1)
stw r0, 0x06f8(r1)
stw r0, 0x06fc(r1)
replace_old_kernel_0x198
; Adjust a few KDP pointers to point into the new KDP
lwz r12, KDP.PA_PageMapStart(r1)
subf r12, r11, r12
add r12, r12, r1
stw r12, KDP.PA_PageMapStart(r1)
lwz r12, KDP.PA_PageMapEnd(r1)
subf r12, r11, r12
add r12, r12, r1
stw r12, KDP.PA_PageMapEnd(r1)
lwz r12, 0x05e8(r1)
subf r12, r11, r12
add r12, r12, r1
stw r12, 0x05e8(r1)
; Wipe KDP's NKInfo and ProcessorInfo
li r12, 0x200
addi r10, r1, KDP.NanoKernelInfo
@wipeloop
subic. r12, r12, 4
stwx r0, r10, r12
bgt+ @wipeloop
; r9 = physical base of kernel
li r12, 0
addi r10, r1, KDP.InfoRecord
bl MoveRecord ; (NanoKernelCode, NewKDPInfoRecord, OldKDP, 0)
stw r10, KDP.InfoRecord + InfoRecord.InfoRecordPtr(r1)
stw r0, KDP.InfoRecord + InfoRecord.Zero(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKProcessorStateLen(r1)
addi r10, r1, PSA.ProcessorState
lwz r9, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1)
bl MoveRecord ; (OldProcessorState, NewPSAProcessorState, OldKDP, ProcessorStateLen)
stw r10, KDP.InfoRecord + InfoRecord.NKProcessorStatePtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKHWInfoLen(r1)
lwz r10, EWA.PA_IRP(r1)
addi r10, r10, IRP.HWInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1)
bl MoveRecord ; (OldHWInfo, NewIRPHWInfo, OldKDP, HWInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKHWInfoPtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1)
addi r10, r1, KDP.ProcessorInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1)
bl MoveRecord ; (OldProcessorInfo, NewKDPProcessorInfo, OldKDP, ProcessorInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr(r1)
stw r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoPtr2(r1)
lhz r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1)
cmplwi r10, 0x0112
bge- @ProcessorInfo_version_already_current
li r12, 160
li r10, 0x0112
sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen(r1)
sth r12, KDP.InfoRecord + InfoRecord.NKProcessorInfoLen2(r1)
sth r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer(r1)
sth r10, KDP.InfoRecord + InfoRecord.NKProcessorInfoVer2(r1)
@ProcessorInfo_version_already_current
lhz r12, KDP.InfoRecord + InfoRecord.NKDiagInfoLen(r1)
addi r10, r1, PSA.DiagInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1)
bl MoveRecord ; (OldDiagInfo, NewPSADiagInfo, OldKDP, DiagInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKDiagInfoPtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKSystemInfoLen(r1)
lwz r10, EWA.PA_IRP(r1)
addi r10, r10, IRP.SystemInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1)
bl MoveRecord ; (OldSystemInfo, NewIRPSystemInfo, OldKDP, SystemInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKSystemInfoPtr(r1)
lhz r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1)
addi r10, r1, KDP.NanoKernelInfo
lwz r9, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1)
bl MoveRecord ; (OldNanoKernelInfo, NewKDPNanoKernelInfo, OldKDP, NanoKernelInfoLen)
stw r10, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoPtr(r1)
li r12, 0x160
sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoLen(r1)
li r12, kNanoKernelVersion
sth r12, KDP.InfoRecord + InfoRecord.NKNanoKernelInfoVer(r1)
lwz r8, KDP.ProcessorInfo + NKProcessorInfo.DecClockRateHz(r1)
stw r8, PSA.DecClockRateHzCopy(r1)
; Play with ConfigFlags
lwz r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
_bset r8, r8, 31 ; always set bit 31
if &TYPE('NKShowLog') != 'UNDEFINED'
_bset r8, r8, 28 ; see if someone can test this
endif
cmplwi r23, 0x27f3 ; set bit 27 on ROM 2.7f3 or later
blt- @oldrom ; means later than PDM and Cordyceps
_bset r8, r8, 27
@oldrom
stw r8, KDP.NanoKernelInfo + NKNanoKernelInfo.ConfigFlags(r1)
; Say hello.
bl InitScreenConsole
_log 'Hello from the replacement multitasking NanoKernel. Version: '
mr r8, r12
bl printh
_log '^n Old KDP: '
mr r8, r11
bl printw
_log ' new KDP: '
mr r8, r1
bl printw
_log ' new irp: '
lwz r8, EWA.PA_IRP(r1)
mr r8, r8
bl printw
_log 'ROM vers: '
mr r8, r23
bl printh
_log '^n'
; Jump back into the common code path of Init.s
; The Emulator ContextBlock is expected in r6.
lwz r6, KDP.PA_ECB(r1)
b InitHighLevel
; MoveRecord
; Xrefs:
; replace_old_kernel
; r9 = base of kernel???
; Seems to be code to relocate some old structures.
MoveRecord ; OUTSIDE REFERER
; Check whether the old structure is in KDP
;
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_InfoRecord(r22)
subf r9, r22, r9 ; r9 = offset of old address in irp
cmplwi r9, 0x1000
bge- @kdp
add r21, r9, r11 ; r21 = the old address if it had been in KDP instead?
@0x18
; r9 = offset of old structure in old parent page
; r10 = destination
; r12 = length
;
@loop
subic. r12, r12, 4
blt- @exit_loop
lwzx r9, r21, r12
stwx r9, r10, r12
bgt+ @loop
@exit_loop
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_KernelData(r22)
subf r10, r1, r10
lisori r21, -9 * 4096
cmpw r10, r21 ; if dest is nearer than 9 pages below kdp...
blt- @0x50
add r10, r10, r22
blr
@0x50
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_InfoRecord(r22)
lwz r21, EWA.PA_IRP(r1)
add r10, r10, r1
subf r10, r21, r10
add r10, r10, r22
blr
@kdp
add r9, r9, r22
lwz r22, KDP.PA_ConfigInfo(r1)
lwz r22, NKConfigurationInfo.LA_KernelData(r22)
subf r9, r22, r9 ; r9 now equals an offset from old_kdp
add r21, r9, r11 ; r21 = address in new_kdp
b @0x18

2192
NanoKernel/NKScheduler.s Normal file
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1313
NanoKernel/NKScreenConsole.s Normal file
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598
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; Implements two MPCalls that seem to have something to do with COHGs
; Make conditional calls easier
Local_Panic set *
b panic
Local_ReturnParamErrFromMPCall
b ReturnParamErrFromMPCall
Local_ReturnInsufficientResourcesErrFromMPCall
b ReturnMPCallOOM
Local_CommonMPCallReturnPath
b CommonMPCallReturnPath
DeclareMPCall 102, MPCall_102
MPCall_102 ; OUTSIDE REFERER
mfsprg r9, 0
lwz r8, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r9)
lwz r9, CoherenceGroup.ScheduledCpuCount(r8)
cmpwi r9, 1
bgt+ Local_ReturnInsufficientResourcesErrFromMPCall
bl CoherenceFunc
mr r4, r8
mr r5, r9
b ReturnZeroFromMPCall
DeclareMPCall 103, MPCall_103
MPCall_103 ; OUTSIDE REFERER
mfsprg r9, 0
lwz r8, EWA.CPUBase + CPU.CgrpList + LLL.Freeform(r9)
lwz r9, CoherenceGroup.ScheduledCpuCount(r8)
cmpwi r9, 1
bgt+ Local_ReturnInsufficientResourcesErrFromMPCall
clrlwi. r8, r5, 20
bne+ Local_ReturnParamErrFromMPCall
bl CoherenceFunc
cmpw r3, r8
blt+ Local_ReturnParamErrFromMPCall
cmpw r4, r9
blt+ Local_ReturnParamErrFromMPCall
bl PagingFlushTLB
mfsprg r9, 0
mfxer r8
stw r13, 0x00dc(r6)
stw r8, 0x00d4(r6)
stw r12, 0x00ec(r6)
mfctr r8
stw r10, 0x00fc(r6)
stw r8, 0x00f4(r6)
mfpvr r8
rlwinm. r8, r8, 0, 0, 14
bne- @not_601
mfspr r8, mq
stw r8, ContextBlock.MQ(r6)
@not_601
lwz r8, EWA.r1(r9)
stw r8, ContextBlock.r1(r6)
stw r2, ContextBlock.r2(r6)
stw r3, ContextBlock.r3(r6)
andi. r8, r11, MSR_FP
stw r4, ContextBlock.r4(r6)
lwz r8, EWA.r6(r9)
stw r5, ContextBlock.r5(r6)
stw r8, ContextBlock.r6(r6)
bnel+ Save_f0_f31
rlwinm. r8, r7, 0, 12, 12 ; flags
bnel+ Save_v0_v31
lwz r3, ContextBlock.r3(r6)
lwz r4, ContextBlock.r4(r6)
lwz r5, ContextBlock.r5(r6)
stw r11,ContextBlock.MSR(r6)
mr r27, r5
addi r29, r1, 800
bl PagingFunc3
beq+ Local_ReturnInsufficientResourcesErrFromMPCall
rlwimi r27, r31, 0, 0, 19
mr r17, r27
addi r15, r17, 0x34
srwi r3, r3, 12
MPCall_103_0xc8
mr r27, r5
addi r29, r1, 800
bl PagingFunc3
beq+ Local_ReturnInsufficientResourcesErrFromMPCall
rlwimi r27, r31, 0, 0, 19
stwu r27, 0x0004(r15)
addi r3, r3, -0x01
addi r5, r5, 0x1000
cmpwi r3, 0x00
bge+ MPCall_103_0xc8
addi r15, r15, 0x04
subf r15, r17, r15
stw r15, 0x0034(r17)
mfsprg r15, 0
stw r15, 0x0024(r17)
mfsprg r8, 3
stw r8, 0x0028(r17)
MPCall_103_0x10c
mftbu r8
mftb r9, 0x10c
mftbu r16
cmpw r16, r8
bne- MPCall_103_0x10c
stw r8, -0x0278(r15)
stw r9, -0x0274(r15)
mr r29, r17
li r16, 0x06
stw r16, -0x0238(r15)
lhz r16, -0x0116(r15)
stw r16, -0x0234(r15)
li r8, 0x02
; r7 = flags
; r8 = usually 2?
bl SIGP
mr r17, r29
mfsdr1 r8
stw r8, 0x002c(r17)
rlwinm r9, r8, 16, 7, 15
cntlzw r18, r9
li r9, -0x01
srw r9, r9, r18
addi r9, r9, 0x01
stw r9, 0x000c(r17)
rlwinm r8, r8, 0, 0, 15
stw r8, 0x0010(r17)
lis r8, 0x00
ori r8, r8, 0xc000
stw r8, 0x0018(r17)
lis r9, 0x00
ori r9, r9, 0xa000
subf r8, r9, r1
stw r8, 0x001c(r17)
addi r9, r1, 120
lis r31, 0x00
li r14, 0x00
lwz r29, 0x0034(r17)
add r29, r29, r17
MPCall_103_0x1a0
lwzu r30, 0x0008(r9)
MPCall_103_0x1a4
lwz r18, 0x0004(r30)
lhz r15, 0x0000(r30)
andi. r19, r18, 0xe00
lhz r16, 0x0002(r30)
cmplwi r19, 0xc00
bne- MPCall_103_0x1dc
addi r16, r16, 0x01
slwi r16, r16, 2
stw r16, 0x0000(r29)
rlwinm r18, r18, 22, 0, 29
stw r18, 0x0004(r29)
addi r29, r29, 0x0c
addi r14, r14, 0x01
b MPCall_103_0x1fc
MPCall_103_0x1dc
cmpwi r15, 0x00
bne- MPCall_103_0x1fc
cmplwi r16, 0xffff
bne- MPCall_103_0x1fc
addis r31, r31, 0x1000
cmpwi r31, 0x00
bne+ MPCall_103_0x1a0
b MPCall_103_0x204
MPCall_103_0x1fc
addi r30, r30, 0x08
b MPCall_103_0x1a4
MPCall_103_0x204
lwz r16, -0x0aa0(r1)
MPCall_103_0x208
lwz r31, 0x0000(r16)
add r18, r31, r16
lwz r19, 0x0000(r18)
addi r31, r31, 0x18
stw r31, 0x0000(r29)
stw r16, 0x0004(r29)
addi r29, r29, 0x0c
addi r14, r14, 0x01
cmpwi r19, 0x00
beq- MPCall_103_0x238
add r16, r19, r18
b MPCall_103_0x208
MPCall_103_0x238
addi r19, r1, -0x450
lwz r31, -0x0448(r1)
MPCall_103_0x240
cmpw r31, r19
beq- MPCall_103_0x264
li r18, 0x10
stw r18, 0x0000(r29)
stw r31, 0x0004(r29)
addi r29, r29, 0x0c
addi r14, r14, 0x01
lwz r31, 0x0008(r31)
b MPCall_103_0x240
MPCall_103_0x264
stw r14, 0x0030(r17)
lwz r30, 0x0034(r17)
add r30, r30, r17
MPCall_103_0x270
subf r8, r17, r29
stw r8, 0x0008(r30)
lwz r24, 0x0004(r30)
mr r25, r8
lwz r26, 0x0000(r30)
add r29, r29, r26
bl AnotherCoherenceFunc
addi r30, r30, 0x0c
addi r14, r14, -0x01
cmpwi r14, 0x00
bne+ MPCall_103_0x270
subf r8, r17, r29
stw r8, 0x0020(r17)
lwz r24, 0x001c(r17)
mr r25, r8
lwz r26, 0x0018(r17)
add r29, r29, r26
bl AnotherCoherenceFunc
subf r8, r17, r29
stw r8, 0x0014(r17)
lwz r24, 0x0010(r17)
mr r25, r8
lwz r26, 0x000c(r17)
add r29, r29, r26
bl AnotherCoherenceFunc
bl LoadStateRestoreFunc
mflr r9
stw r9, 0x0000(r17)
lwz r8, -0x0900(r1)
stw r8, 0x0008(r17)
li r8, 0x00
stw r8, 0x0004(r17)
mfsprg r15, 0
li r16, 0x11
stw r16, -0x0238(r15)
lhz r16, -0x0116(r15)
stw r16, -0x0234(r15)
li r8, 0x02
; r7 = flags
; r8 = usually 2?
bl SIGP
li r3, 0x00
b Local_CommonMPCallReturnPath
LoadStateRestoreFunc
blrl
mr r17, r3
lwz r24, 0x0014(r17)
lwz r25, 0x0010(r17)
lwz r26, 0x000c(r17)
bl YetAnotherCoherenceFunc
lwz r24, 0x002c(r17)
mtsdr1 r24
lwz r24, 0x0020(r17)
lwz r25, 0x001c(r17)
lwz r26, 0x0018(r17)
bl YetAnotherCoherenceFunc
lwz r14, 0x0030(r17)
lwz r30, 0x0034(r17)
add r30, r30, r17
RestoreKernelState_0x38
lwz r24, 0x0008(r30)
lwz r25, 0x0004(r30)
lwz r26, 0x0000(r30)
bl YetAnotherCoherenceFunc
addi r30, r30, 0x0c
addi r14, r14, -0x01
cmpwi r14, 0x00
bne+ RestoreKernelState_0x38
lwz r16, 0x0024(r17)
mtsprg 0, r16
lwz r8, 0x0028(r17)
mtsprg 3, r8
lwz r1, -0x0004(r16)
lwz r6, -0x0014(r16)
lwz r7, -0x0010(r16)
li r8, -0x01
stw r8, 0x0004(r17)
lwz r8, -0x0278(r16)
lwz r9, -0x0274(r16)
li r16, 0x01
mttb r16
mttbu r8
mttb r9
mtdec r16
_log 'Resuming saved kernel state^n'
lwz r8, 0x00d4(r6)
lwz r13, 0x00dc(r6)
mtxer r8
lwz r12, 0x00ec(r6)
lwz r8, 0x00f4(r6)
lwz r10, 0x00fc(r6)
mtctr r8
lwz r11, 0x00a4(r6)
mfpvr r8
rlwinm. r8, r8, 0, 0, 14
bne- RestoreKernelState_0xf8
lwz r8, 0x00c4(r6)
DIALECT POWER
mtmq r8
DIALECT PowerPC
RestoreKernelState_0xf8
lwz r4, -0x0020(r1)
li r2, 0x01
sth r2, 0x0910(r1)
li r2, -0x01
stw r2, 0x0912(r1)
stw r2, 0x0f90(r4)
xoris r2, r2, 0x100
stw r2, 0x0f8c(r4)
li r2, 0x00
stw r2, 0x0f28(r4)
stw r2, 0x0f2c(r4)
lwz r2, 0x0114(r6)
lwz r4, 0x0124(r6)
lwz r5, 0x012c(r6)
lwz r29, 0x00d8(r6)
cmpwi r29, 0x00
lwz r8, 0x0210(r29)
beq- RestoreKernelState_0x144
mtspr vrsave, r8
RestoreKernelState_0x144
bl PagingFlushTLB
addi r29, r1, 0x5e0
bl PagingFunc2AndAHalf
mfsprg r15, 0
lwz r8, -0x001c(r15)
li r9, 0x00
bl SetAddrSpcRegisters
isync
mfsprg r15, 0
li r16, 0x07
stw r16, -0x0238(r15)
lhz r16, -0x0116(r15)
stw r16, -0x0234(r15)
li r8, 0x02
; r7 = flags
; r8 = usually 2?
bl SIGP
mfsprg r15, 0
li r16, 0x11
stw r16, -0x0238(r15)
lhz r16, -0x0116(r15)
stw r16, -0x0234(r15)
li r8, 0x02
; r7 = flags
; r8 = usually 2?
bl SIGP
li r3, 0x00
b Local_CommonMPCallReturnPath
; Xrefs:
; MPCall_102
; MPCall_103
; AnotherCoherenceFunc
; YetAnotherCoherenceFunc
CoherenceFunc ; OUTSIDE REFERER
li r24, 0x00
mfsdr1 r16
rlwinm r16, r16, 16, 7, 15
cntlzw r17, r16
li r16, -0x01
srw r16, r16, r17
addi r8, r16, 0x01
addi r9, r1, 120
lis r31, 0x00
li r19, 0x00
li r14, 0x00
CoherenceFunc_0x2c
lwzu r17, 0x0008(r9)
CoherenceFunc_0x30
lwz r18, 0x0004(r17)
lhz r15, 0x0000(r17)
andi. r18, r18, 0xe00
lhz r16, 0x0002(r17)
cmplwi r18, 0xc00
bne- CoherenceFunc_0x58
addi r16, r16, 0x01
add r19, r19, r16
addi r14, r14, 0x01
b CoherenceFunc_0x78
CoherenceFunc_0x58
cmpwi r15, 0x00
bne- CoherenceFunc_0x78
cmplwi r16, 0xffff
bne- CoherenceFunc_0x78
addis r31, r31, 0x1000
cmpwi r31, 0x00
bne+ CoherenceFunc_0x2c
b CoherenceFunc_0x80
CoherenceFunc_0x78
addi r17, r17, 0x08
b CoherenceFunc_0x30
CoherenceFunc_0x80
slwi r19, r19, 2
add r8, r8, r19
cmpwi r14, 0x00
beq+ Local_ReturnInsufficientResourcesErrFromMPCall
mulli r9, r14, 0x0c
add r8, r8, r9
add r24, r24, r9
li r9, 0x00
li r14, 0x00
lwz r16, -0x0aa0(r1)
CoherenceFunc_0xa8
lwz r17, 0x0000(r16)
add r18, r17, r16
lwz r19, 0x0000(r18)
add r9, r9, r17
addi r9, r9, 0x18
addi r14, r14, 0x01
cmpwi r19, 0x00
add r16, r19, r18
beq- CoherenceFunc_0xd0
b CoherenceFunc_0xa8
CoherenceFunc_0xd0
addi r16, r1, -0x450
lwz r18, -0x0448(r1)
CoherenceFunc_0xd8
cmpw r18, r16
beq- CoherenceFunc_0xf0
addi r9, r9, 0x10
addi r14, r14, 0x01
lwz r18, 0x0008(r18)
b CoherenceFunc_0xd8
CoherenceFunc_0xf0
add r8, r8, r9
mulli r9, r14, 0x0c
add r8, r8, r9
add r24, r24, r9
lis r9, 0x00
ori r9, r9, 0xc000
add r8, r8, r9
lis r9, 0x00
ori r9, r9, 0x3c
add r8, r8, r9
add r24, r24, r9
srwi r9, r8, 12
slwi r9, r9, 2
addi r9, r9, 0x04
add r8, r8, r9
add r24, r24, r9
mr r9, r24
blr
CoherenceFunc_0x138 ; OUTSIDE REFERER
srwi r23, r28, 12
slwi r23, r23, 2
add r23, r23, r17
lwz r23, 0x0038(r23)
rlwimi r23, r28, 0, 20, 31
blr
; Xrefs:
; MPCall_103
AnotherCoherenceFunc ; OUTSIDE REFERER
cmpwi r26, 0x00
beqlr-
mflr r22
addi r24, r24, -0x01
mr r28, r25
AnotherCoherenceFunc_0x14
bl CoherenceFunc_0x138
clrlwi r25, r23, 0x14
subfic r25, r25, 0x1000
cmplw r25, r26
blt- AnotherCoherenceFunc_0x2c
mr r25, r26
AnotherCoherenceFunc_0x2c
mr r19, r23
mr r20, r25
addi r23, r23, -0x01
mtctr r25
AnotherCoherenceFunc_0x3c
lbzu r27, 0x0001(r24)
stbu r27, 0x0001(r23)
bdnz+ AnotherCoherenceFunc_0x3c
bl YetAnotherCoherenceFunc_0x64
subf r26, r25, r26
add r28, r28, r25
cmpwi r26, 0x00
bne+ AnotherCoherenceFunc_0x14
mtlr r22
blr
; Xrefs:
; RestoreKernelState
; AnotherCoherenceFunc
YetAnotherCoherenceFunc ; OUTSIDE REFERER
cmpwi r26, 0x00
beqlr-
mr r19, r25
mr r20, r26
mflr r22
addi r25, r25, -0x01
mr r28, r24
YetAnotherCoherenceFunc_0x1c
bl CoherenceFunc_0x138
clrlwi r24, r23, 0x14
subfic r24, r24, 0x1000
cmplw r24, r26
blt- YetAnotherCoherenceFunc_0x34
mr r24, r26
YetAnotherCoherenceFunc_0x34
addi r23, r23, -0x01
mtctr r24
YetAnotherCoherenceFunc_0x3c
lbzu r27, 0x0001(r23)
stbu r27, 0x0001(r25)
bdnz+ YetAnotherCoherenceFunc_0x3c
add r28, r28, r24
subf r26, r24, r26
cmpwi r26, 0x00
bne+ YetAnotherCoherenceFunc_0x1c
bl YetAnotherCoherenceFunc_0x64
mtlr r22
blr
YetAnotherCoherenceFunc_0x64 ; OUTSIDE REFERER
sync
isync
lhz r21, 0x0f4a(r1)
addi r15, r21, -0x01
add r20, r19, r20
add r20, r20, r15
neg r15, r21
and r19, r19, r15
and r20, r20, r15
YetAnotherCoherenceFunc_0x88
dcbst 0, r19
sync
icbi 0, r19
add r19, r19, r21
cmpw r19, r20
blt+ YetAnotherCoherenceFunc_0x88
sync
isync
blr

1569
NanoKernel/NKTasks.s Normal file
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1369
NanoKernel/NKThud.s Normal file
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1002
NanoKernel/NKTimers.s Normal file
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4374
NanoKernel/NKTranslation.s Normal file
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1988
NanoKernel/NKVMCalls.s Normal file
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59
NanoKernel/NanoKernel.s Normal file
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@ -0,0 +1,59 @@
include 'MacErrors.a'
include 'InfoRecords.a'
include 'EmulatorPublic.a'
include 'NKPublic.a'
include 'NKOpaque.a'
include 'NKEquates.s'
include 'NKMacros.s'
NKTop
include 'NKInit.s'
align 5
include 'NKInterrupts.s'
align 5
include 'NKPaging.s'
align 5
include 'NKTranslation.s'
align 5
include 'NKVMCalls.s'
align 5
include 'NKPowerCalls.s'
align 5
include 'NKRTASCalls.s'
align 5
include 'NKCacheCalls.s'
; Mostly MP calls:
align 5
include 'NKMPCalls.s'
align 5
include 'NKQueues.s'
align 5
include 'NKTasks.s'
align 5
include 'NKAddressSpaceMPCalls.s'
align 5
include 'NKPoolAllocator.s'
align 5
include 'NKTimers.s'
align 5
include 'NKScheduler.s'
align 5
include 'NKIndex.s'
align 5
include 'NKPrimaryIntHandlers.s'
align 5
include 'NKConsoleLog.s'
align 5
include 'NKSleep.s'
align 5
include 'NKThud.s'
align 5
include 'NKScreenConsole.s'
align 5
include 'NKAdditions.s'
align 5
NKBtm

483
PPCExceptionTable.s Normal file
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@ -0,0 +1,483 @@
HASH1 equ 978
HASH2 equ 979
ICMP equ 981
DCMP equ 977
IMISS equ 980
DMISS equ 976
RPA equ 982
macro
Vanilla &idx
@start
b @jump1
b @jump2
@jump1
; r1 -> SPRG1
; LR -> SPRG2
; targ -> r1
; optr -> LR
mtsprg 1, r1
mflr r1
mtsprg 2, r1
mfsprg r1, 3
lwz r1, &idx(r1)
mtlr r1
blrl
dc.l @start - TableStart
mflr r1
@jump2
mtsprg 1, r1
mfsprg r1, 3
mtsprg 2, r1
mtlr r1
lwz r1, &idx(r1)
dc.l @start - TableStart
blrl
endm
TableStart
; 0000-00ff: For software use only
org 0x0000
mtsprg 1, r1
mfsprg r1, 3
lwz r1, 0x00BC(r1)
mtlr r1
blrl
org 0x0080
dc.l 0x0000D000 ; '....' (invalid instruction)
; 0100-0fff: Architecture-defined exceptions
org 0x0100
b $+0x0008 ; 0x00000108
b $+0x0050 ; 0x00000154
mtsprg 1, r1
mfcr r1
mtsprg 2, r1
mfsrr1 r1
mtcrf 255, r1
bne cr7, RTASFairyDust
mfspr r1, HID0
mtcrf 255, r1
bns cr3, RTASFairyDust
mfsprg r1, 2
mtcrf 255, r1
mflr r1
mtsprg 2, r1
mfsprg r1, 3
lwz r1, 0x0004(r1)
mtlr r1
blrl
dc.l 0x00000100 ; '....' (invalid instruction)
org 0x180
PerfMon
mtsprg 2, r1
mfsprg r1, 3
stw r2, 0x0000(r1)
mfsprg r2, 2
rlwinm r2, r2, 26, 24, 29
lwzx r1, r2, r1
mflr r2
mtlr r1
mfsprg r1, 2
mtsprg 2, r2
mfsprg r2, 3
lwz r2, 0x0000(r2)
blr
org 0x0200 ; Machine Check
Vanilla 0x0008
org 0x0300 ; Data Storage
Vanilla 0x000C
org 0x0400 ; Instruction Storage
Vanilla 0x0010
org 0x0500 ; External
Vanilla 0x0014
org 0x0600 ; Alignment
Vanilla 0x0018
org 0x0700 ; Program
Vanilla 0x001C
org 0x0800 ; FP Unavailable
Vanilla 0x0020
org 0x0900 ; Decrementer
Vanilla 0x0024
org 0x0A00
Vanilla 0x0028
org 0x0B00
Vanilla 0x002C
org 0x0C00 ; System Call
Vanilla 0x0030
org 0x0D00 ; Trace
Vanilla 0x0034
org 0x0E00
Vanilla 0x0038
; Performance monitor???
org 0x0F00
mtsprg 1, r1
li r1, 0xF00
b PerfMon
org 0x0F20
mtsprg 1, r1
li r1, 0xF20
b PerfMon
; 1000-2fff: Implementation-specific exceptions
org 0x1000
mfspr r2, HASH1
lwz r1, 0x0000(r2)
mfctr r0
mfspr r3, ICMP
cmpw r1, r3
beq $+0x001C ; 0x00001030
li r1, 7
mtctr r1
lwzu r1, 0x0008(r2)
cmpw r1, r3
bdnzf cr0_EQ, $-0x0008 ; 0x00001020
bne $+0x0038 ; 0x00001064
lwz r1, 0x0004(r2)
mtctr r0
andi. r3, r1, 0x0008
bne $+0x006C ; 0x000010A8
mfspr r0, IMISS
mfsrr1 r3
mtcrf 128, r3
mtspr RPA, r1
ori r1, r1, 0x0100
srwi r1, r1, 8
dc.l 0x7C0007E4 ; '|...' (invalid instruction)
stb r1, 0x0006(r2)
rfi
andi. r1, r3, 0x0040
bne $+0x0014 ; 0x0000107C
mfspr r2, HASH2
lwz r1, 0x0000(r2)
ori r3, r3, 0x0040
b $-0x0068 ; 0x00001010
mfsrr1 r3
clrlwi r2, r3, 16
oris r2, r2, 0x4000
mtctr r0
mtsrr1 r2
mfmsr r0
xoris r0, r0, 0x0002
mtcrf 128, r3
mtmsr r0
isync
b $-0x0CA4 ; 0x00000400
mfsrr1 r3
clrlwi r2, r3, 16
oris r2, r2, 0x1000
b $-0x0028 ; 0x0000108C
org 0x1100
mfspr r2, HASH1
lwz r1, 0x0000(r2)
mfctr r0
mfspr r3, DCMP
cmpw r1, r3
beq $+0x001C ; 0x00001130
li r1, 7
mtctr r1
lwzu r1, 0x0008(r2)
cmpw r1, r3
bdnzf cr0_EQ, $-0x0008 ; 0x00001120
bne $+0x0034 ; 0x00001160
lwz r1, 0x0004(r2)
mtctr r0
mfspr r0, DMISS
mfsrr1 r3
mtcrf 128, r3
mtspr RPA, r1
ori r1, r1, 0x0100
srwi r1, r1, 8
dc.l 0x7C0007A4 ; '|...' (invalid instruction)
stb r1, 0x0006(r2)
rfi
nop
andi. r1, r3, 0x0040
bne $+0x013C ; 0x000012A0
mfspr r2, HASH2
lwz r1, 0x0000(r2)
ori r3, r3, 0x0040
b $-0x0064 ; 0x00001110
org 0x1200
mfspr r2, HASH1
lwz r1, 0x0000(r2)
mfctr r0
mfspr r3, DCMP
cmpw r1, r3
beq $+0x001C ; 0x00001230
li r1, 7
mtctr r1
lwzu r1, 0x0008(r2)
cmpw r1, r3
bdnzf cr0_EQ, $-0x0008 ; 0x00001220
bne $+0x003C ; 0x00001268
lwz r1, 0x0004(r2)
mtctr r0
slwi. r3, r1, 30
bge $+0x0044 ; 0x00001280
andi. r3, r1, 0x0001
bne $+0x0054 ; 0x00001298
mfspr r0, DMISS
mfsrr1 r3
mtcrf 128, r3
ori r1, r1, 0x0180
mtspr RPA, r1
dc.l 0x7C0007A4 ; '|...' (invalid instruction)
sth r1, 0x0006(r2)
rfi
andi. r1, r3, 0x0040
bne $+0x0034 ; 0x000012A0
mfspr r2, HASH2
lwz r1, 0x0000(r2)
ori r3, r3, 0x0040
b $-0x006C ; 0x00001210
mfsrr1 r0
extrwi r0, r0, 1, 17
mfspr r3, DMISS
mfsrin r3, r3
rlwnm. r3, r3, r0, 1, 1
beq $-0x004C ; 0x00001248
lis r1, 2048
b $+0x000C ; 0x000012A8
lis r1, 16384
mtctr r0
mfsrr1 r3
rlwimi r1, r3, 9, 6, 6
clrlwi r2, r3, 16
mtsrr1 r2
mtdsisr r1
mfspr r1, DMISS
andi. r2, r2, 0x0001
beq+ $+0x0008 ; 0x000012CC
xori r1, r1, 0x0007
mtdar r1
mfmsr r0
xoris r0, r0, 0x0002
mtcrf 128, r3
mtmsr r0
isync
b $-0x0FE4 ; 0x00000300
org 0x1300
Vanilla 0x004C
org 0x1400
Vanilla 0x0050
org 0x1500
Vanilla 0x0054
org 0x1600
Vanilla 0x0058
org 0x1700
Vanilla 0x005C
org 0x1800
Vanilla 0x0060
org 0x1900
Vanilla 0x0064
org 0x1A00
Vanilla 0x0068
org 0x1B00
Vanilla 0x006C
org 0x1C00
Vanilla 0x0070
org 0x1D00
Vanilla 0x0074
org 0x1E00
Vanilla 0x0078
org 0x1F00
Vanilla 0x007C
org 0x2000
Vanilla 0x0080
org 0x2100
Vanilla 0x0084
org 0x2200
Vanilla 0x0088
org 0x2300
Vanilla 0x008C
org 0x2400
Vanilla 0x0090
org 0x2500
Vanilla 0x0094
org 0x2600
Vanilla 0x0098
org 0x2700
Vanilla 0x009C
org 0x2800
Vanilla 0x00A0
org 0x2900
Vanilla 0x00A4
org 0x2A00
Vanilla 0x00A8
org 0x2B00
Vanilla 0x00AC
org 0x2C00
Vanilla 0x00B0
org 0x2D00
Vanilla 0x00B4
org 0x2E00
Vanilla 0x00B8
org 0x2F00
Vanilla 0x00BC
; Outside the exception table, but called by it:
org 0x3000
RTASFairyDust
mr r21,r3
li r0,0
lwz r5, 0(r21)
lwz r4, 4(r21)
lwz r9, 12(r21)
lwz r3, 12(r9)
lwz r6, 8(r21)
lwz r8, 16(r21)
lwz r22,24(r21)
lwz r23,28(r21)
bl @clrbats
lis r7, 'RT'
ori r7,r7,'AS'
; Soo, we jump to *(arg + 24) the ugly way
mtlr r22
blr
@clrbats
mtdbatl 0,r0
mtdbatu 0,r0
mtdbatl 1,r0
mtdbatu 1,r0
mtdbatl 2,r0
mtdbatu 2,r0
mtdbatl 3,r0
mtdbatu 3,r0
mtibatl 0,r0
mtibatu 0,r0
mtibatl 1,r0
mtibatu 1,r0
mtibatl 2,r0
mtibatu 2,r0
mtibatl 3,r0
mtibatu 3,r0
isync
blr

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The PowerPC ROM for NewWorld Macs
=================================
This repo is part of the *CDG5* project. It builds a 4 MB PowerPC Mac ROM by appending PowerPC code to a 68k Mac ROM (either the included dump, [or one that you built yourself](https://github.com/elliotnunn/mac-rom)). The build result is a byte-perfect copy of the ROM inside the final "Mac OS ROM" release.
Fixing line endings
-------------------
MPW requires old-style Mac line endings (CR), while Git works better with Unix line endings (LF). Git filters can be used to convert between the two. Files committed to the repo are "cleaned" (LF-ed), and then "smudged" (CR-ed) when they hit the working tree. After cloning, append these snippets to your Git config.
Append this to `.git/config`:
[filter "maclines"]
clean = LC_CTYPE=C tr \\\\r \\\\n
smudge = LC_CTYPE=C tr \\\\n \\\\r
Append this to `.git/info/attributes`:
* filter=maclines
*.* -filter
*.s filter=maclines
*.a filter=maclines
*.c filter=maclines
*.h filter=maclines
Finally, do a once-off "re-smudge":
rm -rf ../powermac-rom/*
git checkout .
Setting type and creator codes
------------------------------
Some MPW Tools require their input files to have the correct Mac OS file type, but Git does not save Mac OS type and creator codes. This shell script will give enough files a "TEXT" type to keep MPW happy.
sh SetFileTypes.sh
Building
--------
This code is built with the [Macintosh Programmer's Workshop](https://en.wikipedia.org/wiki/Macintosh_Programmer%27s_Workshop) (MPW), which runs on the Classic Mac OS. To satisfy the memory requirements of the build process, the MPW Shell should get a memory partition of at least 16 MB. Once you have MPW set up, the build process is not particularly fussy.
Not many computers run the Classic Mac OS any more. Here are a few workarounds:
* Just find a Mac running Mac OS 7.5-9.2. (Not much fun if it's also your test machine.)
* Use the Classic environment on a PowerPC Mac running Mac OS X 10.4 or earlier. (A small PowerBook or iBook is perfect.)
* Use [EMPW](https://github.com/elliotnunn/empw) ("Emulated MPW"), a package of command-line tools, emulators and OS images that lets you run MPW commands straight from your macOS Terminal. This is my preferred solution.
Once MPW is set up, the build command is:
EasyBuild
Using EMPW, that's:
empw -b EasyBuild
The 4 MB image will be at `BuildResults/PowerROM`.
What's next?
------------
On NewWorld Macs, this image is extracted into RAM from a "Mac OS ROM" file at boot. Use https://github.com/elliotnunn/newworld-rom to build such a file.

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#!/bin/sh
cd "`dirname "$0"`" && find . -type f -not -path '*/.*' -not -ipath './BuildResults/*' \( -not -name '*.*' -o -iname '*.s' -o -iname '*.a' -o -iname '*.c' -o -iname '*.h' \) -exec SetFile -t 'TEXT' -c 'MPS ' {} \;