mirror of
https://github.com/elliotnunn/powermac-rom.git
synced 2024-12-11 14:49:35 +00:00
126 lines
2.5 KiB
Plaintext
126 lines
2.5 KiB
Plaintext
EDP record 0,INCR
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org 0x70
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IplValue ds.w 1 ; 070 ; 68k int level or -1
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org 0x100
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ContextBlock ds.b 768 ; 100:300 ; Emulator Context Block, ECB; NKv2 ties this to blue task
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org 0xf00
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BootstrapVersion ds.b 16 ; f00:f10 ; Bootstrap loader version info, from ConfigInfo
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endr
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; Lives in EDP. Keeping a separate record to EDP makes the code nicer.
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; Gets called the "system context"
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ContextBlock record 0,INCR
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EmpiricalCpuFeatures ds.l 1 ; 000 ; (SPAC) copied from kdp by CreateTask
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org 0x5c
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LA_EmulatorKernelTrapTable ds.l 1
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org 0x84
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LA_EmulatorEntry ds.l 1 ; 084 ; Entry pt of emulator; set by NK Init.s
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org 0x94
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LA_EmulatorData ds.l 1
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org 0x9c
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LA_DispatchTable ds.l 1
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org 0xa4
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MSR ds.l 1 ; 0a4 ; (SPAC) copied from kdp by CreateTask
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org 0xc4
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MQ ds.l 1 ; 0c4 ; 601 only
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ds.l 1
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PriorityShifty ds.l 1 ; 0cc ; if low nybble is empty, InitRDYQs sets this to 2
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org 0xd4
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XER ds.l 1
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VectorSaveArea ds.l 1 ; 0d8 ; AltiVec hack: vector registers don't fit in CB!
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org 0xe0
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PageInSystemHeap ds.l 1 ; 0e0 ; these are set by StartInit.a:FiddleWithEmulator
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OtherPageInSystemHeap ds.l 1 ; 0e4
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FE000000 ds.l 1 ; 0e8
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Zero ds.l 1 ; 0ec
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org 0xfc
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CodePtr ds.l 1 ; 0fc ; probably goes in SRR0?
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org 0x100
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ds.l 1
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r0 ds.l 1 ; 104
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ds.l 1
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r1 ds.l 1 ; 10c
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ds.l 1
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r2 ds.l 1 ; 114
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ds.l 1
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r3 ds.l 1 ; 11c
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ds.l 1
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r4 ds.l 1 ; 124
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ds.l 1
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r5 ds.l 1 ; 12c
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ds.l 1
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r6 ds.l 1 ; 134
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ds.l 1
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r7 ds.l 1 ; 13c
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ds.l 1
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r8 ds.l 1 ; 144
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ds.l 1
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r9 ds.l 1 ; 14c
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ds.l 1
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r10 ds.l 1 ; 154
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ds.l 1
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r11 ds.l 1 ; 15c
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ds.l 1
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r12 ds.l 1 ; 164
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ds.l 1
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r13 ds.l 1 ; 16c
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ds.l 1
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r14 ds.l 1 ; 174
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ds.l 1
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r15 ds.l 1 ; 17c
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ds.l 1
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r16 ds.l 1 ; 184
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ds.l 1
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r17 ds.l 1 ; 18c
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ds.l 1
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r18 ds.l 1 ; 194
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ds.l 1
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r19 ds.l 1 ; 19c
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ds.l 1
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r20 ds.l 1 ; 1a4
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ds.l 1
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r21 ds.l 1 ; 1ac
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ds.l 1
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r22 ds.l 1 ; 1b4
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ds.l 1
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r23 ds.l 1 ; 1bc
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ds.l 1
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r24 ds.l 1 ; 1c4
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ds.l 1
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r25 ds.l 1 ; 1cc
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ds.l 1
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r26 ds.l 1 ; 1d4
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ds.l 1
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r27 ds.l 1 ; 1dc
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ds.l 1
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r28 ds.l 1 ; 1e4
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ds.l 1
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r29 ds.l 1 ; 1ec
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ds.l 1
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r30 ds.l 1 ; 1f4
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ds.l 1
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r31 ds.l 1 ; 1fc
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FloatRegisters ds.d 32 ; 200:300
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endr
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