mirror of
https://github.com/elliotnunn/supermario.git
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261 lines
10 KiB
Plaintext
261 lines
10 KiB
Plaintext
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; File: SCSIMgrInitPSC.a
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;
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; Contains: SCSI Manager 53c96 initialization routines
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;
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; Written by: Jonathan Abilay/Paul Wolf
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;
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; Copyright: © 1990-1992 by Apple Computer, Inc. All rights reserved.
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;
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; Change History (most recent first):
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;
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; <SM2> 11/3/92 SWC Changed SCSIEqu.a->SCSI.a.
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; <1> 6/2/92 kc first checked in
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; <SM0> 6/01/92 kc Rolled in from Pandora.
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; <1> 1/17/92 PDW first checked in
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; ———————————————————————————————————————————————————————————————————————————————————————
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; Pre-Pandora ROM comments begin here.
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; ———————————————————————————————————————————————————————————————————————————————————————
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; <2> 8/19/91 SAM (PDW) Reverted to old in/out buserr handler support. Added 'IF
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; forROM' around initialization that is not needed in a linked
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; patch.
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; <1> 8/8/91 SAM (PDW) Checked into Regatta for the first time with lots of
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; changes over the TERROR sources.
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; <0> 8/8/91 SAM Split off from 7.0 GM sources.
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;
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; Pre Regatta split-off change history:
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;
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; <T7> 6/27/91 djw (pdw) Removed all traces of SCSIBusy and FreeHook stuff Added
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; BusErr and CyclePhase jump vector initialization.
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; <T6> 6/14/91 djw (actually PDW) Added jvTransfer initialization (overriding
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; Transfer with Transfer_96).
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; <T5> 6/9/91 BG (actually PDW) Rearranged headers to work more consistently
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; between test INIT and ROM builds. Also added IF around
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; _SetTrapAddress so that the INIT does not patch the trap
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; address.
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; <T4> 3/30/91 BG (actually JMA) Added PostFreeHook_96.
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; <T3> 2/17/91 BG (actually JMA) added SlowComp_96, FastComp_96, DoSCSIBusy_96 &
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; SCSIErr_96
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; <T2> 1/5/91 BG (actually JMA) Added more functionalities.
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; <T1> 12/7/90 JMA Checked into TERROR for the first time.
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;
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;========================================================================== <T3>
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BLANKS ON ; assembler accepts spaces & tabs in operand field
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STRING ASIS ; generate string as specified
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PRINT OFF ; do not send subsequent lines to the listing file
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; don't print includes
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IF (&TYPE('forTestInit') = 'UNDEFINED') THEN
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forTestInit: EQU 0
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ENDIF
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LOAD 'StandardEqu.d' ; from StandardEqu.a and for building ROMs
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INCLUDE 'HardwarePrivateEqu.a' ; <T2>
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INCLUDE 'SCSI.a'
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INCLUDE 'SCSIPriv.a'
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INCLUDE 'UniversalEqu.a' ; for TestFor <T2>
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INCLUDE 'SCSIEqu96.a'
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PRINT ON ; do send subsequent lines to the listing files
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SCSIMgrInitPSC PROC EXPORT ;
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EXPORT InitMgr_SCSI_PSC
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; From SCSIMgr96.a ---
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IMPORT SCSIMgr_PSC
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IMPORT DoSCSICmd_PSC, DoSCSIComplete_PSC
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IMPORT DoSCSISelect_sPSC, DoSCSISelect_dPSC ; <T2>
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IMPORT DoSCSISelAtn_sPSC, DoSCSISelAtn_dPSC, CyclePhase_PSC ; <T9>
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IMPORT DoSCSIStat_PSC, DoSCSIMsgOut_PSC
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IMPORT Unimplemented_PSC
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IMPORT DoSCSIReset_PSC, DoSCSIGet_PSC
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IMPORT DoSCSIMsgIn_PSC
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IMPORT NewSCSIRead_PSC, NewSCSIWrite_PSC
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IMPORT NewSCSIWBlind_PSC, NewSCSIRBlind_PSC
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IMPORT SCSIErr_PSC
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; From SCSIMgrHW96.a ---
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IMPORT BusErrHandler_PSC
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IMPORT ResetBus_PSC, SlowRead_PSC, Transfer_PSC
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IMPORT SlowWrite_PSC, SlowComp_PSC
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IMPORT FastRead_PSC, FastWrite_PSC, FastComp_PSC
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WITH scsiGlobalRecord
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;-------------------------------------------------------------
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;
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; Initialization code for the SCSI Manager 5394/5396
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InitMgr_SCSI_PSC
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movem.l intrRegs, -(sp) ; save all registers, for convenience
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moveq.l #0, zeroReg ; initialize "zeroReg"
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movea.l SCSIGlobals, a4 ; get ptr to structure
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moveq.l #numSelectors-1, d1 ; loop count
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IF forTestInit OR forROM THEN ; if not a linked patch, make addrs relative
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lea.l SCSIMgr_PSC, a1 ; get start of SCSI Mgr code
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move.l a1, d0 ; remember base address
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ELSE
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moveq.l #0, D0 ; if linked patch, make addrs absolute
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ENDIF
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lea OffsetTbl96, a1 ; address of offset table
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movea.l a4, a0 ; point to base of old SCSI Mgr jump table
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@MakeJmpTbl
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move.l (a1)+, d2 ; get the next offset
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beq.s @skipEntry ; if zero, skip this entry
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add.l d0, d2 ; compute the address
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move.l d2, (a0) ; install it in the jump table
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@skipEntry
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adda.l #4, a0
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dbra d1, @MakeJmpTbl ; loop for all vectors
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lea.l Transfer_PSC, a1 ; <T6> <T2>
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move.l a1, jvTransfer(a4) ; use this Transfer routine <T6> <T2>
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lea.l CyclePhase_PSC, a1 ; <T7> pdw
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move.l a1, jvCyclePhase(a4) ; use this CyclePhase routine <T7> pdw
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lea.l ResetBus_PSC, a1
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move.l a1, jvResetBus(a4) ; use this Bus Reset routine
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lea.l BusErrHandler_PSC, a1 ; <T7> pdw
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move.l a1, jvBusErr(a4) ; use this SCSI Bus Error handler <T7> pdw
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move.l #1,blindBusTO(a4) ; initlz blind rd/wr timeout to ≈1mS
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lea.l SlowRead_PSC, a1
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move.l a1, jvVSRO(a4) ; use this Slow Read routine
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lea.l SlowWrite_PSC, a1
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move.l a1, jvVSWO(a4) ; use this Slow Write routine
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lea.l SlowRead_PSC, a1
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; lea.l FastRead_PSC, a1
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move.l a1, jvVFRO(a4) ; use this Fast Read routine
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lea.l SlowWrite_PSC, a1
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; lea.l FastWrite_PSC, a1
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move.l a1, jvVFWO(a4) ; use this Fast Write routine
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lea.l SlowComp_PSC, a1 ; <T3> thru next <T3>
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move.l a1, jvCSO(a4) ; use this Slow Compare routine
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lea.l FastComp_PSC, a1
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move.l a1, jvCFO(a4) ; use this Fast Compare routine
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lea.l SCSIErr_PSC, a1
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move.l a1, jvErr(a4) ; use this Error routine
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lea.l Unimplemented_PSC, a1
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move.l a1, jvClearIRQ(a4) ; use this clear IRQ routine
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move.l a1, jvSel15(a4) ; Selector 15 routine
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move.l a1, jvSel16(a4) ; Selector 16 routine
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move.l a1, jvSel17(a4) ; Selector 17 routine <T3>
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move.l zeroReg, d0 ; disable SCSI interrupts <T2> thru next <T2>
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movea.l jvDisEnable(a4), a0 ; addr of interrupt enable/disable routine
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jsr (a0) ; disable interrupts
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IF forROM AND NOT forTestInit THEN ; <2>
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clr.l G_IntrpStat(a4) ; clear our Intrp Status
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clr.l G_FakeStat(a4) ; clear fake stat
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clr.l G_State96(a4) ; clear our indicators of 53c96 state <T7> pdw
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clr.l G_SCSIDevMap0(a4) ; initialize SCSI Device Map 0
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clr.l G_SCSIDevMap1(a4) ; initialize SCSI Device Map 1
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clr.l base539x1(a4) ; init second SCSI base address
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clr.l G_SCSIDREQ(a4) ; initialize SCSI DREQ regr
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; All this time we've been using a default host ID = 7. Just in case that ever changes <2>
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; load whatever SCSIMgrInit got from PRAM as our host ID.
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move.b G_ID(a4), d1 ; get SCSI host ID mask
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move.b #7, d0 ; load shift count
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@1
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lsl.b #1, d1 ; shift out mask bit until all 0's
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dbeq d0, @1 ; remaining count in d0 will be SCSI ID
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ori.b #initCF1, d0 ; use this our designated SCSI host ID
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move.b d0, rCF1(a3) ; use this new config regr. value, hopefully
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; nobody has changed the setting since HW init time
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move.l SCSIBase, base539x0(a4) ; load addr of first SCSI chip
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move.l #SCSI0_DAFB, pdma5380(a4) ; load addr of DAFB regr containing DREQ bit
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ENDIF ; <2>
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; IF isUniversal THEN
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TestFor SCSI96_2Exists ; do we have a second SCSICyc96 chip?
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beq.s @noSCSICyc96 ;
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@s2Exists
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move.l SCSI2Base, base539x1(a4) ; addr of second SCSI chip
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move.l #SCSI1_DAFB, hhsk5380(a4) ; load addr of DAFB regr containing DREQ bit
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lea.l DoSCSISelect_dPSC, a1 ; point to Dual SCSICyc96 Select proc
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move.l a1, jvSelect(a4) ; use this Select routine
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lea.l DoSCSISelAtn_dPSC, a1 ; point to Dual SCSICyc96 Select/WAtn proc
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move.l a1, jvSelAtn(a4) ; use this Select routine
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@noSCSICyc96 ;
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; ENDIF
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move.b #mgrVersion2, state2(a4) ; save the version number
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@InitDone
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movem.l (sp)+, intrRegs ; restore registers
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rts
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;-------------------------------------------------------------
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;
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Macro
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DispatchVector &ROMAddress
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IF forTestInit OR forROM THEN ;
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dc.l &ROMAddress-SCSIMgr_PSC
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ELSE
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dcImportResident &ROMAddress
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ENDIF
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EndM
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OffsetTbl96
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IF 1 THEN ;\/----\/----\/----\/
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DispatchVector DoSCSIReset_PSC ; 0: SCSIReset
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DispatchVector DoSCSIGet_PSC ; 1: SCSIGet
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DispatchVector DoSCSISelect_sPSC ; 2: SCSISelect <T2>
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DispatchVector DoSCSICmd_PSC ; 3: SCSICmd
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DispatchVector DoSCSIComplete_PSC ; 4: SCSIComplete
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DispatchVector NewSCSIRead_PSC ; 5: SCSIRead
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DispatchVector NewSCSIWrite_PSC ; 6: SCSIWrite
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DispatchVector Unimplemented_PSC ; 7: Was SCSIInstall
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DispatchVector NewSCSIRBlind_PSC ; 8: SCSIRBlind
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DispatchVector NewSCSIWBlind_PSC ; 9: SCSIWBlind
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DispatchVector DoSCSIStat_PSC ; 10: SCSIStat
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DispatchVector DoSCSISelAtn_sPSC ; 11: SCSISelAtn <T2>
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DispatchVector DoSCSIMsgIn_PSC ; 12: SCSIMsgIn
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DispatchVector DoSCSIMsgOut_PSC ; 13: SCSIMsgOut
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ELSE ;/\----/\----/\----/\
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DispatchVector 0 ; 0: SCSIReset
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DispatchVector 0 ; 1: SCSIGet
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DispatchVector DoSCSISelect_sPSC ; 2: SCSISelect <T2>
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DispatchVector DoSCSICmd_PSC ; 3: SCSICmd
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DispatchVector DoSCSIComplete_PSC ; 4: SCSIComplete
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DispatchVector 0 ; 5: SCSIRead
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DispatchVector 0 ; 6: SCSIWrite
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DispatchVector 0 ; 7: Was SCSIInstall
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DispatchVector 0 ; 8: SCSIRBlind
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DispatchVector 0 ; 9: SCSIWBlind
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DispatchVector DoSCSIStat_PSC ; 10: SCSIStat
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DispatchVector DoSCSISelAtn_sPSC ; 11: SCSISelAtn <T2>
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DispatchVector 0 ; 12: SCSIMsgIn
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DispatchVector DoSCSIMsgOut_PSC ; 13: SCSIMsgOut
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ENDIF
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;==========================================================================
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ENDWITH
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END
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