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## Description
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2022-08-22 06:49:18 +00:00
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2023-07-08 19:33:10 +00:00
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BMac aka BigMac is an Ethernet media access controller cell integrated in the
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Heathrow and Paddington I/O controllers.
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According to a former Apple employee, BMac has been licensed from Sun.
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It's therefore not surprising that it has a lot in common with the Sun
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"Happy Meal" (HME) controller.
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2020-03-07 22:40:46 +00:00
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2023-07-08 19:33:10 +00:00
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### BMac based Ethernet HW
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There are three BMac based HW configurations:
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* BMac in a Heathrow I/O + LXT907 PHY used in Power Macintosh G3 (Old World)
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* BMac+ in a Paddington I/O + LXT970 aka ST10040 PHY in Power Macintosh Blue & White (New World)
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* BMac+ in a Paddington I/O + DP83843 PHY in a Bronze Keyboard PowerBook G3
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## Documentation
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No official documentation has surfaced so far. Fortunately, the official source
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code as well as the STP2002 datasheet provide enough information on the BMac device.
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* Apple source code: https://github.com/apple-oss-distributions/AppleBMacEthernet
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* STP2002 datasheet: https://people.freebsd.org/~wpaul/STP2002QFP-UG.pdf
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## Register Map
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BMac registers are located at offset 0x11000 starting from the I/O controller base address.
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| Register Name | Offset | Description |
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|:-------------:|:------:|:---------------------------------------------------:|
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| XIFC | 0x000 | Transceiver interface configuration register |
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| TXFIFOCSR | 0x100 | Transceiver FIFO control & status register |
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| TXTH | 0x110 | Transceiver FIFO treshold |
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| RXFIFOCSR | 0x120 | Receiver FIFO control & status register |
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| MEMADD | 0x130 |
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| XCVRIF | 0x160 |
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| CHIPID | 0x170 | Chip aka Ethernet cell identification register |
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| MIFCSR | 0x180 | Media interface control & status register |
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| SROMCSR | 0x190 | Serial EEPROM control & status register |
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| TXPNTR | 0x1A0 | Transceiver pointer |
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| RXPNTR | 0x1B0 | Receiver pointer |
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| STATUS | 0x200 | Global status register |
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| INTDISABLE | 0x210 | Global interrupt disable register |
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| TXRST | 0x420 | Transceiver software reset |
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| TXCFG | 0x430 | Transceiver configuration register |
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| IPG1 | 0x440 | Interpacket gap 1 register |
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| IPG2 | 0x450 | Interpacket gap 2 register |
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| ALIMIT | 0x460 | Transceiver attempt limit register |
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| SLOT | 0x470 | Transceiver slot time register |
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| PALEN | 0x480 | Transceiver preamble length register |
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| PAPAT | 0x490 | Transceiver preamble pattern register |
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| TXSFD | 0x4A0 | Transceiver start of frame delimiter (SFD) register |
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| JAM | 0x4B0 | Transceiver jam size register |
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| TXMAX | 0x4C0 | Transceiver maximum frame size register |
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| TXMIN | 0x4D0 | Transceiver minimum frame size register |
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| PAREG | 0x4E0 | Transceiver peak attempts register |
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| DCNT | 0x4F0 | Defer timer (counter ?) |
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| NCCNT | 0x500 | Normal collision counter |
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| NTCNT | 0x510 | Network collision counter |
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| EXCNT | 0x520 | Excessive collision counter |
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| LTCNT | 0x530 | Late collision counter |
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| RSEED | 0x540 | Transceiver random number seed register |
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| TXSM | 0x550 | Transceiver state machine register |
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| RXRST | 0x620 | Receiver software reset register |
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| RXCFG | 0x630 | Receiver configuration register |
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| RXMAX | 0x640 | Receiver maximum frame size register |
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| RXMIN | 0x650 | Receiver minimum frame size register |
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| MADD2 | 0x660 | Receiver MAC address 2 register |
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| MADD1 | 0x670 | Receiver MAC address 1 register |
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| MADD0 | 0x680 | Receiver MAC address 0 register |
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| FRCNT | 0x690 | Receiver frame counter register |
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| LECNT | 0x6A0 | Receiver length error counter register |
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| AECNT | 0x6B0 | Receiver alignment error counter register |
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| FECNT | 0x6C0 | Receiver frame check sum error counter register |
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| RXSM | 0x6D0 | Receiver state machine register |
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| RXCV | 0x6E0 | Receiver code violation register |
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| HASH3 | 0x700 | Receiver hash table 3 register |
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| HASH2 | 0x710 | Receiver hash table 2 register |
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| HASH1 | 0x720 | Receiver hash table 1 register |
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| HASH0 | 0x730 | Receiver hash table 0 register |
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| AFR2 | 0x740 | Receiver address filter 2 register |
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| AFR1 | 0x750 | Receiver address filter 1 register |
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| AFR0 | 0x760 | Receiver address filter 0 register |
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| AFCR | 0x770 | Receiver address filter control register |
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