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Documenation Update 3/7/2020
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@ -2,7 +2,7 @@ The ATI Rage is a video card that comes bundled with early Power Mac G3s and New
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# Memory Map
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The ATI Rage can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x9000. However, the video memory appears to be at 0x81000000.
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The ATI Rage can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x9000. However, the video memory appears to be at 0x81000000 and is capped at 8 MB.
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# Register Map
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65
zdocs/bmac.md
Normal file
65
zdocs/bmac.md
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@ -0,0 +1,65 @@
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The BMac is an Ethernet controller featured in G3 and early G4 Macs. As described by a Linux contributor, this controller "appears to have some parts in common with the Sun "Happy Meal" (HME) controller".
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The max frame size is 0x5EE bytes.
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It resides on 0xF3011000, with Writing DMA on 0xF3008200 and Reading DMA on 0xF3008300.
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## Register Map
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| Register Name | Offset |
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|:-------------:|:------:|
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| XIFC | 0x000 |
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| TXFIFOCSR | 0x100 |
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| TXTH | 0x110 |
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| RXFIFOCSR | 0x120 |
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| MEMADD | 0x130 |
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| XCVRIF | 0x160 |
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| CHIPID | 0x170 |
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| MIFCSR | 0x180 |
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| SROMCSR | 0x190 |
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| TXPNTR | 0x1A0 |
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| RXPNTR | 0x1B0 |
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| STATUS | 0x200 |
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| INTDISABLE | 0x210 |
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| TXRST | 0x420 |
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| TXCFG | 0x430 |
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| IPG1 | 0x440 |
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| IPG2 | 0x450 |
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| ALIMIT | 0x460 |
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| SLOT | 0x470 |
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| PALEN | 0x480 |
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| PAPAT | 0x490 |
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| TXSFD | 0x4A0 |
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| JAM | 0x4B0 |
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| TXMAX | 0x4C0 |
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| TXMIN | 0x4D0 |
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| PAREG | 0x4E0 |
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| DCNT | 0x4F0 |
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| NCCNT | 0x500 |
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| NTCNT | 0x510 |
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| EXCNT | 0x520 |
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| LTCNT | 0x530 |
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| RSEED | 0x540 |
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| TXSM | 0x550 |
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| RXRST | 0x620 |
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| RXRST | 0x620 |
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| RXCFG | 0x630 |
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| RXMAX | 0x640 |
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| RXMIN | 0x650 |
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| MADD2 | 0x660 |
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| MADD1 | 0x670 |
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| MADD0 | 0x680 |
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| FRCNT | 0x690 |
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| LECNT | 0x6A0 |
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| AECNT | 0x6B0 |
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| FECNT | 0x6C0 |
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| RXSM | 0x6D0 |
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| RXCV | 0x6E0 |
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| HASH3 | 0x700 |
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| HASH2 | 0x710 |
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| HASH1 | 0x720 |
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| HASH0 | 0x730 |
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| AFR2 | 0x740 |
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| AFR1 | 0x750 |
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| AFR0 | 0x760 |
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| AFCR | 0x770 |
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@ -8,7 +8,15 @@ It also contains the emulations for the VIA Cuda, SWIM 3 floppy drive, ESCC, and
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| Register Name | Offset |
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|:-------------------:|:------:|
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| Base Address 0 | 0x10 |
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| Interrupt Events 2 | 0x10 |
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| Interrupt Mask 2 | 0x14 |
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| Interrupt Clear 2 | 0x18 |
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| Interrupt Levels 2 | 0x1C |
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| Interrupt Events 1 | 0x20 |
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| Interrupt Mask 1 | 0x24 |
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| Interrupt Clear 1 | 0x28 |
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| Interrupt Levels 1 | 0x2C |
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| Chassis Light Color | 0x32 |
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| Media Bay Control | 0x34 |
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| Feature Control | 0x38 |
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| Auxiliary Control | 0x3C |
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@ -2,34 +2,6 @@
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The Old World ROM is always 4 megabytes (MB). The first three MB are reserved for the 68k code, while the last MB is for the PowerPC boot-up code.
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# BMac
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BMac is an Ethernet controller featured in G3 and early G4 Macs. As described by a Linux contributor, this controller "appears to have some parts in common with the Sun "Happy Meal" (HME) controller".
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The max frame size is 0x5EE bytes.
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It resides on 0xF3011000, with Writing DMA on 0xF3008200 and Reading DMA on 0xF3008300.
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## Register Map
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| Register Name | Offset |
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|:-------------:|:------:|
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| XIFC | 0x000 |
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| TXFIFOCSR | 0x100 |
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| TXTH | 0x110 |
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| RXFIFOCSR | 0x120 |
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| MEMADD | 0x130 |
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| XCVRIF | 0x160 |
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| CHIPID | 0x170 |
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| TXPNTR | 0x1A0 |
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| RXPNTR | 0x1B0 |
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| STATUS | 0x200 |
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| INTDISABLE | 0x210 |
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| TXRST | 0x420 |
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| TXCFG | 0x430 |
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| RXRST | 0x620 |
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| RXCFG | 0x630 |
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# Serial
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For serial, it replicates the functionality of a Zilog ESCC. There are two different ports - one located at (MacIOBase) + 0x13000 for the printer, and the other at (MacIOBase) + 0x13020 for the modem.
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@ -81,6 +53,8 @@ The SWIM 3 (Sanders-Wozniak integrated machine 3) is the floppy drive disk contr
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The SWIM chip is resided on the logic board physically and is located at IOBase + 0x15000 in the device tree. It sits between the I/O controller and the floppy disk connector. Its function is to translate the I/O commands to specialized signals to drive the floppy disk drive, i.e. disk spinning speed, head position, phase sync, etc.
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Unlike its predecessor, it allowed some DMA capability.
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The floppy drives themselves were provided by Sony.
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Some New World Macs do have a SWIM 3 driver present, but this normally goes unused due to no floppy drive being connected.
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@ -1,5 +1,9 @@
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OpenFirmware is a standard to defined a firmware's interfaces. It primarily uses the Forth programming language.
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OpenFirmware is a standard to defined a firmware's interfaces. It primarily uses the Forth programming language. It's available on most PCI Power Macs and all New World Power Macs by holding Command, Option, O, and F together during bootup.
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The bootpath for Old World Macs is usually set to "/AAPL,ROM". New World Macs specify "\\:tbxi" as the boot path instead.
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When using an Old World PCI Power Mac, it gets relocated from 0xFF800000 to 0x00400000 during boot-up, then instruction and data translations are enabled.
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There is also a section of NVRAM reserved for boot-up code called "NVRAMRC", ran each time the system is booted up.
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It gets compiled to native PowerPC code during boot-up.
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@ -38,8 +38,22 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
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| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
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| Machine State Register | 1 | |
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# HID 0
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| Model | Bits Enabled |
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| :------------ | :------------------ |
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| 601 | (NOT PRESENT) |
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| 603 | NHR, DOZE/NAP/SLEEP |
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| 604 | NHR |
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| 603E | NHR, DOZE/NAP/SLEEP |
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| 603EV | NHR, DOZE/NAP/SLEEP |
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| 604E | NHR |
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| 750 (G3) | NHR, DOZE/NAP/SLEEP |
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# Eccentricities
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* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.
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* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.
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* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.
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* As the PowerPC does not have an instruction to load an immediate 32-bit value, it's common to see a lis/ori coding pattern.
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