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Documenation Update 3/7/2020

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dingusdev 2020-03-07 15:40:46 -07:00
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2
zdocs/atirage.md
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@ -2,7 +2,7 @@ The ATI Rage is a video card that comes bundled with early Power Mac G3s and New
# Memory Map
The ATI Rage can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x9000. However, the video memory appears to be at 0x81000000.
The ATI Rage can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x9000. However, the video memory appears to be at 0x81000000 and is capped at 8 MB.
# Register Map

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zdocs/bmac.md Normal file
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@ -0,0 +1,65 @@
The BMac is an Ethernet controller featured in G3 and early G4 Macs. As described by a Linux contributor, this controller "appears to have some parts in common with the Sun "Happy Meal" (HME) controller".
The max frame size is 0x5EE bytes.
It resides on 0xF3011000, with Writing DMA on 0xF3008200 and Reading DMA on 0xF3008300.
## Register Map
| Register Name | Offset |
|:-------------:|:------:|
| XIFC | 0x000 |
| TXFIFOCSR | 0x100 |
| TXTH | 0x110 |
| RXFIFOCSR | 0x120 |
| MEMADD | 0x130 |
| XCVRIF | 0x160 |
| CHIPID | 0x170 |
| MIFCSR | 0x180 |
| SROMCSR | 0x190 |
| TXPNTR | 0x1A0 |
| RXPNTR | 0x1B0 |
| STATUS | 0x200 |
| INTDISABLE | 0x210 |
| TXRST | 0x420 |
| TXCFG | 0x430 |
| IPG1 | 0x440 |
| IPG2 | 0x450 |
| ALIMIT | 0x460 |
| SLOT | 0x470 |
| PALEN | 0x480 |
| PAPAT | 0x490 |
| TXSFD | 0x4A0 |
| JAM | 0x4B0 |
| TXMAX | 0x4C0 |
| TXMIN | 0x4D0 |
| PAREG | 0x4E0 |
| DCNT | 0x4F0 |
| NCCNT | 0x500 |
| NTCNT | 0x510 |
| EXCNT | 0x520 |
| LTCNT | 0x530 |
| RSEED | 0x540 |
| TXSM | 0x550 |
| RXRST | 0x620 |
| RXRST | 0x620 |
| RXCFG | 0x630 |
| RXMAX | 0x640 |
| RXMIN | 0x650 |
| MADD2 | 0x660 |
| MADD1 | 0x670 |
| MADD0 | 0x680 |
| FRCNT | 0x690 |
| LECNT | 0x6A0 |
| AECNT | 0x6B0 |
| FECNT | 0x6C0 |
| RXSM | 0x6D0 |
| RXCV | 0x6E0 |
| HASH3 | 0x700 |
| HASH2 | 0x710 |
| HASH1 | 0x720 |
| HASH0 | 0x730 |
| AFR2 | 0x740 |
| AFR1 | 0x750 |
| AFR0 | 0x760 |
| AFCR | 0x770 |

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zdocs/heathrow.md
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@ -8,7 +8,15 @@ It also contains the emulations for the VIA Cuda, SWIM 3 floppy drive, ESCC, and
| Register Name | Offset |
|:-------------------:|:------:|
| Base Address 0 | 0x10 |
| Interrupt Events 2 | 0x10 |
| Interrupt Mask 2 | 0x14 |
| Interrupt Clear 2 | 0x18 |
| Interrupt Levels 2 | 0x1C |
| Interrupt Events 1 | 0x20 |
| Interrupt Mask 1 | 0x24 |
| Interrupt Clear 1 | 0x28 |
| Interrupt Levels 1 | 0x2C |
| Chassis Light Color | 0x32 |
| Media Bay Control | 0x34 |
| Feature Control | 0x38 |
| Auxiliary Control | 0x3C |

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zdocs/misc.md
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@ -2,34 +2,6 @@
The Old World ROM is always 4 megabytes (MB). The first three MB are reserved for the 68k code, while the last MB is for the PowerPC boot-up code.
# BMac
BMac is an Ethernet controller featured in G3 and early G4 Macs. As described by a Linux contributor, this controller "appears to have some parts in common with the Sun "Happy Meal" (HME) controller".
The max frame size is 0x5EE bytes.
It resides on 0xF3011000, with Writing DMA on 0xF3008200 and Reading DMA on 0xF3008300.
## Register Map
| Register Name | Offset |
|:-------------:|:------:|
| XIFC | 0x000 |
| TXFIFOCSR | 0x100 |
| TXTH | 0x110 |
| RXFIFOCSR | 0x120 |
| MEMADD | 0x130 |
| XCVRIF | 0x160 |
| CHIPID | 0x170 |
| TXPNTR | 0x1A0 |
| RXPNTR | 0x1B0 |
| STATUS | 0x200 |
| INTDISABLE | 0x210 |
| TXRST | 0x420 |
| TXCFG | 0x430 |
| RXRST | 0x620 |
| RXCFG | 0x630 |
# Serial
For serial, it replicates the functionality of a Zilog ESCC. There are two different ports - one located at (MacIOBase) + 0x13000 for the printer, and the other at (MacIOBase) + 0x13020 for the modem.
@ -81,6 +53,8 @@ The SWIM 3 (Sanders-Wozniak integrated machine 3) is the floppy drive disk contr
The SWIM chip is resided on the logic board physically and is located at IOBase + 0x15000 in the device tree. It sits between the I/O controller and the floppy disk connector. Its function is to translate the I/O commands to specialized signals to drive the floppy disk drive, i.e. disk spinning speed, head position, phase sync, etc.
Unlike its predecessor, it allowed some DMA capability.
The floppy drives themselves were provided by Sony.
Some New World Macs do have a SWIM 3 driver present, but this normally goes unused due to no floppy drive being connected.

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zdocs/openfirmware.md
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@ -1,5 +1,9 @@
OpenFirmware is a standard to defined a firmware's interfaces. It primarily uses the Forth programming language.
OpenFirmware is a standard to defined a firmware's interfaces. It primarily uses the Forth programming language. It's available on most PCI Power Macs and all New World Power Macs by holding Command, Option, O, and F together during bootup.
The bootpath for Old World Macs is usually set to "/AAPL,ROM". New World Macs specify "\\:tbxi" as the boot path instead.
When using an Old World PCI Power Mac, it gets relocated from 0xFF800000 to 0x00400000 during boot-up, then instruction and data translations are enabled.
There is also a section of NVRAM reserved for boot-up code called "NVRAMRC", ran each time the system is booted up.
It gets compiled to native PowerPC code during boot-up.

16
zdocs/powerpc.md
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@ -38,8 +38,22 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
| Machine State Register | 1 | |
# HID 0
| Model | Bits Enabled |
| :------------ | :------------------ |
| 601 | (NOT PRESENT) |
| 603 | NHR, DOZE/NAP/SLEEP |
| 604 | NHR |
| 603E | NHR, DOZE/NAP/SLEEP |
| 603EV | NHR, DOZE/NAP/SLEEP |
| 604E | NHR |
| 750 (G3) | NHR, DOZE/NAP/SLEEP |
# Eccentricities
* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.
* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.
* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.
* As the PowerPC does not have an instruction to load an immediate 32-bit value, it's common to see a lis/ori coding pattern.