2020-02-28 16:04:28 +00:00
|
|
|
/*
|
|
|
|
DingusPPC - The Experimental PowerPC Macintosh emulator
|
2022-01-10 16:42:24 +00:00
|
|
|
Copyright (C) 2018-22 divingkatae and maximum
|
2020-02-28 16:04:28 +00:00
|
|
|
(theweirdo) spatium
|
|
|
|
|
|
|
|
(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
|
|
|
|
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
|
|
it under the terms of the GNU General Public License as published by
|
|
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
|
|
(at your option) any later version.
|
|
|
|
|
|
|
|
This program is distributed in the hope that it will be useful,
|
|
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
GNU General Public License for more details.
|
|
|
|
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
|
|
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
|
|
|
*/
|
2019-08-27 12:14:12 +00:00
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
/** High-level VIA-CUDA combo device emulation.
|
|
|
|
*/
|
2019-08-27 12:14:12 +00:00
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
#include <core/timermanager.h>
|
2021-10-23 18:17:47 +00:00
|
|
|
#include <devices/common/adb/adb.h>
|
2022-01-10 16:42:24 +00:00
|
|
|
#include <devices/common/hwinterrupt.h>
|
2021-10-23 18:17:47 +00:00
|
|
|
#include <devices/common/viacuda.h>
|
2022-07-17 03:28:05 +00:00
|
|
|
#include <devices/deviceregistry.h>
|
2021-09-15 22:46:38 +00:00
|
|
|
#include <loguru.hpp>
|
2022-01-10 16:42:24 +00:00
|
|
|
#include <machines/machinebase.h>
|
2021-10-23 18:17:47 +00:00
|
|
|
#include <memaccess.h>
|
|
|
|
|
|
|
|
#include <cinttypes>
|
2021-10-13 22:01:30 +00:00
|
|
|
#include <memory>
|
2019-08-27 12:14:12 +00:00
|
|
|
|
|
|
|
using namespace std;
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
ViaCuda::ViaCuda() {
|
2020-03-14 13:23:46 +00:00
|
|
|
this->name = "ViaCuda";
|
|
|
|
|
2022-01-26 15:45:21 +00:00
|
|
|
supports_types(HWCompType::ADB_HOST | HWCompType::I2C_HOST);
|
|
|
|
|
2021-10-18 14:37:18 +00:00
|
|
|
// VIA reset clears all internal registers to logic 0
|
|
|
|
// except timers/counters and the shift register
|
|
|
|
// as stated in the 6522 datasheet
|
|
|
|
this->via_regs[VIA_A] = 0;
|
|
|
|
this->via_regs[VIA_B] = 0;
|
|
|
|
this->via_regs[VIA_DIRB] = 0;
|
|
|
|
this->via_regs[VIA_DIRA] = 0;
|
|
|
|
this->via_regs[VIA_IER] = 0;
|
|
|
|
this->via_regs[VIA_ACR] = 0;
|
|
|
|
this->via_regs[VIA_PCR] = 0;
|
|
|
|
this->via_regs[VIA_IFR] = 0;
|
|
|
|
|
|
|
|
// load maximum value into the timer registers for safety
|
|
|
|
// (not prescribed in the 6522 datasheet)
|
2019-08-27 12:14:12 +00:00
|
|
|
this->via_regs[VIA_T1LL] = 0xFF;
|
|
|
|
this->via_regs[VIA_T1LH] = 0xFF;
|
2021-10-18 14:37:18 +00:00
|
|
|
this->via_regs[VIA_T2CL] = 0xFF;
|
|
|
|
this->via_regs[VIA_T2CH] = 0xFF;
|
2019-09-21 12:54:53 +00:00
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
this->_via_ifr = 0; // all flags cleared
|
|
|
|
this->_via_ier = 0; // all interrupts disabled
|
|
|
|
|
2022-02-13 02:02:17 +00:00
|
|
|
// intialize counters/timers
|
|
|
|
this->t1_counter = 0xFFFF;
|
|
|
|
this->t1_active = false;
|
|
|
|
this->t2_counter = 0xFFFF;
|
2022-01-10 16:42:24 +00:00
|
|
|
this->t2_active = false;
|
|
|
|
|
|
|
|
// calculate VIA clock duration in ns
|
|
|
|
this->via_clk_dur = 1.0f / VIA_CLOCK_HZ * NS_PER_SEC;
|
|
|
|
|
2021-10-13 22:01:30 +00:00
|
|
|
// PRAM is part of Cuda
|
|
|
|
this->pram_obj = std::unique_ptr<NVram> (new NVram("pram.bin", 256));
|
2020-01-13 03:31:10 +00:00
|
|
|
|
2022-01-21 10:08:32 +00:00
|
|
|
// ADB bus is driven by Cuda
|
2022-01-10 16:42:24 +00:00
|
|
|
this->adb_bus = std::unique_ptr<ADB_Bus> (new ADB_Bus());
|
|
|
|
|
|
|
|
this->cuda_init();
|
2020-04-22 02:45:59 +00:00
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
this->int_ctrl = nullptr;
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
|
|
|
|
2022-01-21 11:37:47 +00:00
|
|
|
int ViaCuda::device_postinit()
|
|
|
|
{
|
|
|
|
this->int_ctrl = dynamic_cast<InterruptCtrl*>(
|
|
|
|
gMachineObj->get_comp_by_type(HWCompType::INT_CTRL));
|
|
|
|
this->irq_id = this->int_ctrl->register_dev_int(IntSrc::VIA_CUDA);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
void ViaCuda::cuda_init() {
|
2020-02-28 01:41:02 +00:00
|
|
|
this->old_tip = 0;
|
2019-09-21 12:54:53 +00:00
|
|
|
this->old_byteack = 0;
|
2020-02-28 01:41:02 +00:00
|
|
|
this->treq = 1;
|
|
|
|
this->in_count = 0;
|
|
|
|
this->out_count = 0;
|
2020-04-27 00:50:40 +00:00
|
|
|
this->poll_rate = 11;
|
2019-08-27 12:14:12 +00:00
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
uint8_t ViaCuda::read(int reg) {
|
2019-08-27 12:14:12 +00:00
|
|
|
/* reading from some VIA registers triggers special actions */
|
2020-02-27 02:51:07 +00:00
|
|
|
switch (reg & 0xF) {
|
2019-09-21 12:54:53 +00:00
|
|
|
case VIA_B:
|
2022-01-10 16:42:24 +00:00
|
|
|
return (this->via_regs[VIA_B]);
|
2019-09-21 12:54:53 +00:00
|
|
|
case VIA_A:
|
|
|
|
case VIA_ANH:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "Attempted read from VIA Port A!");
|
2019-09-21 12:54:53 +00:00
|
|
|
break;
|
2019-08-27 12:14:12 +00:00
|
|
|
case VIA_IER:
|
2022-01-10 16:42:24 +00:00
|
|
|
return (this->_via_ier | 0x80); // bit 7 always reads as "1"
|
|
|
|
case VIA_IFR:
|
|
|
|
return this->_via_ifr;
|
2022-02-13 02:02:17 +00:00
|
|
|
case VIA_T1CL:
|
|
|
|
this->_via_ifr &= ~VIA_IF_T1;
|
|
|
|
update_irq();
|
|
|
|
return this->calc_counter_val(this->t1_counter, this->t1_start_time) & 0xFFU;
|
|
|
|
case VIA_T1CH:
|
|
|
|
return this->calc_counter_val(this->t1_counter, this->t1_start_time) >> 8;
|
2022-01-10 16:42:24 +00:00
|
|
|
case VIA_T2CL:
|
|
|
|
this->_via_ifr &= ~VIA_IF_T2;
|
|
|
|
update_irq();
|
2022-02-13 02:02:17 +00:00
|
|
|
return this->calc_counter_val(this->t2_counter, this->t2_start_time) & 0xFFU;
|
|
|
|
case VIA_T2CH:
|
|
|
|
return this->calc_counter_val(this->t2_counter, this->t2_start_time) >> 8;
|
2022-01-10 16:42:24 +00:00
|
|
|
case VIA_SR:
|
|
|
|
this->_via_ifr &= ~VIA_IF_SR;
|
|
|
|
update_irq();
|
|
|
|
break;
|
2019-08-27 12:14:12 +00:00
|
|
|
}
|
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
return (this->via_regs[reg & 0xF]);
|
2019-08-27 12:14:12 +00:00
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::write(int reg, uint8_t value) {
|
2022-01-10 16:42:24 +00:00
|
|
|
this->via_regs[reg & 0xF] = value;
|
|
|
|
|
2020-02-27 02:51:07 +00:00
|
|
|
switch (reg & 0xF) {
|
2019-08-27 12:14:12 +00:00
|
|
|
case VIA_B:
|
2020-03-04 14:46:51 +00:00
|
|
|
write(value);
|
2019-08-27 12:14:12 +00:00
|
|
|
break;
|
|
|
|
case VIA_A:
|
2019-09-21 12:54:53 +00:00
|
|
|
case VIA_ANH:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "Attempted write to VIA Port A!");
|
2019-08-27 12:14:12 +00:00
|
|
|
break;
|
|
|
|
case VIA_DIRB:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "VIA_DIRB = 0x%X", value);
|
2019-08-27 12:14:12 +00:00
|
|
|
break;
|
|
|
|
case VIA_DIRA:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "VIA_DIRA = 0x%X", value);
|
2019-08-27 12:14:12 +00:00
|
|
|
break;
|
|
|
|
case VIA_PCR:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "VIA_PCR = 0x%X", value);
|
2019-08-27 12:14:12 +00:00
|
|
|
break;
|
|
|
|
case VIA_ACR:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "VIA_ACR = 0x%X", value);
|
2022-01-10 16:42:24 +00:00
|
|
|
break;
|
|
|
|
case VIA_IFR:
|
2022-01-21 10:08:32 +00:00
|
|
|
// for each "1" in value clear the corresponding flags
|
2022-01-10 16:42:24 +00:00
|
|
|
this->_via_ifr &= ~value;
|
|
|
|
update_irq();
|
2019-08-27 12:14:12 +00:00
|
|
|
break;
|
|
|
|
case VIA_IER:
|
2022-01-10 16:42:24 +00:00
|
|
|
if (value & 0x80) {
|
|
|
|
this->_via_ier |= value & 0x7F;
|
|
|
|
} else {
|
|
|
|
this->_via_ier &= ~value;
|
|
|
|
}
|
|
|
|
update_irq();
|
2019-08-27 12:14:12 +00:00
|
|
|
print_enabled_ints();
|
|
|
|
break;
|
2022-02-13 02:02:17 +00:00
|
|
|
case VIA_T1CH:
|
|
|
|
if (this->via_regs[VIA_ACR] & 0xC0) {
|
|
|
|
ABORT_F("Unsupported VIA T1 mode, ACR=0x%X", this->via_regs[VIA_ACR]);
|
|
|
|
}
|
|
|
|
// cancel active T1 timer task
|
|
|
|
if (this->t1_active) {
|
|
|
|
TimerManager::get_instance()->cancel_timer(this->t1_timer_id);
|
|
|
|
this->t1_active = false;
|
|
|
|
}
|
|
|
|
// clear T1 flag in IFR
|
|
|
|
this->_via_ifr &= ~VIA_IF_T1;
|
|
|
|
update_irq();
|
|
|
|
// load initial value into counter 1
|
|
|
|
this->t1_counter = (value << 8) | this->via_regs[VIA_T1CL];
|
|
|
|
// TODO: delay for one phase 2 clock
|
|
|
|
// sample current vCPU time and remember it
|
|
|
|
this->t1_start_time = TimerManager::get_instance()->current_time_ns();
|
|
|
|
// set up timout timer for T1
|
|
|
|
this->t1_timer_id = TimerManager::get_instance()->add_oneshot_timer(
|
|
|
|
static_cast<uint64_t>(this->via_clk_dur * (this->t1_counter + 3) + 0.5f),
|
|
|
|
[this]() {
|
|
|
|
this->assert_t1_int();
|
|
|
|
}
|
|
|
|
);
|
|
|
|
this->t1_active = true;
|
|
|
|
break;
|
2022-01-10 16:42:24 +00:00
|
|
|
case VIA_T2CH:
|
2022-02-13 02:02:17 +00:00
|
|
|
if (this->via_regs[VIA_ACR] & 0x20) {
|
|
|
|
ABORT_F("VIA T2 pulse count mode not supported!");
|
|
|
|
}
|
|
|
|
// cancel active T2 timer task
|
2022-01-10 16:42:24 +00:00
|
|
|
if (this->t2_active) {
|
|
|
|
TimerManager::get_instance()->cancel_timer(this->t2_timer_id);
|
|
|
|
this->t2_active = false;
|
|
|
|
}
|
|
|
|
// clear T2 flag in IFR
|
|
|
|
this->_via_ifr &= ~VIA_IF_T2;
|
|
|
|
update_irq();
|
2022-02-13 02:02:17 +00:00
|
|
|
// load initial value into counter 2
|
|
|
|
this->t2_counter = (value << 8) | this->via_regs[VIA_T2CL];
|
|
|
|
// TODO: delay for one phase 2 clock
|
2022-01-10 16:42:24 +00:00
|
|
|
// sample current vCPU time and remember it
|
2022-02-13 02:02:17 +00:00
|
|
|
this->t2_start_time = TimerManager::get_instance()->current_time_ns();
|
|
|
|
// set up timeout timer for T2
|
2022-01-10 16:42:24 +00:00
|
|
|
this->t2_timer_id = TimerManager::get_instance()->add_oneshot_timer(
|
2022-02-13 02:02:17 +00:00
|
|
|
static_cast<uint64_t>(this->via_clk_dur * (this->t2_counter + 3) + 0.5f),
|
|
|
|
[this]() {
|
|
|
|
this->assert_t2_int();
|
|
|
|
}
|
|
|
|
);
|
2022-01-10 16:42:24 +00:00
|
|
|
this->t2_active = true;
|
|
|
|
break;
|
|
|
|
case VIA_SR:
|
|
|
|
this->_via_ifr &= ~VIA_IF_SR;
|
|
|
|
update_irq();
|
|
|
|
break;
|
2019-08-27 12:14:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-02-13 02:02:17 +00:00
|
|
|
uint16_t ViaCuda::calc_counter_val(const uint16_t last_val, const uint64_t& last_time)
|
|
|
|
{
|
|
|
|
// calcualte current counter value based on elapsed time and timer frequency
|
|
|
|
uint64_t cur_time = TimerManager::get_instance()->current_time_ns();
|
|
|
|
uint32_t diff = (cur_time - last_time) / this->via_clk_dur;
|
|
|
|
return last_val - diff;
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::print_enabled_ints() {
|
|
|
|
const char* via_int_src[] = {"CA2", "CA1", "SR", "CB2", "CB1", "T2", "T1"};
|
2019-08-27 12:14:12 +00:00
|
|
|
|
|
|
|
for (int i = 0; i < 7; i++) {
|
2022-01-10 16:42:24 +00:00
|
|
|
if (this->_via_ier & (1 << i))
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(INFO, "VIA %s interrupt enabled", via_int_src[i]);
|
2019-08-27 12:14:12 +00:00
|
|
|
}
|
|
|
|
}
|
2019-09-21 12:54:53 +00:00
|
|
|
|
2022-08-24 11:08:24 +00:00
|
|
|
void ViaCuda::update_irq()
|
|
|
|
{
|
|
|
|
uint8_t active_ints = this->_via_ifr & this->_via_ier & 0x7F;
|
|
|
|
if (active_ints != this->old_ifr) {
|
|
|
|
uint8_t new_irq = !!active_ints;
|
|
|
|
this->_via_ifr = (active_ints) | (new_irq << 7);
|
|
|
|
this->old_ifr = active_ints;
|
|
|
|
LOG_F(6, "VIA: assert IRQ, IFR=0x%02X", this->_via_ifr);
|
2022-01-10 16:42:24 +00:00
|
|
|
this->int_ctrl->ack_int(this->irq_id, new_irq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
inline bool ViaCuda::ready() {
|
2019-09-21 12:54:53 +00:00
|
|
|
return ((this->via_regs[VIA_DIRB] & 0x38) == 0x30);
|
|
|
|
}
|
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
void ViaCuda::assert_sr_int() {
|
|
|
|
this->sr_timer_on = false;
|
|
|
|
this->_via_ifr |= VIA_IF_SR;
|
|
|
|
update_irq();
|
|
|
|
}
|
|
|
|
|
2022-02-13 02:02:17 +00:00
|
|
|
void ViaCuda::assert_t1_int() {
|
|
|
|
this->_via_ifr |= VIA_IF_T1;
|
|
|
|
this->t1_active = false;
|
|
|
|
update_irq();
|
|
|
|
}
|
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
void ViaCuda::assert_t2_int() {
|
|
|
|
this->_via_ifr |= VIA_IF_T2;
|
|
|
|
this->t2_active = false;
|
|
|
|
update_irq();
|
|
|
|
}
|
|
|
|
|
2022-08-27 15:34:05 +00:00
|
|
|
#ifdef DEBUG_CPU_INT
|
|
|
|
void ViaCuda::assert_int(uint8_t flags) {
|
|
|
|
this->_via_ifr |= (flags & 0x7F);
|
|
|
|
update_irq();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2022-01-21 10:08:32 +00:00
|
|
|
void ViaCuda::assert_ctrl_line(ViaLine line)
|
|
|
|
{
|
|
|
|
switch (line) {
|
|
|
|
case ViaLine::CA1:
|
|
|
|
this->_via_ifr |= VIA_IF_CA1;
|
|
|
|
break;
|
|
|
|
case ViaLine::CA2:
|
|
|
|
this->_via_ifr |= VIA_IF_CA2;
|
|
|
|
break;
|
|
|
|
case ViaLine::CB1:
|
|
|
|
this->_via_ifr |= VIA_IF_CB1;
|
|
|
|
break;
|
|
|
|
case ViaLine::CB2:
|
|
|
|
this->_via_ifr |= VIA_IF_CB1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ABORT_F("Assertion of unknown VIA line requested!");
|
|
|
|
}
|
|
|
|
update_irq();
|
|
|
|
}
|
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
void ViaCuda::schedule_sr_int(uint64_t timeout_ns) {
|
|
|
|
if (this->sr_timer_on) {
|
|
|
|
TimerManager::get_instance()->cancel_timer(this->sr_timer_id);
|
|
|
|
this->sr_timer_on = false;
|
|
|
|
}
|
|
|
|
this->sr_timer_id = TimerManager::get_instance()->add_oneshot_timer(
|
|
|
|
timeout_ns,
|
|
|
|
[this]() { this->assert_sr_int(); });
|
|
|
|
this->sr_timer_on = true;
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::write(uint8_t new_state) {
|
2020-03-04 14:46:51 +00:00
|
|
|
if (!ready()) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "Cuda not ready!");
|
2019-09-21 12:54:53 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
int new_tip = !!(new_state & CUDA_TIP);
|
2019-09-21 12:54:53 +00:00
|
|
|
int new_byteack = !!(new_state & CUDA_BYTEACK);
|
|
|
|
|
|
|
|
/* return if there is no state change */
|
|
|
|
if (new_tip == this->old_tip && new_byteack == this->old_byteack)
|
|
|
|
return;
|
|
|
|
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda state changed!");
|
2019-09-21 12:54:53 +00:00
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
this->old_tip = new_tip;
|
2019-09-21 12:54:53 +00:00
|
|
|
this->old_byteack = new_byteack;
|
|
|
|
|
|
|
|
if (new_tip) {
|
|
|
|
if (new_byteack) {
|
|
|
|
this->via_regs[VIA_B] |= CUDA_TREQ; /* negate TREQ */
|
|
|
|
this->treq = 1;
|
|
|
|
|
|
|
|
if (this->in_count) {
|
2020-03-04 14:46:51 +00:00
|
|
|
process_packet();
|
2019-09-21 12:54:53 +00:00
|
|
|
|
|
|
|
/* start response transaction */
|
|
|
|
this->via_regs[VIA_B] &= ~CUDA_TREQ; /* assert TREQ */
|
|
|
|
this->treq = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
this->in_count = 0;
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda: enter sync state");
|
2019-09-21 12:54:53 +00:00
|
|
|
this->via_regs[VIA_B] &= ~CUDA_TREQ; /* assert TREQ */
|
2020-02-28 01:41:02 +00:00
|
|
|
this->treq = 0;
|
|
|
|
this->in_count = 0;
|
2019-09-21 12:54:53 +00:00
|
|
|
this->out_count = 0;
|
|
|
|
}
|
|
|
|
|
2022-01-10 16:42:24 +00:00
|
|
|
// send dummy byte as idle acknowledge or attention
|
|
|
|
//assert_sr_int();
|
|
|
|
schedule_sr_int(USECS_TO_NSECS(61));
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2019-09-21 12:54:53 +00:00
|
|
|
if (this->via_regs[VIA_ACR] & 0x10) { /* data transfer: Host --> Cuda */
|
2022-02-19 22:22:21 +00:00
|
|
|
if (this->in_count < sizeof(this->in_buf)) {
|
2019-09-21 12:54:53 +00:00
|
|
|
this->in_buf[this->in_count++] = this->via_regs[VIA_SR];
|
2022-01-10 16:42:24 +00:00
|
|
|
// tell the system we've read the byte after 71 usecs
|
2022-01-21 10:08:32 +00:00
|
|
|
schedule_sr_int(USECS_TO_NSECS(71));
|
2022-01-10 16:42:24 +00:00
|
|
|
//assert_sr_int();
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2021-10-17 20:31:54 +00:00
|
|
|
LOG_F(WARNING, "Cuda input buffer too small. Truncating data!");
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
2020-05-12 18:55:45 +00:00
|
|
|
} else { /* data transfer: Cuda --> Host */
|
2020-03-15 12:28:35 +00:00
|
|
|
(this->*out_handler)();
|
2022-01-10 16:42:24 +00:00
|
|
|
//assert_sr_int();
|
|
|
|
// tell the system we've written next byte after 88 usecs
|
|
|
|
schedule_sr_int(USECS_TO_NSECS(88));
|
2020-03-15 12:28:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-09-21 12:54:53 +00:00
|
|
|
|
2021-10-13 22:01:30 +00:00
|
|
|
/* sends zeros to host ad infinitum */
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::null_out_handler() {
|
2020-03-15 12:28:35 +00:00
|
|
|
this->via_regs[VIA_SR] = 0;
|
|
|
|
}
|
2019-09-21 12:54:53 +00:00
|
|
|
|
2021-10-13 22:01:30 +00:00
|
|
|
/* sends PRAM content to host ad infinitum */
|
|
|
|
void ViaCuda::pram_out_handler()
|
|
|
|
{
|
|
|
|
this->via_regs[VIA_SR] = this->pram_obj->read_byte(this->cur_pram_addr++);
|
|
|
|
}
|
|
|
|
|
2020-03-15 12:28:35 +00:00
|
|
|
/* sends data from out_buf until exhausted, then switches to next_out_handler */
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::out_buf_handler() {
|
2020-03-15 12:28:35 +00:00
|
|
|
if (this->out_pos < this->out_count) {
|
|
|
|
LOG_F(9, "OutBufHandler: sending next byte 0x%X", this->out_buf[this->out_pos]);
|
|
|
|
this->via_regs[VIA_SR] = this->out_buf[this->out_pos++];
|
2020-05-12 18:55:45 +00:00
|
|
|
} else if (this->is_open_ended) {
|
2020-03-15 12:28:35 +00:00
|
|
|
LOG_F(9, "OutBufHandler: switching to next handler");
|
2020-05-12 18:55:45 +00:00
|
|
|
this->out_handler = this->next_out_handler;
|
2020-03-15 12:28:35 +00:00
|
|
|
this->next_out_handler = &ViaCuda::null_out_handler;
|
|
|
|
(this->*out_handler)();
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2020-03-15 12:28:35 +00:00
|
|
|
LOG_F(9, "Sending last byte");
|
|
|
|
this->out_count = 0;
|
|
|
|
this->via_regs[VIA_B] |= CUDA_TREQ; /* negate TREQ */
|
|
|
|
this->treq = 1;
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::response_header(uint32_t pkt_type, uint32_t pkt_flag) {
|
|
|
|
this->out_buf[0] = pkt_type;
|
|
|
|
this->out_buf[1] = pkt_flag;
|
|
|
|
this->out_buf[2] = this->in_buf[1]; /* copy original cmd */
|
|
|
|
this->out_count = 3;
|
|
|
|
this->out_pos = 0;
|
|
|
|
this->out_handler = &ViaCuda::out_buf_handler;
|
2020-03-15 12:28:35 +00:00
|
|
|
this->next_out_handler = &ViaCuda::null_out_handler;
|
2020-05-12 18:55:45 +00:00
|
|
|
this->is_open_ended = false;
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::error_response(uint32_t error) {
|
|
|
|
this->out_buf[0] = CUDA_PKT_ERROR;
|
|
|
|
this->out_buf[1] = error;
|
|
|
|
this->out_buf[2] = this->in_buf[0];
|
|
|
|
this->out_buf[3] = this->in_buf[1]; /* copy original cmd */
|
|
|
|
this->out_count = 4;
|
|
|
|
this->out_pos = 0;
|
|
|
|
this->out_handler = &ViaCuda::out_buf_handler;
|
2020-03-15 12:28:35 +00:00
|
|
|
this->next_out_handler = &ViaCuda::null_out_handler;
|
2020-05-12 18:55:45 +00:00
|
|
|
this->is_open_ended = false;
|
2019-10-07 01:18:18 +00:00
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::process_packet() {
|
2019-09-21 12:54:53 +00:00
|
|
|
if (this->in_count < 2) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(ERROR, "Cuda: invalid packet (too few data)!");
|
2020-03-15 12:28:35 +00:00
|
|
|
error_response(CUDA_ERR_BAD_SIZE);
|
2019-09-21 12:54:53 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-02-27 02:51:07 +00:00
|
|
|
switch (this->in_buf[0]) {
|
2019-10-07 01:18:18 +00:00
|
|
|
case CUDA_PKT_ADB:
|
2022-08-14 12:26:56 +00:00
|
|
|
LOG_F(9, "Cuda: ADB packet received");
|
2020-03-05 00:12:27 +00:00
|
|
|
process_adb_command(this->in_buf[1], this->in_count - 2);
|
2019-09-21 12:54:53 +00:00
|
|
|
break;
|
2019-10-07 01:18:18 +00:00
|
|
|
case CUDA_PKT_PSEUDO:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda: pseudo command packet received");
|
|
|
|
LOG_F(9, "Command: 0x%X", this->in_buf[1]);
|
|
|
|
LOG_F(9, "Data count: %d", this->in_count);
|
2019-09-21 12:54:53 +00:00
|
|
|
for (int i = 0; i < this->in_count; i++) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "0x%X ,", this->in_buf[i]);
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
2020-03-04 14:46:51 +00:00
|
|
|
pseudo_command(this->in_buf[1], this->in_count - 2);
|
2019-09-21 12:54:53 +00:00
|
|
|
break;
|
|
|
|
default:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(ERROR, "Cuda: unsupported packet type = %d", this->in_buf[0]);
|
2020-03-15 12:28:35 +00:00
|
|
|
error_response(CUDA_ERR_BAD_PKT);
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::process_adb_command(uint8_t cmd_byte, int data_count) {
|
|
|
|
int adb_dev = cmd_byte >> 4; // 2 for keyboard, 3 for mouse
|
|
|
|
int cmd = cmd_byte & 0xF;
|
2020-03-05 00:12:27 +00:00
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
if (!cmd) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda: ADB SendReset command requested");
|
2020-03-05 00:12:27 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 0);
|
2020-05-12 18:55:45 +00:00
|
|
|
} else if (cmd == 1) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda: ADB Flush command requested");
|
2020-03-05 00:12:27 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 0);
|
2020-05-12 18:55:45 +00:00
|
|
|
} else if ((cmd & 0xC) == 8) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda: ADB Listen command requested");
|
2020-04-21 22:23:55 +00:00
|
|
|
int adb_reg = cmd_byte & 0x3;
|
2022-01-10 16:42:24 +00:00
|
|
|
if (adb_bus->listen(adb_dev, adb_reg)) {
|
2020-04-22 21:14:49 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 0);
|
2022-01-10 16:42:24 +00:00
|
|
|
for (int data_ptr = 0; data_ptr < adb_bus->get_output_len(); data_ptr++) {
|
|
|
|
this->in_buf[(2 + data_ptr)] = adb_bus->get_output_byte(data_ptr);
|
2020-04-22 02:45:59 +00:00
|
|
|
}
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2020-04-21 22:23:55 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 2);
|
|
|
|
}
|
2020-05-12 18:55:45 +00:00
|
|
|
} else if ((cmd & 0xC) == 0xC) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(9, "Cuda: ADB Talk command requested");
|
2020-03-05 00:12:27 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 0);
|
2020-04-21 22:23:55 +00:00
|
|
|
int adb_reg = cmd_byte & 0x3;
|
2022-01-10 16:42:24 +00:00
|
|
|
if (adb_bus->talk(adb_dev, adb_reg, this->in_buf[2])) {
|
2020-04-22 21:14:49 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 0);
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2020-04-21 22:23:55 +00:00
|
|
|
response_header(CUDA_PKT_ADB, 2);
|
|
|
|
}
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(ERROR, "Cuda: unsupported ADB command 0x%X", cmd);
|
2020-03-05 00:12:27 +00:00
|
|
|
error_response(CUDA_ERR_BAD_CMD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::pseudo_command(int cmd, int data_count) {
|
2021-10-17 20:31:54 +00:00
|
|
|
uint16_t addr;
|
|
|
|
int i;
|
2021-10-13 22:01:30 +00:00
|
|
|
|
2020-02-27 02:51:07 +00:00
|
|
|
switch (cmd) {
|
2020-04-27 00:50:40 +00:00
|
|
|
case CUDA_START_STOP_AUTOPOLL:
|
|
|
|
if (this->in_buf[2]) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(INFO, "Cuda: autopoll started, rate: %d ms", this->poll_rate);
|
2020-05-12 18:55:45 +00:00
|
|
|
} else {
|
2020-04-27 00:50:40 +00:00
|
|
|
LOG_F(INFO, "Cuda: autopoll stopped");
|
|
|
|
}
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
2020-04-18 00:23:50 +00:00
|
|
|
break;
|
2021-10-17 20:31:54 +00:00
|
|
|
case CUDA_READ_MCU_MEM:
|
|
|
|
addr = READ_WORD_BE_A(&this->in_buf[2]);
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
// if starting address is within PRAM region
|
|
|
|
// prepare to transfer PRAM content, othwesise we will send zeroes
|
|
|
|
if (addr >= CUDA_PRAM_START && addr <= CUDA_PRAM_END) {
|
|
|
|
this->cur_pram_addr = addr - CUDA_PRAM_START;
|
|
|
|
this->next_out_handler = &ViaCuda::pram_out_handler;
|
|
|
|
} else if (addr >= CUDA_ROM_START) {
|
|
|
|
// HACK: Cuda ROM dump requsted so let's partially fake it
|
|
|
|
this->out_buf[3] = 0; // empty copyright string
|
|
|
|
WRITE_WORD_BE_A(&this->out_buf[4], 0x0019U);
|
|
|
|
WRITE_WORD_BE_A(&this->out_buf[6], CUDA_FW_VERSION_MAJOR);
|
|
|
|
WRITE_WORD_BE_A(&this->out_buf[8], CUDA_FW_VERSION_MINOR);
|
|
|
|
this->out_count += 7;
|
|
|
|
}
|
|
|
|
this->is_open_ended = true;
|
|
|
|
break;
|
2021-11-10 14:56:50 +00:00
|
|
|
case CUDA_GET_REAL_TIME:
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
this->out_buf[2] = (uint8_t)((this->real_time >> 24) & 0xFF);
|
|
|
|
this->out_buf[3] = (uint8_t)((this->real_time >> 16) & 0xFF);
|
|
|
|
this->out_buf[4] = (uint8_t)((this->real_time >> 8) & 0xFF);
|
|
|
|
this->out_buf[5] = (uint8_t)((this->real_time) & 0xFF);
|
|
|
|
break;
|
2021-10-17 20:31:54 +00:00
|
|
|
case CUDA_WRITE_MCU_MEM:
|
|
|
|
addr = READ_WORD_BE_A(&this->in_buf[2]);
|
|
|
|
// if addr is inside PRAM, update PRAM with data from in_buf
|
|
|
|
// otherwise, ignore data in in_buf
|
|
|
|
if (addr >= CUDA_PRAM_START && addr <= CUDA_PRAM_END) {
|
|
|
|
for (i = 0; i < this->in_count - 4; i++) {
|
|
|
|
this->pram_obj->write_byte((addr - CUDA_PRAM_START + i) & 0xFF,
|
|
|
|
this->in_buf[4+i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
break;
|
2020-01-13 03:31:10 +00:00
|
|
|
case CUDA_READ_PRAM:
|
2021-10-13 22:01:30 +00:00
|
|
|
addr = READ_WORD_BE_A(&this->in_buf[2]);
|
|
|
|
if (addr <= 0xFF) {
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
// this command is open-ended so set up the corresponding context
|
|
|
|
this->cur_pram_addr = addr;
|
|
|
|
this->next_out_handler = &ViaCuda::pram_out_handler;
|
|
|
|
this->is_open_ended = true;
|
|
|
|
} else {
|
|
|
|
error_response(CUDA_ERR_BAD_PAR);
|
|
|
|
}
|
2020-01-13 03:31:10 +00:00
|
|
|
break;
|
2021-11-10 14:56:50 +00:00
|
|
|
case CUDA_SET_REAL_TIME:
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
this->real_time = ((uint32_t)in_buf[2]) >> 24;
|
|
|
|
this->real_time += ((uint32_t)in_buf[3]) >> 16;
|
|
|
|
this->real_time += ((uint32_t)in_buf[4]) >> 8;
|
|
|
|
this->real_time += ((uint32_t)in_buf[5]);
|
|
|
|
break;
|
2020-01-13 03:31:10 +00:00
|
|
|
case CUDA_WRITE_PRAM:
|
2021-10-13 22:01:30 +00:00
|
|
|
addr = READ_WORD_BE_A(&this->in_buf[2]);
|
|
|
|
if (addr <= 0xFF) {
|
2021-10-17 20:31:54 +00:00
|
|
|
// transfer data from in_buf to PRAM
|
|
|
|
for (i = 0; i < this->in_count - 4; i++) {
|
|
|
|
this->pram_obj->write_byte((addr + i) & 0xFF, this->in_buf[4+i]);
|
|
|
|
}
|
2021-10-13 22:01:30 +00:00
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
} else {
|
|
|
|
error_response(CUDA_ERR_BAD_PAR);
|
|
|
|
}
|
2020-01-13 03:31:10 +00:00
|
|
|
break;
|
2021-11-10 14:56:50 +00:00
|
|
|
case CUDA_FILE_SERVER_FLAG:
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
if (this->in_buf[2]) {
|
|
|
|
LOG_F(INFO, "Cuda: File server flag on");
|
|
|
|
this->file_server = true;
|
|
|
|
} else {
|
|
|
|
LOG_F(INFO, "Cuda: File server flag off");
|
|
|
|
this->file_server = false;
|
|
|
|
}
|
|
|
|
break;
|
2020-04-27 00:50:40 +00:00
|
|
|
case CUDA_SET_AUTOPOLL_RATE:
|
|
|
|
this->poll_rate = this->in_buf[2];
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(INFO, "Cuda: autopoll rate set to %d ms", this->poll_rate);
|
2020-04-18 00:23:50 +00:00
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
break;
|
2020-04-27 00:50:40 +00:00
|
|
|
case CUDA_GET_AUTOPOLL_RATE:
|
2020-04-18 00:23:50 +00:00
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
2020-04-27 00:50:40 +00:00
|
|
|
this->out_buf[3] = this->poll_rate;
|
|
|
|
this->out_count++;
|
2020-04-18 00:23:50 +00:00
|
|
|
break;
|
2021-11-10 14:56:50 +00:00
|
|
|
case CUDA_SET_DEVICE_LIST:
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
this->device_mask = ((uint16_t)in_buf[2]) >> 8;
|
|
|
|
this->device_mask += ((uint16_t)in_buf[3]);
|
|
|
|
break;
|
|
|
|
case CUDA_GET_DEVICE_LIST:
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
this->out_buf[2] = (uint8_t)((this->device_mask >> 8) & 0xFF);
|
|
|
|
this->out_buf[3] = (uint8_t)((this->device_mask) & 0xFF);
|
|
|
|
break;
|
|
|
|
case CUDA_ONE_SECOND_MODE:
|
|
|
|
LOG_F(INFO, "Cuda: One Second Interrupt - Byte Sent: %d", this->in_buf[2]);
|
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
|
|
|
break;
|
2019-09-21 12:54:53 +00:00
|
|
|
case CUDA_READ_WRITE_I2C:
|
2020-03-04 14:46:51 +00:00
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
2019-10-07 01:18:18 +00:00
|
|
|
i2c_simple_transaction(this->in_buf[2], &this->in_buf[3], this->in_count - 3);
|
|
|
|
break;
|
|
|
|
case CUDA_COMB_FMT_I2C:
|
2020-03-04 14:46:51 +00:00
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
2019-10-07 01:18:18 +00:00
|
|
|
if (this->in_count >= 5) {
|
2020-05-12 18:55:45 +00:00
|
|
|
i2c_comb_transaction(
|
|
|
|
this->in_buf[2], this->in_buf[3], this->in_buf[4], &this->in_buf[5], this->in_count - 5);
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case CUDA_OUT_PB0: /* undocumented call! */
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(INFO, "Cuda: send %d to PB0", (int)(this->in_buf[2]));
|
2020-03-04 14:46:51 +00:00
|
|
|
response_header(CUDA_PKT_PSEUDO, 0);
|
2019-09-21 12:54:53 +00:00
|
|
|
break;
|
2021-11-10 14:56:50 +00:00
|
|
|
case CUDA_WARM_START:
|
|
|
|
case CUDA_POWER_DOWN:
|
|
|
|
case CUDA_MONO_STABLE_RESET:
|
|
|
|
case CUDA_RESTART_SYSTEM:
|
|
|
|
/* really kludge temp code */
|
2022-08-14 12:26:56 +00:00
|
|
|
LOG_F(INFO, "Cuda: Restart/Shutdown signal sent with command 0x%x!", cmd);
|
2021-11-10 14:56:50 +00:00
|
|
|
//exit(0);
|
|
|
|
break;
|
2019-09-21 12:54:53 +00:00
|
|
|
default:
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(ERROR, "Cuda: unsupported pseudo command 0x%X", cmd);
|
2020-03-04 14:46:51 +00:00
|
|
|
error_response(CUDA_ERR_BAD_CMD);
|
2019-10-07 01:18:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-15 12:28:35 +00:00
|
|
|
/* sends data from the current I2C to host ad infinitum */
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::i2c_handler() {
|
2020-03-15 12:28:35 +00:00
|
|
|
this->receive_byte(this->curr_i2c_addr, &this->via_regs[VIA_SR]);
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::i2c_simple_transaction(uint8_t dev_addr, const uint8_t* in_buf, int in_bytes) {
|
2020-03-15 12:28:35 +00:00
|
|
|
int op_type = dev_addr & 1; /* 0 - write to device, 1 - read from device */
|
2019-10-07 01:18:18 +00:00
|
|
|
|
2020-03-15 12:28:35 +00:00
|
|
|
dev_addr >>= 1; /* strip RD/WR bit */
|
|
|
|
|
|
|
|
if (!this->start_transaction(dev_addr)) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "Unsupported I2C device 0x%X", dev_addr);
|
2020-03-04 14:46:51 +00:00
|
|
|
error_response(CUDA_ERR_I2C);
|
2020-03-15 12:28:35 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* send data to the target I2C device until there is no more data to send
|
|
|
|
or the target device doesn't acknowledge that indicates an error */
|
|
|
|
for (int i = 0; i < in_bytes; i++) {
|
|
|
|
if (!this->send_byte(dev_addr, in_buf[i])) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "NO_ACK during sending, device 0x%X", dev_addr);
|
2020-03-15 12:28:35 +00:00
|
|
|
error_response(CUDA_ERR_I2C);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (op_type) { /* read request initiate an open ended transaction */
|
2020-05-12 18:55:45 +00:00
|
|
|
this->curr_i2c_addr = dev_addr;
|
|
|
|
this->out_handler = &ViaCuda::out_buf_handler;
|
2020-03-15 12:28:35 +00:00
|
|
|
this->next_out_handler = &ViaCuda::i2c_handler;
|
2020-05-12 18:55:45 +00:00
|
|
|
this->is_open_ended = true;
|
2019-10-07 01:18:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-12 18:55:45 +00:00
|
|
|
void ViaCuda::i2c_comb_transaction(
|
|
|
|
uint8_t dev_addr, uint8_t sub_addr, uint8_t dev_addr1, const uint8_t* in_buf, int in_bytes) {
|
2020-03-15 12:28:35 +00:00
|
|
|
int op_type = dev_addr1 & 1; /* 0 - write to device, 1 - read from device */
|
2019-10-07 01:18:18 +00:00
|
|
|
|
|
|
|
if ((dev_addr & 0xFE) != (dev_addr1 & 0xFE)) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(ERROR, "Combined I2C: dev_addr mismatch!");
|
2020-03-15 12:28:35 +00:00
|
|
|
error_response(CUDA_ERR_I2C);
|
2019-10-07 01:18:18 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-03-15 12:28:35 +00:00
|
|
|
dev_addr >>= 1; /* strip RD/WR bit */
|
|
|
|
|
|
|
|
if (!this->start_transaction(dev_addr)) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "Unsupported I2C device 0x%X", dev_addr);
|
2020-03-15 12:28:35 +00:00
|
|
|
error_response(CUDA_ERR_I2C);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!this->send_subaddress(dev_addr, sub_addr)) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "NO_ACK while sending subaddress, device 0x%X", dev_addr);
|
2020-03-04 14:46:51 +00:00
|
|
|
error_response(CUDA_ERR_I2C);
|
2020-03-15 12:28:35 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* send data to the target I2C device until there is no more data to send
|
|
|
|
or the target device doesn't acknowledge that indicates an error */
|
|
|
|
for (int i = 0; i < in_bytes; i++) {
|
|
|
|
if (!this->send_byte(dev_addr, in_buf[i])) {
|
2021-10-18 14:33:00 +00:00
|
|
|
LOG_F(WARNING, "NO_ACK during sending, device 0x%X", dev_addr);
|
2020-03-15 12:28:35 +00:00
|
|
|
error_response(CUDA_ERR_I2C);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!op_type) { /* return dummy response for writes */
|
|
|
|
LOG_F(WARNING, "Combined I2C - write request!");
|
|
|
|
} else {
|
2020-05-12 18:55:45 +00:00
|
|
|
this->curr_i2c_addr = dev_addr;
|
|
|
|
this->out_handler = &ViaCuda::out_buf_handler;
|
2020-03-15 12:28:35 +00:00
|
|
|
this->next_out_handler = &ViaCuda::i2c_handler;
|
2020-05-12 18:55:45 +00:00
|
|
|
this->is_open_ended = true;
|
2019-09-21 12:54:53 +00:00
|
|
|
}
|
2020-01-15 17:15:08 +00:00
|
|
|
}
|
2022-07-17 03:28:05 +00:00
|
|
|
|
|
|
|
static const DeviceDescription ViaCuda_Descriptor = {
|
|
|
|
ViaCuda::create, {}, {}
|
|
|
|
};
|
|
|
|
|
|
|
|
REGISTER_DEVICE(ViaCuda, ViaCuda_Descriptor);
|