2020-02-28 16:04:28 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2022-01-10 16:42:24 +00:00
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Copyright (C) 2018-22 divingkatae and maximum
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2020-02-28 16:04:28 +00:00
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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2019-08-27 12:14:12 +00:00
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2019-08-28 00:39:29 +00:00
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/** VIA-CUDA combo device emulation.
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Versatile interface adapter (VIA) is an old I/O controller that can be found
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in nearly every Macintosh computer. In the 68k era, VIA was used to control
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2022-01-10 16:42:24 +00:00
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various peripheral devices. In a Power Macintosh, its function is limited
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to the I/O interface with the Cuda MCU. I therefore decided to put VIA
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2019-08-28 00:39:29 +00:00
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emulation code here.
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Cuda MCU is a multipurpose IC built around a custom version of the Motorola
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MC68HC05 microcontroller. It provides several functions including:
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- Apple Desktop Bus (ADB) master
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- I2C bus master
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- Realtime clock (RTC)
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2019-09-21 12:54:53 +00:00
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- parameter RAM (first generation of the Power Macintosh)
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2019-08-28 00:39:29 +00:00
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- power management
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MC68HC05 doesn't provide any dedicated hardware for serial communication
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protocols. All signals required for ADB and I2C will be generated by Cuda
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firmware using bit banging (https://en.wikipedia.org/wiki/Bit_banging).
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*/
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2019-08-27 12:14:12 +00:00
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#ifndef VIACUDA_H
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#define VIACUDA_H
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2021-10-23 18:17:47 +00:00
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#include <devices/common/adb/adb.h>
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#include <devices/common/hwcomponent.h>
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2022-01-10 16:42:24 +00:00
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#include <devices/common/hwinterrupt.h>
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2021-10-23 18:17:47 +00:00
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#include <devices/common/i2c/i2c.h>
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#include <devices/common/nvram.h>
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2021-10-13 22:01:30 +00:00
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#include <memory>
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2020-03-14 13:23:46 +00:00
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2022-01-10 16:42:24 +00:00
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#define VIA_CLOCK_HZ 783360
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2019-08-27 12:14:12 +00:00
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/** VIA register offsets. */
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enum {
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VIA_B = 0x00, /* input/output register B */
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VIA_A = 0x01, /* input/output register A */
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VIA_DIRB = 0x02, /* direction B */
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VIA_DIRA = 0x03, /* direction A */
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VIA_T1CL = 0x04, /* low-order timer 1 counter */
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VIA_T1CH = 0x05, /* high-order timer 1 counter */
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VIA_T1LL = 0x06, /* low-order timer 1 latches */
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VIA_T1LH = 0x07, /* high-order timer 1 latches */
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VIA_T2CL = 0x08, /* low-order timer 2 latches */
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VIA_T2CH = 0x09, /* high-order timer 2 counter */
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VIA_SR = 0x0A, /* shift register */
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VIA_ACR = 0x0B, /* auxiliary control register */
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VIA_PCR = 0x0C, /* periheral control register */
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VIA_IFR = 0x0D, /* interrupt flag register */
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VIA_IER = 0x0E, /* interrupt enable register */
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VIA_ANH = 0x0F, /* input/output register A, no handshake */
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};
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2022-01-10 16:42:24 +00:00
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/** VIA interrupt flags */
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enum {
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VIA_IF_CA2 = 1 << 0,
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VIA_IF_CA1 = 1 << 1,
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VIA_IF_SR = 1 << 2,
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VIA_IF_CB2 = 1 << 3,
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VIA_IF_CB1 = 1 << 4,
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VIA_IF_T2 = 1 << 5,
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VIA_IF_T1 = 1 << 6
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};
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2022-01-21 10:08:32 +00:00
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enum class ViaLine {
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CA1,
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CA2,
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CB1,
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CB2
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};
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2019-09-21 12:54:53 +00:00
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/** Cuda communication signals. */
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enum {
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CUDA_TIP = 0x20, /* transaction in progress: 0 - true, 1 - false */
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CUDA_BYTEACK = 0x10, /* byte acknowledge: 0 - true, 1 - false */
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CUDA_TREQ = 0x08 /* Cuda requests transaction from host */
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};
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2019-10-07 01:18:18 +00:00
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/** Cuda packet types. */
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enum {
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CUDA_PKT_ADB = 0,
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CUDA_PKT_PSEUDO = 1,
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CUDA_PKT_ERROR = 2,
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CUDA_PKT_TICK = 3,
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CUDA_PKT_POWER = 4
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};
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2019-09-21 12:54:53 +00:00
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/** Cuda pseudo commands. */
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enum {
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2021-11-10 14:56:50 +00:00
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CUDA_WARM_START = 0x00, /* warm start */
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2020-05-12 18:55:45 +00:00
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CUDA_START_STOP_AUTOPOLL = 0x01, /* start/stop device auto-polling */
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2021-10-17 20:31:54 +00:00
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CUDA_READ_MCU_MEM = 0x02, /* read internal Cuda memory */
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2021-11-10 14:56:50 +00:00
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CUDA_GET_REAL_TIME = 0x03, /* get real time */
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2020-05-12 18:55:45 +00:00
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CUDA_READ_PRAM = 0x07, /* read parameter RAM */
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2021-10-17 20:31:54 +00:00
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CUDA_WRITE_MCU_MEM = 0x08, /* write internal Cuda memory */
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2021-11-10 14:56:50 +00:00
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CUDA_SET_REAL_TIME = 0x09, /* set real time */
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CUDA_POWER_DOWN = 0x0A, /* power down system */
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2020-05-12 18:55:45 +00:00
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CUDA_WRITE_PRAM = 0x0C, /* write parameter RAM */
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2021-11-10 14:56:50 +00:00
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CUDA_MONO_STABLE_RESET = 0x0D, /* mono stable reset */
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CUDA_RESTART_SYSTEM = 0x11, /* restart system */
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CUDA_FILE_SERVER_FLAG = 0x13, /* set file server flag */
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2020-05-12 18:55:45 +00:00
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CUDA_SET_AUTOPOLL_RATE = 0x14, /* set auto-polling rate */
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CUDA_GET_AUTOPOLL_RATE = 0x16, /* get auto-polling rate */
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2021-11-10 14:56:50 +00:00
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CUDA_SET_DEVICE_LIST = 0x19, /* set device list */
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CUDA_GET_DEVICE_LIST = 0x1A, /* get device list */
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CUDA_ONE_SECOND_MODE = 0x1B, /* one second interrupt mode */
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2020-05-12 18:55:45 +00:00
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CUDA_READ_WRITE_I2C = 0x22, /* read/write I2C device */
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CUDA_COMB_FMT_I2C = 0x25, /* combined format I2C transaction */
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CUDA_OUT_PB0 = 0x26, /* output one bit to Cuda's PB0 line */
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2019-09-21 12:54:53 +00:00
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};
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2019-10-07 01:18:18 +00:00
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/** Cuda error codes. */
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enum {
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2020-03-15 12:28:35 +00:00
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CUDA_ERR_BAD_PKT = 1, /* invalid packet type */
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CUDA_ERR_BAD_CMD = 2, /* invalid pseudo command */
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CUDA_ERR_BAD_SIZE = 3, /* invalid packet size */
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2021-10-13 22:01:30 +00:00
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CUDA_ERR_BAD_PAR = 4, /* invalid parameter */
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2020-03-15 12:28:35 +00:00
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CUDA_ERR_I2C = 5 /* invalid I2C data or no acknowledge */
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2019-10-07 01:18:18 +00:00
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};
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2022-02-19 22:22:21 +00:00
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#define CUDA_IN_BUF_SIZE 256
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2021-10-17 20:31:54 +00:00
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/** PRAM addresses within Cuda's internal memory */
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#define CUDA_PRAM_START 0x100 // starting address of PRAM
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#define CUDA_PRAM_END 0x1FF // last byte of PRAM
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#define CUDA_ROM_START 0xF00 // starting address of ROM containing Cuda FW
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/** Latest Cuda Firmware version. */
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#define CUDA_FW_VERSION_MAJOR 0x0002
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#define CUDA_FW_VERSION_MINOR 0x0029
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2019-09-21 12:54:53 +00:00
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2020-05-12 18:55:45 +00:00
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class ViaCuda : public HWComponent, public I2CBus {
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2019-08-27 12:14:12 +00:00
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public:
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2020-01-15 17:15:08 +00:00
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ViaCuda();
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2021-10-13 22:01:30 +00:00
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~ViaCuda() = default;
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2019-08-27 12:14:12 +00:00
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2022-07-17 03:28:05 +00:00
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static std::unique_ptr<HWComponent> create() {
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return std::unique_ptr<ViaCuda>(new ViaCuda());
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}
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2022-01-21 11:37:47 +00:00
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// HWComponent methods
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int device_postinit();
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2019-08-27 12:14:12 +00:00
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uint8_t read(int reg);
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void write(int reg, uint8_t value);
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2022-01-21 10:08:32 +00:00
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void assert_ctrl_line(ViaLine line);
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2022-08-27 15:34:05 +00:00
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#ifdef DEBUG_CPU_INT
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void assert_int(uint8_t flags);
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#endif
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2019-08-27 12:14:12 +00:00
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private:
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2022-01-10 16:42:24 +00:00
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// VIA virtual HW registers
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uint8_t via_regs[16];
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2022-01-26 15:45:21 +00:00
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float via_clk_dur; // one VIA clock duration = 1,27655 us
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2022-01-10 16:42:24 +00:00
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// VIA internal state
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uint32_t sr_timer_id = 0;
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bool sr_timer_on = false;
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2022-02-13 02:02:17 +00:00
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// timer 1 state
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bool t1_active;
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uint16_t t1_counter;
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uint32_t t1_timer_id = 0;
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uint64_t t1_start_time = 0;
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// timer 2 state
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2022-01-10 16:42:24 +00:00
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bool t2_active;
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2022-02-13 02:02:17 +00:00
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uint16_t t2_counter;
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uint32_t t2_timer_id = 0;
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uint64_t t2_start_time = 0;
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2022-01-10 16:42:24 +00:00
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2022-02-13 02:02:17 +00:00
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// VIA interrupt related stuff
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2022-01-10 16:42:24 +00:00
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InterruptCtrl* int_ctrl;
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uint32_t irq_id;
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2022-02-13 02:02:17 +00:00
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uint8_t _via_ifr;
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uint8_t _via_ier;
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2022-08-24 11:08:24 +00:00
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uint8_t old_ifr = 0;
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2019-08-27 12:14:12 +00:00
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2019-09-21 12:54:53 +00:00
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/* Cuda state. */
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2022-01-10 16:42:24 +00:00
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uint8_t old_tip;
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uint8_t old_byteack;
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uint8_t treq;
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2022-02-19 22:22:21 +00:00
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uint8_t in_buf[CUDA_IN_BUF_SIZE];
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2022-01-10 16:42:24 +00:00
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int32_t in_count;
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uint8_t out_buf[16];
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int32_t out_count;
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int32_t out_pos;
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uint8_t poll_rate;
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int32_t real_time = 0;
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bool file_server;
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2021-11-10 14:56:50 +00:00
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uint16_t device_mask = 0;
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2019-09-21 12:54:53 +00:00
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2021-10-17 20:31:54 +00:00
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bool is_open_ended; // true if current transaction is open-ended
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uint8_t curr_i2c_addr; // current I2C address
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uint8_t cur_pram_addr; // current PRAM address, range 0...FF
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2020-03-15 12:28:35 +00:00
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void (ViaCuda::*out_handler)(void);
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void (ViaCuda::*next_out_handler)(void);
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2022-01-10 16:42:24 +00:00
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std::unique_ptr<NVram> pram_obj;
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std::unique_ptr<ADB_Bus> adb_bus;
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2020-01-13 03:31:10 +00:00
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2022-01-10 16:42:24 +00:00
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// VIA methods
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void print_enabled_ints(); // print enabled VIA interrupts and their sources
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void init_ints();
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void update_irq();
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void assert_sr_int();
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2022-02-13 02:02:17 +00:00
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void assert_t1_int();
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2022-01-10 16:42:24 +00:00
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void assert_t2_int();
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void schedule_sr_int(uint64_t timeout_ns);
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2022-02-13 02:02:17 +00:00
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uint16_t calc_counter_val(const uint16_t last_val, const uint64_t& last_time);
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2019-09-21 12:54:53 +00:00
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2022-01-10 16:42:24 +00:00
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// CUDA methods
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void cuda_init();
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2020-03-04 14:46:51 +00:00
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bool ready();
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void write(uint8_t new_state);
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void response_header(uint32_t pkt_type, uint32_t pkt_flag);
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void error_response(uint32_t error);
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void process_packet();
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2020-03-05 00:12:27 +00:00
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void process_adb_command(uint8_t cmd_byte, int data_count);
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2020-03-04 14:46:51 +00:00
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void pseudo_command(int cmd, int data_count);
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2019-10-07 01:18:18 +00:00
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2020-03-15 12:28:35 +00:00
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void null_out_handler(void);
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2021-10-13 22:01:30 +00:00
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void pram_out_handler(void);
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2020-03-15 12:28:35 +00:00
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void out_buf_handler(void);
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void i2c_handler(void);
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2019-10-07 01:18:18 +00:00
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/* I2C related methods */
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2020-03-04 14:46:51 +00:00
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void i2c_simple_transaction(uint8_t dev_addr, const uint8_t* in_buf, int in_bytes);
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2020-05-12 18:55:45 +00:00
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void i2c_comb_transaction(
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uint8_t dev_addr, uint8_t sub_addr, uint8_t dev_addr1, const uint8_t* in_buf, int in_bytes);
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2019-08-27 12:14:12 +00:00
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};
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#endif /* VIACUDA_H */
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