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https://github.com/dingusdev/dingusppc.git
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All remaining 601 opcodes implemented
Plus adjustments to twi, bclr, and bcctr.
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dingusdev
parent
1543acc696
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11b1623a69
@ -84,6 +84,21 @@ const char* opc_muldivs[16] = { /* multiply and division instructions */
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"", "", "divwu", "divw"
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};
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const char* opc_shft_reg[32]{ /* Regular shift instructions */
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"slw", "", "", "", "slq", "sliq", "sllq", "slliq",
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"", "", "", "", "", "", "", "",
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"srw", "", "", "", "srq", "sriq", "srlq", "srliq",
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"sraw", "srawi", "", "", "sraq", "sraiq", "", ""
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};
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const char* opc_shft_ext[32]{ /* Extended shift instructions (601 only) */
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"", "", "", "", "sle", "", "sleq", "",
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"", "", "", "", "", "", "", "",
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"rrib", "", "", "", "sre", "", "sreq", "",
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"", "", "", "", "srea", "", "", ""
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};
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const char* opc_int_ldst[16] = { /* integer load and store instructions */
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"lwz", "lwzu", "lbz", "lbzu", "stw", "stwu", "stb", "stbu", "lhz", "lhzu",
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"lha", "lhau", "sth", "sthu", "lmw", "stmw"
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@ -185,6 +200,9 @@ void opc_illegal(PPCDisasmContext* ctx)
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void opc_twi(PPCDisasmContext* ctx)
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{
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char opcode[10] = "";
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auto to = (ctx->instr_code >> 21) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
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@ -192,21 +210,41 @@ void opc_twi(PPCDisasmContext* ctx)
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if (ctx->simplified) {
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switch (to) {
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case 1:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twlgti", ra, imm);
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strcpy(opcode, "twlgti");
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break;
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case 2:
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strcpy(opcode, "twllti");
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break;
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case 4:
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strcpy(opcode, "tweqi");
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break;
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case 5:
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strcpy(opcode, "twlgei");
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break;
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case 6:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twllei", ra, imm);
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strcpy(opcode, "twllei");
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break;
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case 8:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twgti", ra, imm);
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strcpy(opcode, "twgti");
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break;
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case 12:
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strcpy(opcode, "twgei");
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break;
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case 16:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twlti", ra, imm);
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strcpy(opcode, "twlti");
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break;
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case 20:
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", "twlei", ra, imm);
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strcpy(opcode, "twlei");
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break;
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case 24:
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strcpy(opcode, "twnei");
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break;
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default:
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opc_illegal(ctx);
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return;
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}
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ctx->instr_str = my_sprintf("%-8sr%d, 0x%08X", opcode, ra, imm);
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}
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else {
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ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%08X", "twi", to, ra, imm);
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@ -321,6 +359,20 @@ void opc_rlwinm(PPCDisasmContext* ctx)
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fmt_rotateop(ctx->instr_str, "rlwinm", rs, ra, sh, mb, me, true);
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}
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void opc_rlmi(PPCDisasmContext* ctx)
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{
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto sh = (ctx->instr_code >> 11) & 0x1F;
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auto mb = (ctx->instr_code >> 6) & 0x1F;
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auto me = (ctx->instr_code >> 1) & 0x1F;
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if (ctx->instr_code & 1)
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fmt_rotateop(ctx->instr_str, "rlmi.", rs, ra, sh, mb, me, true);
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else
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fmt_rotateop(ctx->instr_str, "rlmi", rs, ra, sh, mb, me, true);
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}
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void opc_rlwnm(PPCDisasmContext* ctx)
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{
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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@ -801,21 +853,52 @@ void opc_group31(PPCDisasmContext* ctx)
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return;
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case 0x18: /* Shifting instructions */
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if (index == 0)
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fmt_threeop(ctx->instr_str, "slw", rs, ra, rb);
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else if (index == 16)
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fmt_threeop(ctx->instr_str, "srw", rs, ra, rb);
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else if (index == 24)
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fmt_threeop(ctx->instr_str, "sraw", rs, ra, rb);
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else if (index == 25)
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fmt_threeop_uimm(ctx->instr_str, "srawi", rs, ra, rb);
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strcpy(opcode, opc_shft_reg[index]);
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if (rc_set)
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strcat(opcode, ".");
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switch (index) {
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case 0: case 4: case 6: case 16:
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case 20: case 22: case 24: case 28:
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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case 5: case 7: case 21: case 23:
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case 25: case 29:
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fmt_threeop_uimm(ctx->instr_str, opcode, rs, ra, rb);
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default:
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opc_illegal(ctx);
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}
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return;
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case 0x19: /* (Extended) Shifting instructions - 601 only*/
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strcpy(opcode, opc_shft_ext[index]);
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if (rc_set)
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strcat(opcode, ".");
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switch (index) {
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case 4: case 6: case 16:
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case 20: case 22: case 28:
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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default:
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opc_illegal(ctx);
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}
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return;
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case 0x1A: /* Byte sign extend instructions */
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if (index == 28)
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fmt_twoop(ctx->instr_str, "extsh", rs, ra);
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strcpy(opcode, "extsh");
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else if (index == 29)
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fmt_twoop(ctx->instr_str, "extsb", rs, ra);
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strcpy(opcode, "extsb");
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if (rc_set)
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strcat(opcode, ".");
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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return;
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case 0x1C: /* logical instructions */
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@ -879,7 +962,7 @@ void opc_group31(PPCDisasmContext* ctx)
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else
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "cmp", rs, ra, rb);
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break;
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case 4:
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case 4: /* tw */
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if (rc_set)
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opc_illegal(ctx);
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else
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@ -896,6 +979,14 @@ void opc_group31(PPCDisasmContext* ctx)
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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break;
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case 29: /* maskg */
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strcpy(opcode, "maskg");
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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break;
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case 32: /* cmpl */
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if (rc_set)
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opc_illegal(ctx);
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@ -917,6 +1008,14 @@ void opc_group31(PPCDisasmContext* ctx)
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case 146: /* mtmsr */
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fmt_oneop(ctx->instr_str, "mtmsr", rs);
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break;
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case 277: /* lscbx */
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strcpy(opcode, "lscbx");
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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break;
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case 339: /* mfspr */
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if (ctx->simplified) {
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switch (ref_spr) {
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@ -955,9 +1054,25 @@ void opc_group31(PPCDisasmContext* ctx)
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case 512: /* mcrxr */
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ctx->instr_str = my_sprintf("%-8scrf%d", "mcrxr", (rs >> 2));
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break;
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case 531: /* clcs */
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strcpy(opcode, "clcs");
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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break;
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case 533: /* lswx */
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fmt_threeop_simm(ctx->instr_str, "lswx", rs, ra, rb);
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break;
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case 541: /* maskir */
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strcpy(opcode, "maskir");
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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return;
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case 597: /* lswi */
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fmt_threeop_simm(ctx->instr_str, "lswi", rs, ra, rb);
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break;
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@ -1421,7 +1536,7 @@ static std::function<void(PPCDisasmContext*)> OpcodeDispatchTable[64] = {
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opc_ar_im, power_dozi, opc_cmp_i_li, opc_cmp_i_li,
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opc_ar_im, opc_ar_im, opc_ar_im, opc_ar_im,
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opc_bcx, opc_sc, opc_bx, opc_group19,
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opc_rlwimi, opc_rlwinm, opc_illegal, opc_rlwnm,
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opc_rlwimi, opc_rlwinm, opc_rlmi, opc_rlwnm,
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opc_bool_im, opc_bool_im, opc_bool_im, opc_bool_im,
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opc_bool_im, opc_bool_im, opc_illegal, opc_group31,
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opc_intldst, opc_intldst, opc_intldst, opc_intldst,
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