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https://github.com/dingusdev/dingusppc.git
synced 2024-12-23 21:29:28 +00:00
ppcdisasm: fix bcctr and bclr instructions.
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parent
4ecc48a6cc
commit
1543acc696
@ -36,11 +36,11 @@ const char* bx_mnem[4] = {
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};
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const char* bclrx_mnem[2] = {
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"bclr", "bclrl"
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"blr", "blrl"
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};
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const char* bcctrx_mnem[2] = {
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"bcctr", "bcctrl"
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"bctr", "bctrl"
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};
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const char* br_cond[8] = { /* simplified branch conditions */
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@ -376,7 +376,7 @@ void opc_bool_im(PPCDisasmContext* ctx)
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if (ctx->simplified) {
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if (index == 0) {
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if (imm == 0 && !ra && !rs && !imm) { /* unofficial, produced by IDA */
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ctx->instr_str = "nop";
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ctx->instr_str = my_sprintf("%-8s", "nop");
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return;
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}
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}
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@ -482,12 +482,16 @@ void opc_bcctrx(PPCDisasmContext* ctx)
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{
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uint32_t bo, bi, cr;
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char opcode[10] = "b";
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char operands[10] = "";
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char operands[4] = "";
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bo = (ctx->instr_code >> 21) & 0x1F;
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bi = (ctx->instr_code >> 16) & 0x1F;
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cr = bi >> 2;
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if (!(bo & 4)) { /* bcctr with BO[2] = 0 is invalid */
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opc_illegal(ctx);
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}
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if (!ctx->simplified || ((bo & 0x10) && bi) ||
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(((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
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generic_bcctrx(ctx, bo, bi);
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@ -495,7 +499,45 @@ void opc_bcctrx(PPCDisasmContext* ctx)
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}
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if ((bo & 0x14) == 0x14) {
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ctx->instr_str = my_sprintf("%-8s0x%08X", bcctrx_mnem[0]);
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ctx->instr_str = my_sprintf("%-8s", bcctrx_mnem[ctx->instr_code & 1]);
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return;
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}
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strcat(opcode, br_cond[((bo >> 1) & 4) | (bi & 3)]);
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strcat(opcode, "ctr");
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if (cr) {
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strcat(operands, "cr0");
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operands[2] = cr + '0';
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}
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if (ctx->instr_code & 1) {
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strcat(opcode, "l"); /* add suffix "l" if the LK bit is set */
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}
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if (bo & 1) { /* incorporate prediction bit if set */
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strcat(opcode, "+");
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}
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ctx->instr_str = my_sprintf("%-8s%s", opcode, operands);
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}
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void opc_bclrx(PPCDisasmContext* ctx)
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{
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uint32_t bo, bi, cr;
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char opcode[10] = "b";
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char operands[12] = "";
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bo = (ctx->instr_code >> 21) & 0x1F;
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bi = (ctx->instr_code >> 16) & 0x1F;
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cr = bi >> 2;
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if (!ctx->simplified || ((bo & 0x10) && bi) ||
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(((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
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generic_bclrx(ctx, bo, bi);
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return;
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}
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if ((bo & 0x14) == 0x14) {
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ctx->instr_str = my_sprintf("%-8s", bclrx_mnem[ctx->instr_code & 1]);
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return;
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}
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@ -509,77 +551,26 @@ void opc_bcctrx(PPCDisasmContext* ctx)
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operands[4] = cr + '0';
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}
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strcat(operands, br_cond[4 + (bi & 3)]);
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strcat(operands, ", ");
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}
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}
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else { /* CTR ignored */
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strcat(opcode, br_cond[((bo >> 1) & 4) | (bi & 3)]);
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if (cr) {
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strcat(operands, "cr0, ");
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strcat(operands, "cr0");
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operands[2] = cr + '0';
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}
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}
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strcat(opcode, "lr");
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if (ctx->instr_code & 1) {
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strcat(opcode, "l"); /* add suffix "l" if the LK bit is set */
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}
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if (bo & 1) { /* incorporate prediction bit if set */
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strcat(opcode, (ctx->instr_code & 0x8000) ? "-" : "+");
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strcat(opcode, "+");
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}
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ctx->instr_str = my_sprintf("%-8s%s0x%08X", opcode, operands);
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}
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void opc_bclrx(PPCDisasmContext* ctx)
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{
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uint32_t bo, bi, cr;
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char opcode[10] = "b";
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char operands[10] = "";
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bo = (ctx->instr_code >> 21) & 0x1F;
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bi = (ctx->instr_code >> 16) & 0x1F;
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cr = bi >> 2;
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if (!ctx->simplified || ((bo & 0x10) && bi) ||
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(((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
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generic_bclrx(ctx, bo, bi);
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return;
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}
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if ((bo & 0x14) == 0x14) {
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ctx->instr_str = my_sprintf("%-8s0x%08X", bclrx_mnem[0]);
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return;
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}
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if (!(bo & 4)) {
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strcat(opcode, "d");
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strcat(opcode, (bo & 2) ? "z" : "nz");
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if (!(bo & 0x10)) {
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strcat(opcode, (bo & 8) ? "tlr" : "flr");
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if (cr) {
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strcat(operands, "4*cr0+");
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operands[4] = cr + '0';
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}
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strcat(operands, br_cond[4 + (bi & 3)]);
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strcat(operands, ", ");
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}
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}
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else { /* CTR ignored */
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strcat(opcode, br_cond[((bo >> 1) & 4) | (bi & 3)]);
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if (cr) {
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strcat(operands, "cr0, ");
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operands[2] = cr + '0';
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}
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}
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if (ctx->instr_code & 1) {
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strcat(opcode, "l"); /* add suffix "l" if the LK bit is set */
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}
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if (bo & 1) { /* incorporate prediction bit if set */
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strcat(opcode, (ctx->instr_code & 0x8000) ? "-" : "+");
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}
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ctx->instr_str = my_sprintf("%-8s%s0x%08X", opcode, operands);
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ctx->instr_str = my_sprintf("%-8s%s", opcode, operands);
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}
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void opc_bx(PPCDisasmContext* ctx)
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@ -597,7 +588,7 @@ void opc_ori(PPCDisasmContext* ctx)
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auto imm = ctx->instr_code & 0xFFFF;
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if (!ra && !rs && !imm && ctx->simplified) {
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ctx->instr_str = "nop";
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ctx->instr_str = my_sprintf("%-8s", "nop");
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return;
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}
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if (imm == 0 && ctx->simplified) { /* inofficial, produced by IDA */
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@ -7,6 +7,50 @@
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0xFFF03008,0x48000355,bl,0xFFF0335C
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0xFFF03000,0x4280035C,b,0xFFF0335C
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# bcctr variants with simplified mnemonics
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0xFFF03000,0x4E800420,bctr
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0xFFF03000,0x4E800421,bctrl
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0xFFF03000,0x4C820420,bnectr
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0xFFF03000,0x4C820421,bnectrl
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0xFFF03000,0x4C960420,bnectr,cr5
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0xFFF03000,0x4C920421,bnectrl,cr4
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0xFFF03000,0x4D980420,bltctr,cr6
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0xFFF03000,0x4C9D0420,blectr,cr7
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0xFFF03000,0x4D820420,beqctr
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0xFFF03000,0x4D960420,beqctr,cr5
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0xFFF03000,0x4CA80420,bgectr+,cr2
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0xFFF03000,0x4C980421,bgectrl,cr6
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0xFFF03000,0x4D810420,bgtctr
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0xFFF03000,0x4D850420,bgtctr,cr1
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0xFFF03000,0x4D8B0421,bsoctrl,cr2
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0xFFF03000,0x4C830420,bnsctr
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0xFFF03000,0x4C930420,bnsctr,cr4
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# bclr variants with simplified mnemonics
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0xFFF03000,0x4E800020,blr
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0xFFF03000,0x4E800021,blrl
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0xFFF03000,0x4D800020,bltlr
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0xFFF03000,0x4D840020,bltlr,cr1
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0xFFF03000,0x4C810021,blelrl
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0xFFF03000,0x4C8D0020,blelr,cr3
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0xFFF03000,0x4DA20020,beqlr+
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0xFFF03000,0x4DBE0021,beqlrl+,cr7
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0xFFF03000,0x4CA80020,bgelr+,cr2
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0xFFF03000,0x4DB90020,bgtlr+,cr6
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0xFFF03000,0x4C8A0021,bnelrl,cr2
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0xFFF03000,0x4D930020,bsolr,cr4
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0xFFF03000,0x4C8F0021,bnslrl,cr3
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0xFFF03000,0x4E000020,bdnzlr
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0xFFF03000,0x4E200020,bdnzlr+
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0xFFF03000,0x4E400020,bdzlr
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0xFFF03000,0x4E400021,bdzlrl
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0xFFF03000,0x4E600020,bdzlr+
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0xFFF03000,0x4C000020,bdnzflr,lt
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0xFFF03000,0x4C040020,bdnzflr,4*cr1+lt
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0xFFF03000,0x4C5D0021,bdzflrl,4*cr7+gt
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0xFFF03000,0x4D020020,bdnztlr,eq
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0xFFF03000,0x4D530021,bdztlrl,4*cr4+so
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# conditional branches with simplified mnemonics, primary opcode 0x10
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0xFFF0011C,0x409E2EE4,bne,cr7,0xFFF03000
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0xFFF00100,0x40A60098,bne+,cr1,0xFFF00198
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@ -14,6 +58,7 @@
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0xFFF03004,0x41200054,bdnzt+,lt,0xFFF03058
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0xFFF03004,0x40000054,bdnzf,lt,0xFFF03058
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0xFFF03000,0x4106FFF4,bdnzt,4*cr1+eq,0xFFF02FF4
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0xFFF03000,0x4001558F,bdnzfla,gt,0x0000558C
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# indexed load/store instructions, primary opcode 0x1F
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0xFFF00100,0x7D49F02E,lwzx,r10,r9,r30
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Can't render this file because it contains an unexpected character in line 4 and column 24.
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@ -53,8 +53,7 @@ static vector<PPCDisasmContext> read_test_data()
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/* put instruction mnemonic padded with trailing spaces */
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idisasm << tokens[2];
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if (tokens.size() > 3) // don't pad operand-less instructions
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idisasm << setw(8 - tokens[2].length()) << "";
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idisasm << setw(8 - tokens[2].length()) << "";
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/* now add comma-separated operands */
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for (i = 3; i < tokens.size(); i++) {
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